CN104865517A - Testing and debugging circuit - Google Patents
Testing and debugging circuit Download PDFInfo
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- CN104865517A CN104865517A CN201510324183.7A CN201510324183A CN104865517A CN 104865517 A CN104865517 A CN 104865517A CN 201510324183 A CN201510324183 A CN 201510324183A CN 104865517 A CN104865517 A CN 104865517A
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Abstract
The invention provides a testing and debugging circuit used for testing a tested circuit with a serial interface. The testing and debugging circuit comprises a test input control terminal, a register set and a test output channel, wherein the test input control terminal is connected with the serial interface of the tested circuit; the register set is used for receiving the input of the serial interface to perform assignment, receiving control signals from the test input control terminal, and controlling the tested circuit to enter a test mode according to assignment data and the control signals; and in the test mode, the test output channel corresponding to tested signals is opened according to the assignment of the register set, and high-low voltage signals and current signals are transmission separately. According to the testing and debugging circuit, the number of test signals can be flexibly configured, the structure is simple and the use is convenient, key signals can be debugged and tested to the utmost extent on the basis of not changing an original design and the quality assurance and reliability requirements of an integrated circuit can be met.
Description
Technical field
The application relates to the detection debug circuit in a kind of integrated circuit (IC) design.More particularly, the present invention relates to the detection debug circuit that the circuit-under-test of the such as memory device with serial line interface and so on is tested.
Background technology
At present, the analog simulation in integrated circuit design process, testing authentication method cannot cover whole IC interior institute produced problem.This internal circuit problem is likely embodied in whole integrate circuit function or performance test, and phenomenon is substantially identical.Meanwhile, the particular problem existing for IC interior, such as internal clock cycles is inaccurate, reference voltage value drift etc. is also difficult to location.Therefore, in order to ensure the q&r requirement of integrated circuit, improving testing efficiency, should consider test problem when designing, design is easy to the circuit of test and debugging.
In prior art, along with modern integrated circuits scale is increasing.Although it is more to survey adjustable key signal in design process, also easier with location to the investigation of product problem, too much test lead is drawn, and not only has influence on the integral layout of former chip port, brings trouble also to post-production test board and encapsulation.
Summary of the invention
Therefore, need to provide a kind of circuit of detection debug circuit to memory device without the need to too much test port to detect and debug.Thus, the invention provides a kind of detection debug circuit utilizing the serial line interface control register group realizing circuit measurability of circuit-under-test.
This detection debug circuit comprises: test input control end, is connected with the serial line interface of described circuit-under-test; Parasites Fauna, receives the input of described serial line interface to carry out assignment, and from described test input control end reception control signal, according to described assignment data and described control signal, controls described circuit-under-test and enter test pattern; With test output channel.Wherein under described test pattern, according to the assignment of described Parasites Fauna, the described test output channel corresponding to measured signal is opened.
Above-mentioned detection debug circuit and circuit-under-test share the serial line interface of circuit-under-test, and do not change primary circuit structure or make primary circuit additionally add other structures.
In above-mentioned detection debug circuit, test input control end is by gating or the state turning off control register group; Whether Parasites Fauna enters test pattern according to the strobe state decision-making circuit of test input control end, and be reconfigured by serial line interface, debugged signal is exported to the debugging end of internal circuit, complete debugging, maybe export detected signal to test output channel; Test output channel opens the output channel of detected signal to need the signal detected in circuit during output register group simulation assignment by the control signal of Parasites Fauna.
The conveniently investigation of problem, the input debugging end being analyzed the module of problem by register pair is needed to carry out assignment again, make the electric parameter of output valve or investigation adjust back to default value to carry out the analysis of problem, this process is the assignment of Parasites Fauna to analog module in circuit-under-test.When power supply not power down, by test input control end is dragged down shutoff test pattern, make circuit enter normal operating conditions, now in circuit, the value of the input debugging end of problem module has become the new value composed.
In some embodiments, when test input control end is for turning off, Parasites Fauna exports as powering on default value, and serial line interface performs normal instructions and enters duty; When test input control end is opened, enter test pattern, after the state machine of serial port circuit detects start bit, assignment is again carried out in the debugging position of serial line interface to Parasites Fauna, and the input debugging end of this debugging position to analog module controls.Turn off test pattern after the assignment of debugging position and enter normal operating conditions, now debug according to the adjustable part of assignment to internal analogue circuit of register or detect.
In some embodiments, serial line interface is downloaded into string code at test input control end gating and the effective condition of chip selection signal, after string last position of code is loaded into, by in all string codes write register, assignment is carried out to Parasites Fauna at the rising edge of next clock signal, to realize debugging to internal circuit and detection.
In some embodiments, Parasites Fauna arranges initial value for the fixed configurations of internal analogue circuit module under circuit normal mode and turn off all sense channels when powering on.By test input control end, Parasites Fauna is reconfigured, can test pattern be opened, then assignment is again carried out to corresponding test path control signal, the test signal paths wanting to detect can be opened, the production of monitor signal.
In some embodiments, detect debug circuit and also can comprise decoding scheme, decoding scheme and Parasites Fauna and test output channel and be connected, test opening and shutting off of output channel by decoding scheme control.
In the above-described embodiment, can encapsulate out the test input control end of circuit at unnecessary empty pin for entering test pattern, can ensure to power on correctly completes, and makes chip be in correct duty, the normal use of memory device can not be affected, reduce the design accuracy requirement of mimic channel.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of the detection debug circuit comprising an embodiment of the present invention;
Fig. 2 detects the sequential chart that debug circuit detects the reference voltage of circuit-under-test shown in Fig. 1;
Fig. 3 is the circuit theory diagrams of a kind of implementation of the test output channel detecting debug circuit shown in Fig. 1;
Fig. 4 is the circuit theory diagrams of the another kind of implementation of the test output channel detecting debug circuit shown in Fig. 1.
Embodiment
Below in conjunction with accompanying drawing, embodiments of the present invention are described in further detail.
Fig. 1 is the structured flowchart of the detection debug circuit of an embodiment of the present invention.This circuit utilizes the serial line interface control register group of circuit-under-test, thus can detect circuit-under-test and debug.
As shown in Figure 1, detect debug circuit and comprise test input control end 2, Parasites Fauna 3 and test output channel 4.Wherein, the serial line interface 1 that debug circuit also uses circuit-under-test is detected.In Parasites Fauna, the number of register decides by needing the signal number detecting or debug in circuit-under-test, can be modified as any number as required.Parasites Fauna 3 in the present embodiment is the shift register that 32 registers are linked to be, and is configured to serial input-parallel and exports.
As shown in Figure 1, the serial line interface 1 of circuit-under-test is connected with the Parasites Fauna 3 detecting debug circuit, and the data for being inputted outside input in Parasites Fauna 3 to carry out assignment to the register in Parasites Fauna 3.Test input control end 2 is connected with Parasites Fauna 3, is carried out the state of control register group 3 by the gating of this control end 2 or cut-off signals.Parasites Fauna 3 can be arranged in the digital circuit of circuit-under-test.When test input control end 2 controls as strobe state (high level) according to external signal, circuit-under-test enters test pattern.After entering test pattern, in circuit-under-test, the module of design margin can be adjusted, and needs the key signal carrying out testing to be output.
In addition, the string code that Parasites Fauna 3 inputs by serial line interface 1 reconfigures, thus makes measured signal export test output channel 4 to.Test output channel 4 opens the output channel of measured signal according to the control signal of Parasites Fauna 3, to need the signal detected in circuit during output register group assignment.
As shown in Figure 1, chip selection signal, clock signal and data-signal (namely go here and there code) all input in digital circuit.Serial line interface 1 is downloaded into string code with to Parasites Fauna 3 assignment at test input control end 2 gating and the effective condition of chip selection signal.When serial line interface 1 be loaded into string code last time, at the rising edge of next clock signal by all string codes write Parasites Fauna 3, the state of control register group 3.
When test input control end 2 turns off (low level), Parasites Fauna 3 exports as the default value that powers on, and serial line interface 1 performs normal instructions and enters duty.When test input control end 2 opens (high level), enter test pattern, after start bit being detected, serial line interface 1 pair of Parasites Fauna 3 carries out assignment again, turn off test pattern after assignment and enter normal operating conditions, now can according to the assignment of Parasites Fauna 3 the adjustable part of internal analogue circuit be debugged or be detected.
The figure place of the process required time and register in Parasites Fauna of output valve or parameter being recalled to preset value is also that number is relevant.In the present embodiment, 34 clock period of this process need, comprise first clock period of serial ports clock acquisition to the start bit of serial input, 32 clock period that 32 register assignments need, and last clock period register value being sent to internal circuit.
By the assignment of serial line interface 1, Parasites Fauna 3 can be debugged the internal module of circuit-under-test in a conventional manner, also can open the test channel of measured signal and measured signal be transferred to test output channel 4.
Fig. 2 is the sequential chart of detection reference voltage according to an embodiment of the invention.
During analog module design, key component leaves certain design margin.For mimic channel, comprise the voltage-regulation of charge pump, voltage rising time regulates, precharge time of sense amplifier regulates and sense amplifier reference current adjustment etc.Namely the critical mode control signal that detection signal for whole circuit also can comprise digital circuits section output controls to read and write the key signal such as key signal, test charge pump high pressure, reference voltage, internal clocking, memory cell current, reference memory unit electric current wiped.
As shown in Figure 2, for test benchmark voltage Vref, this detection debug circuit how detected signal value is described.After having powered on, when test input control end 2 gating (high level) and chip selection signal effectively (high level) time, circuit enters test pattern.After the state machine of serial port circuit detects start bit, serial line interface 1 starts Parasites Fauna 3 assignment.
According to the definition of register-bit, only have when the control bit TM_VREF controlling whether detection reference voltage is 1, the test channel of test benchmark voltage just can be opened.After the assignment of Parasites Fauna 3 is terminated, turn off test input control end and namely exit test pattern.Circuit-under-test enters normal operating conditions and carries out read operation.After reference voltage starts, will from test output terminal 211 output reference voltage value.
Fig. 3 is the circuit theory diagrams of a kind of implementation of testing output channel in the present invention.Test output channel in this circuit diagram and export high-voltage signal.Wherein, NAND28, NAND236 are two input nand gates, and INV58, INV59, INV25 are phase inverters, and HVINV24, HVINV26 are high pressure phase inverter, and M71 is nmos device, and M73, M74 are PMOS device.This circuit carries out the outer survey of high pressure and outer filling when carrying out erasing and write operation.When high pressure is surveyed, by the unlatching of Hi-pot test output channel, test out the high tension voltage value that internal charge pump produces outward; When high pressure is filled with, feed high-voltage value by High voltage output passage outward, internal circuit is directly adopted outer to high voltage supply work, and do not adopt internal charge pump to power.It can thus be appreciated that Hi-pot test passage is bidirectional port.
100 ends and 101 ends are control ends of wiping and write operation, and 102 ends are high-pressure channel control end, are connected on the output terminal of Parasites Fauna.The control signal of the digital circuits section output of circuit-under-test inputs to Sheffer stroke gate NAND 28 via phase inverter INV 59 and INV 58 respectively through 100 ends and 101 ends and carries out logical operation, the signal from Parasites Fauna that the result of logical operation and 102 ends input is after the logical operation of Sheffer stroke gate NAND 236, the grid of one tunnel access nmos device M71, the grid of PMOS device M73 is accessed through phase inverter INV 25 and high pressure phase inverter HVINV 24 in another road, the grid of PMOS device M74 is also accessed on another road through phase inverter INV 25 and high pressure phase inverter HVINV 26, with the break-make of this control M71, when transmission channel is not opened, M71 is opened, move M71 drain potential to zero, ensure that M73 and M74 better ends.When M73 and M74 conducting, M71 turns off, and does not affect the conducting of two pipes.Internal port 110 is connected to the drain electrode of PMOS device M73, and outside port 111 is connected to the drain electrode of PMOS device M74.PMOS device M73 is connected the drain electrode of nmos device M71 with the source electrode of M74.When 100 ends or 101 ends and 102 ends simultaneously effectively (high level) time, NAND236 exports as low, now M71 pipe turns off, M73 and M74 pipe is opened, Hi-pot test passage is opened, internal port 111 is communicated with outside port 110, can carry out the outer survey of high pressure by 110 ends and 111 ends to circuit-under-test or fill with outward, i.e. the external output of test signal or the input of external signal.
Fig. 4 is the circuit theory diagrams of the another kind of implementation of testing output channel in the present invention.Test output channel in this circuit and export low-voltage signal or current signal.Wherein NAND 6<0:7> is three input nand gates, and label L EssT.LTssT.LT0:7> represents to have the same Sheffer stroke gate in 8 tunnels, but input end is different.INV 134<0:7>, INV 2<0:3>, INV 3<0:3>, INV 4<0:2>, INV1<0:2>, INV 5, INV 112 are phase inverters, and M23<0:7>, M0<0:2>, M63 are nmos device.201 ~ 204 ends control low-voltage signal test and export.
202 Duan Jing No. tetra-gun stocks INV 2<0:3> and INV 3<0:3> access Sheffer stroke gate NAND 6<0:7>, input four signals from Parasites Fauna, these four signals are four in 32 signals that in the present embodiment, Parasites Fauna exports, and can be arranged voluntarily by user according to circuit requirements.These four signals are inputed to the grid of nmos device M23<0:7> as decoding, the unlatching of 16 passages can be controlled, namely 4 line-16 line code translators are linked to be, as decoding scheme, wherein 8 passages are 8 test channel of nmos device M23<0:7>, remain 8 passages unsettled.
The needs that 201 terminations receipts digital circuits export carry out the signal tested, the test signal arranged in the present embodiment is the number control signal in the circuit-under-tests such as clock signal clk, as erased, progd, ewen, ewds, porb, poweron, ref_en etc., these signals can be arranged according to the demand of different circuit.When a wherein road in 202 end decoding gating nmos device M23<0:7>, the test signal that 201 ends are corresponding outputs to 204 ends.
203 ends can distinguish three signals that receiving register group exports, reference voltage test control signal TM_VBG is set in the present embodiment, inner 1.8V voltage tester control signal TM_1d8 and logic testing control signal TM_LOGIC, via the grid exporting nmos device M0<0:2> after phase inverter INV 4<0:2> and INV1<0:2> respectively to, control gating reference voltage respectively, the grid reading the test channel M0<0:2> of the test signal of bias voltage and the input of 201 ends is opened.
204 ends can input the signal exported from mimic channel and digital circuit corresponding to 203 ends respectively, and the signal inputted according to 203 ends in the present embodiment is reference voltage signal VREF, inner 1.8V voltage signal V1d8 and logical signal LOGIC.Have in above-mentioned three signals of 203 ends inputs one effective time, choose the signal of 204 corresponding ends and tested by test output terminal 211 end.
205 ends and 206 ends control current signal test and export.206 ends are controlled by Parasites Fauna, and when 206 end input signals are effective, the current signal that 205 ends export can be transmitted by nmos device M63, tests at 211 ends.
As can be seen from Fig. 3 and Fig. 4, this circuit only employs detection and the debugging that a test input and maximum two test output detections ends just complete multiple unlike signal, and can by the separately transmission of digital signal, simulating signal, voltage signal and current signal, decrease design technology, structure is simple, easy to use.
The foregoing is only embodiments of the invention, not thereby limit scope of patent protection of the present invention, the present invention additionally can also improve above-mentioned various module, or adopts technically equivalent ones to replace.Such as: the signal in above-mentioned example can replace with other signal according to the situation of actual circuit-under-test.Other modules etc. optimized further can also be increased.Therefore the equivalence change that all utilizations instructions of the present invention and diagramatic content are done, or directly or indirectly apply to other correlative technology fields, be all in like manner all contained in scope that the present invention contains.
Claims (6)
1. detect a debug circuit, for testing the circuit-under-test with serial line interface, described detection debug circuit comprises:
Test input control end, is connected with the serial line interface of described circuit-under-test;
Parasites Fauna, receives the input of described serial line interface to carry out assignment, and from described test input control end reception control signal, according to described assignment data and described control signal, controls described circuit-under-test and enter test pattern; With
Test output channel, wherein
Under described test pattern, according to the assignment of described Parasites Fauna, the described test output channel corresponding to measured signal is opened.
2. detection debug circuit according to claim 1, comprises a described test input control end and maximum two test output detections ends.
3. detection debug circuit according to claim 1 and 2, wherein, when test input control end is effective and chip selection signal is effective, described Parasites Fauna is loaded into the string code be used for described Parasites Fauna assignment by described serial line interface, after string last position of code is loaded into, described in the rising edge of next clock signal, the assignment of register completes, to realize debugging to circuit-under-test and detection.
4. the detection debug circuit according to any one of claim 1-3, wherein, the configuration relevant to described Parasites Fauna assignment comprises:
Power on initial value, for the internal analogue circuit module under circuit-under-test normal mode fixed configurations and turn off all sense channels;
By described test input control end reconfiguring Parasites Fauna, for opening test pattern, the internal module of described circuit-under-test is debugged; With
Again assignment is carried out to corresponding test path control signal, for opening the test channel of measured signal, the production of monitor signal.
5. the detection debug circuit according to any one of claim 1-4, also comprises decoding scheme, and described decoding scheme is connected with described Parasites Fauna and described test output channel, controls opening and shutting off of described test output channel by described decoding scheme.
6. one kind has the circuit of serial line interface, comprise digital circuit blocks and analog module, and the detection debug circuit according to any one of claim 1-5, wherein said Parasites Fauna is included in described digital circuit blocks, described analog module is connected between described Parasites Fauna and described test output channel, and Signal transmissions to the described test output channel of described Parasites Fauna carries out debugging and detecting.
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| CN201510324183.7A CN104865517B (en) | 2015-06-12 | 2015-06-12 | Detect debug circuit |
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| CN201510324183.7A CN104865517B (en) | 2015-06-12 | 2015-06-12 | Detect debug circuit |
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| CN104865517A true CN104865517A (en) | 2015-08-26 |
| CN104865517B CN104865517B (en) | 2018-01-02 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117236239A (en) * | 2023-11-10 | 2023-12-15 | 成都翌创微电子有限公司 | Universal connectivity test method, apparatus and medium for digital circuit verification |
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| CN103903651A (en) * | 2012-12-25 | 2014-07-02 | 上海华虹宏力半导体制造有限公司 | Double-line serial port build-in self-test circuit, and communication method thereof |
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| CN1536486A (en) * | 2003-04-04 | 2004-10-13 | 上海华园微电子技术有限公司 | Intelligent card chip with microprocessor capable of making automatic test |
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| CN117236239A (en) * | 2023-11-10 | 2023-12-15 | 成都翌创微电子有限公司 | Universal connectivity test method, apparatus and medium for digital circuit verification |
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