CN104851403A - GOA circuit based on oxide semiconductor thin-film transistor - Google Patents
GOA circuit based on oxide semiconductor thin-film transistor Download PDFInfo
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- CN104851403A CN104851403A CN201510292125.0A CN201510292125A CN104851403A CN 104851403 A CN104851403 A CN 104851403A CN 201510292125 A CN201510292125 A CN 201510292125A CN 104851403 A CN104851403 A CN 104851403A
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- 239000010409 thin film Substances 0.000 title claims abstract description 254
- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 238000012423 maintenance Methods 0.000 claims description 15
- 230000009977 dual effect Effects 0.000 claims description 12
- 230000005540 biological transmission Effects 0.000 claims description 7
- 239000003990 capacitor Substances 0.000 claims description 7
- 230000005611 electricity Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 10
- 239000004973 liquid crystal related substance Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- VEMKTZHHVJILDY-UHFFFAOYSA-N resmethrin Chemical compound CC1(C)C(C=C(C)C)C1C(=O)OCC1=COC(CC=2C=CC=CC=2)=C1 VEMKTZHHVJILDY-UHFFFAOYSA-N 0.000 description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 229960001296 zinc oxide Drugs 0.000 description 2
- 235000014692 zinc oxide Nutrition 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2230/00—Details of flat display driving waveforms
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0404—Matrix technologies
- G09G2300/0408—Integration of the drivers onto the display substrate
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0404—Matrix technologies
- G09G2300/0417—Special arrangements specific to the use of low carrier mobility technology
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/06—Details of flat display driving waveforms
- G09G2310/061—Details of flat display driving waveforms for resetting or blanking
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
- G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
- G11C19/287—Organisation of a multiplicity of shift registers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal (AREA)
- Shift Register Type Memory (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a gate driver on array (GOA) circuit based on an oxide semiconductor thin-film transistor. The electricity leakage can be prevented and reliability of the GOA circuit can be improved. A gate and a source electrode of a fortieth thin-film transistor (T40) in a first pull-down module (400) are in short circuit, thereby avoiding crosstalk current occurrence caused by a GOA unit circuit during an inactive period; a gate and a drain electrode of a seventy-fifth thin-film transistor (T75) in a pull-down holding module (600) are electrically connected to a first node (Q(N)), thereby preventing the influence on pull-down holding of the first node (Q(N)) by a constant-voltage high level (DCH); and a clearing and resetting module (700) is arranged and is used for carrying out clearing and resetting on the first node (Q(N)) before generation of each frame of picture, thereby eliminating the interference on the GOA circuit by residual charges and guaranteeing the normal output and normal picture display of the GOA circuit.
Description
Technical field
The present invention relates to liquid crystal display-driving field, particularly relate to a kind of GOA circuit of based oxide semiconductor thin film transistor (TFT).
Background technology
Liquid crystal display (Liquid Crystal Display, LCD) has that fuselage is thin, power saving, the many merits such as radiationless, be widely used.As: LCD TV, mobile phone, personal digital assistant (PDA), digital camera, computer screen or notebook computer screen etc., occupy an leading position in flat display field.
Liquid crystal display major part on existing market is backlight liquid crystal display, and it comprises display panels and backlight module (backlight module).The principle of work of display panels is at thin-film transistor array base-plate (Thin Film Transistor Array Substrate, TFT Array Substrate) and colored filter substrate (Color Filter, CF) liquid crystal molecule is poured between, and on two plate bases, apply driving voltage to control the sense of rotation of liquid crystal molecule, so that the light refraction of backlight module is out produced picture.
In active liquid crystal display, each pixel is electrically connected a thin film transistor (TFT) (TFT), the grid (Gate) of thin film transistor (TFT) is connected to horizontal scanning line, drain electrode (Drain) is connected to the data line of vertical direction, and source electrode (Source) is then connected to pixel electrode.Horizontal scanning line applies enough voltage, the all TFT be electrically connected on this horizontal scanning line can be made to open, thus signal voltage on data line can writing pixel, controls the penetrability of different liquid crystal and then reaches the effect controlling color and brightness.Gate Driver on Array, is called for short GOA, is utilize the array of existing Thin Film Transistor-LCD (Array) processing procedure to be produced on tft array substrate by grid line-scanning drive circuit, realizes the type of drive of lining by line scan to grid.GOA technology can reduce welding (bonding) operation of external IC, has an opportunity promote production capacity and reduce cost of products, and display panels can be made to be more suitable for making the display product of narrow frame or Rimless.
Along with oxide semiconductor thin-film transistor, as indium gallium zinc oxide (Indium Gallium ZincOxide, IGZO) development of thin film transistor (TFT), the panel periphery integrated circuit of based oxide semiconductor thin film transistor (TFT) also becomes the focus of concern.Although oxide semiconductor has higher carrier mobility, but its threshold voltage value is at about 0V, and the amplitude of oscillation of subthreshold region is less, and the voltage Vgs between the grid of GOA circuit a lot of TFT element when OFF state and source electrode is generally 0V, the design difficulty of the GOA circuit of based oxide semiconductor thin film transistor (TFT) will be increased like this, when some scan drive circuits being applicable to amorphous silicon semiconductor thin film transistor (TFT) are applied to the GOA circuit of based oxide semiconductor thin film transistor (TFT), some functional issues will be there are.
In addition, under the induction and effect of stress of some external factor, oxide semiconductor thin-film transistor sometimes also can produce the trend that threshold voltage reduces toward negative value, the GOA circuit of based oxide semiconductor thin film transistor (TFT) will be directly caused to work like this, such as, at high temperature, the threshold voltage of oxide semiconductor thin-film transistor can move toward negative value, can cause GOA circuit malfunction like this; Equally, under the electric stress effect of some illumination, the threshold voltage of oxide semiconductor thin-film transistor can move toward negative value.Therefore, the GOA circuit designing based oxide semiconductor thin film transistor (TFT) must consider the impact of TFT threshold voltage shift.
Figure 1 shows that a kind of GOA circuit of the existing feasible based oxide semiconductor thin film transistor (TFT) for the problems referred to above, comprise pull-up control module 100, pull-up module 200, the drop-down module 400 of lower transmission module 300, first, bootstrap capacitor module 500 and drop-down maintenance module 600.But still there is certain problem in the GOA circuit of this existing based oxide semiconductor thin film transistor (TFT), such as: set N as positive integer, in N level GOA unit circuit, owing to being provided with the first constant voltage negative potential VSS and the second constant voltage negative potential DCL, there is the problem of crossfire in this N level GOA unit circuit between inaction period; Because the drain electrode of the thin film transistor (TFT) T75 in drop-down maintenance module 600 is electrically connected at constant voltage noble potential DCH, constant voltage noble potential DCH can affect the drop-down maintenance to first node Q (N) between inaction period; In addition, when showing each frame picture, there is residual charge in first node Q (N) place, may affect the normal output of GOA circuit, causes picture to show abnormal.
Summary of the invention
The object of the present invention is to provide a kind of GOA circuit of based oxide semiconductor thin film transistor (TFT), electric leakage can not only be prevented, improve the reliability of GOA circuit, the generation of crossfire can also be avoided, avoid constant voltage noble potential on the impact of the drop-down maintenance of first node, remove residual charge to the interference of GOA circuit, ensure the normal output of GOA circuit and the normal display of picture.
For achieving the above object, the invention provides a kind of GOA circuit of based oxide semiconductor thin film transistor (TFT), comprise multiple GOA unit circuit of cascade, every one-level GOA unit circuit includes: pull-up control module, pull-up module, lower transmission module, the first drop-down module, bootstrap capacitor module and drop-down maintenance module;
If N is positive integer, except first order GOA unit circuit, in N level GOA unit circuit:
Described pull-up control module comprises the 11 thin film transistor (TFT), and the grid of described 11 thin film transistor (TFT) receives the level number of delivering a letter of upper level N-1 level GOA unit circuit, and source electrode is electrically connected at constant voltage noble potential, and drain electrode is electrically connected at first node;
Described pull-up module comprises: the 21 thin film transistor (TFT), and the grid of described 21 thin film transistor (TFT) is electrically connected at first node, and source electrode is electrically connected at should the m group clock signal of N level GOA unit circuit, and drain electrode exports scanning drive signal;
Described lower transmission module comprises: the 22 thin film transistor (TFT), and the grid of described 22 thin film transistor (TFT) is electrically connected at first node, and source electrode is electrically connected at should the m group clock signal of N level GOA unit circuit, the drain electrode output stage number of delivering a letter;
Described first drop-down module comprise the 40 thin film transistor (TFT), with the 41 thin film transistor (TFT); Grid and the source electrode of described 40 thin film transistor (TFT) are all electrically connected at first node, and drain electrode is electrically connected at the drain electrode of the 41 thin film transistor (TFT); The grid input of described 41 thin film transistor (TFT) corresponds to the m+2 group clock signal of lower the two poles of the earth N+2 level GOA unit circuit, source electrode input scanning drive signal;
Described bootstrap capacitor module comprises electric capacity, and one end of described electric capacity is electrically connected at first node, and the other end is electrically connected at scanning drive signal;
Described drop-down maintenance module comprises: a dual phase inverter be made up of multiple thin film transistor (TFT), the 42 thin film transistor (TFT), the 32 thin film transistor (TFT), the 75 thin film transistor (TFT), with the 76 thin film transistor (TFT); The input end of described dual phase inverter is electrically connected at first node, and output terminal is electrically connected at Section Point; The grid of described 42 thin film transistor (TFT) is electrically connected at Section Point, and drain electrode is electrically connected at first node, and source electrode is electrically connected at the 3rd node; The grid of described 32 thin film transistor (TFT) is electrically connected at Section Point, and drain electrode is electrically connected at scanning drive signal, and source electrode is electrically connected at the first constant voltage negative potential; The grid of described 75 thin film transistor (TFT) is all electrically connected at first node with drain electrode, and source electrode is electrically connected at the 3rd node; The grid of described 76 thin film transistor (TFT) is electrically connected at Section Point, and drain electrode is electrically connected at the 3rd node, and source electrode is electrically connected at the second constant voltage negative potential;
Described second constant voltage negative potential is lower than the first constant voltage negative potential;
Each thin film transistor (TFT) is oxide semiconductor thin-film transistor.
The GOA circuit of described based oxide semiconductor thin film transistor (TFT) also comprises one and empties replacement module, for emptying replacement to first node before each frame picture produces.
Optionally, described in empty and reset module and comprise one the 9th thin film transistor (TFT), the grid of described 9th thin film transistor (TFT) access scan start signal, drain electrode is electrically connected at first node, and source electrode is electrically connected at the first constant voltage negative potential.
Optionally, described in empty and reset module and comprise one the 9th thin film transistor (TFT), the grid of described 9th thin film transistor (TFT) access scan start signal, drain electrode is electrically connected at first node, and source electrode is electrically connected at the m group clock signal of corresponding N level GOA unit circuit.
Optionally, described in empty and reset module and comprise one the 9th thin film transistor (TFT), the grid of described 9th thin film transistor (TFT) access reset signal, drain electrode is electrically connected at first node, and source electrode is electrically connected at the m group clock signal of corresponding N level GOA unit circuit; Described reset signal produced before scan start signal.
Optionally, if described clock signal comprises M group altogether, M is the integral multiple of 4, then, as N > M, arrange and empty replacement module in N level GOA unit circuit.
Optionally, in every one-level GOA unit circuit, all setting empties replacement module.
Optionally, described clock signal comprises four groups: first group of clock signal, second group of clock signal, the 3rd group of clock signal and the 4th group of clock signal altogether; When described m group clock signal is the 3rd clock signal, described m+2 group clock signal is first group of clock signal, and when described clock signal is the 4th group of clock signal, described m+2 group clock signal is second group of clock signal; The waveform duty cycle of described four groups of clock signals is 25/75;
Arrange in level V to afterbody GOA unit circuit and empty replacement module.
Described dual phase inverter comprises: the 51 thin film transistor (TFT), and grid and the source electrode of described 51 thin film transistor (TFT) are all electrically connected at constant voltage noble potential, and drain electrode is electrically connected at the 4th node; 52 thin film transistor (TFT), the grid of described 52 thin film transistor (TFT) is electrically connected at first node, and drain electrode is electrically connected at the 4th node, and source electrode is electrically connected at the first constant voltage negative potential; 53 thin film transistor (TFT), the grid of described 53 thin film transistor (TFT) is electrically connected at the 4th node, and source electrode is electrically connected at constant voltage noble potential, and drain electrode is electrically connected at Section Point; 54 thin film transistor (TFT), the grid of described 54 thin film transistor (TFT) is electrically connected at first node, and drain electrode is electrically connected at Section Point, and source electrode is electrically connected at the 5th node; 73 thin film transistor (TFT), the grid of described 73 thin film transistor (TFT) is electrically connected at the 4th node, and source electrode is electrically connected at constant voltage noble potential, and drain electrode is electrically connected at the 5th node; 74 thin film transistor (TFT), the grid of described 74 thin film transistor (TFT) is electrically connected at first node, and source electrode is electrically connected at the second constant voltage negative potential, and drain electrode is electrically connected at the 5th node; Wherein said 51 thin film transistor (TFT), the 52 thin film transistor (TFT), the 53 thin film transistor (TFT), with the 54 thin film transistor (TFT) form main phase inverter, described 73 thin film transistor (TFT), with the 74 thin film transistor (TFT) forms assist phase inverter.
In first order GOA unit circuit, the grid access scan start signal of described 11 thin film transistor (TFT).
Beneficial effect of the present invention: the GOA circuit of a kind of based oxide semiconductor thin film transistor (TFT) provided by the invention, electric leakage can not only be prevented, improve the reliability of GOA circuit, also by avoiding GOA unit circuit to produce crossfire between inaction period the grid of the 40 thin film transistor (TFT) in the first drop-down module and source shorted, avoid constant voltage noble potential on the impact of the drop-down maintenance of first node by the grid of the 75 thin film transistor (TFT) in drop-down maintenance module is all electrically connected at first node with drain electrode, empty replacement module by setting, before each frame picture produces, replacement is emptied to first node, to remove the interference of residual charge to GOA circuit, ensure the normal output of GOA circuit and the normal display of picture.
Accompanying drawing explanation
In order to further understand feature of the present invention and technology contents, refer to following detailed description for the present invention and accompanying drawing, but accompanying drawing only provides reference and explanation use, is not used for being limited the present invention.
In accompanying drawing,
Fig. 1 is a kind of circuit diagram of GOA circuit of existing based oxide semiconductor thin film transistor (TFT);
Fig. 2 is the circuit diagram of the first embodiment of the GOA circuit that the present invention is based on oxide semiconductor thin-film transistor;
Fig. 3 is the circuit diagram of the second embodiment of the GOA circuit that the present invention is based on oxide semiconductor thin-film transistor;
Fig. 4 is the circuit diagram of the 3rd embodiment of the GOA circuit that the present invention is based on oxide semiconductor thin-film transistor;
Fig. 5 is the annexation figure of first order GOA unit circuit in first, second, third embodiment of the GOA circuit that the present invention is based on oxide semiconductor thin-film transistor;
Fig. 6 is the input signal of first, second, third embodiment of the GOA circuit that the present invention is based on oxide semiconductor thin-film transistor and the waveform schematic diagram of key node;
Fig. 7 is the connection configuration diagram of second, third embodiment of the GOA circuit that the present invention is based on oxide semiconductor thin-film transistor;
Fig. 8 is the circuit diagram of the 4th embodiment of the GOA circuit that the present invention is based on oxide semiconductor thin-film transistor;
Fig. 9 is the annexation figure of first order GOA unit circuit in the 4th embodiment of the GOA circuit that the present invention is based on oxide semiconductor thin-film transistor;
Figure 10 is the input signal of the 4th embodiment and the waveform schematic diagram of key node of the GOA circuit that the present invention is based on oxide semiconductor thin-film transistor;
Figure 11 is the connection configuration diagram of the 4th embodiment of the GOA circuit that the present invention is based on oxide semiconductor thin-film transistor.
Embodiment
For further setting forth the technological means and effect thereof that the present invention takes, be described in detail below in conjunction with the preferred embodiments of the present invention and accompanying drawing thereof.
The invention provides a kind of GOA circuit of based oxide semiconductor thin film transistor (TFT).Refer to Fig. 2, for the present invention is based on the circuit diagram of the first embodiment of the GOA circuit of oxide semiconductor thin-film transistor, comprise multiple GOA unit circuit of cascade, every one-level GOA unit circuit includes: pull-up control module 100, pull-up module 200, the drop-down module 400 of lower transmission module 300, first, bootstrap capacitor module 500 and drop-down maintenance module 600.
If N is positive integer, except first order GOA unit circuit, in N level GOA unit circuit:
Described pull-up control module 100 comprises the 11 thin film transistor (TFT) T11, the grid of described 11 thin film transistor (TFT) T11 receives the level number of the delivering a letter ST (N-1) of upper level N-1 level GOA unit circuit, source electrode is electrically connected at constant voltage noble potential DCH, and drain electrode is electrically connected at first node Q (N).
Described pull-up module 200 comprises: the 21 thin film transistor (TFT) T21, the grid of described 21 thin film transistor (TFT) T21 is electrically connected at first node Q (N), source electrode is electrically connected at should m group clock signal C K (m) of N level GOA unit circuit, and drain electrode exports scanning drive signal G (N).
Described lower transmission module 300 comprises: the 22 thin film transistor (TFT) T22, the grid of described 22 thin film transistor (TFT) T22 is electrically connected at first node Q (N), source electrode is electrically connected at should m group clock signal C K (m) of N level GOA unit circuit, the drain electrode output stage number of delivering a letter ST (N).
Described first drop-down module 400 comprise the 40 thin film transistor (TFT) T40, with the 41 thin film transistor (TFT) T41; Grid and the source electrode of described 40 thin film transistor (TFT) T40 are all electrically connected at first node Q (N), and drain electrode is electrically connected at the drain electrode of the 41 thin film transistor (TFT) T41; The grid input of described 41 thin film transistor (TFT) T41 corresponds to the m+2 group clock signal C K (m+2) of lower the two poles of the earth N+2 level GOA unit circuit, source electrode input scanning drive signal G (N).
Described bootstrap capacitor module 500 comprises electric capacity Cb, and one end of described electric capacity Cb is electrically connected at first node Q (N), and the other end is electrically connected at scanning drive signal G (N).
Described drop-down maintenance module 600 comprises: dual phase inverter F, the 42 thin film transistor (TFT) T42 be made up of multiple thin film transistor (TFT), the 32 thin film transistor (TFT) T32, the 75 thin film transistor (TFT) T75, with the 76 thin film transistor (TFT) T76; The input end of described dual phase inverter F is electrically connected at first node Q (N), and output terminal is electrically connected at Section Point P (N); The grid of described 42 thin film transistor (TFT) T42 is electrically connected at Section Point P (N), and drain electrode is electrically connected at first node Q (N), and source electrode is electrically connected at the 3rd node T (N); The grid of described 32 thin film transistor (TFT) T32 is electrically connected at Section Point P (N), and drain electrode is electrically connected at scanning drive signal G (N), and source electrode is electrically connected at the first constant voltage negative potential VSS; The grid of described 75 thin film transistor (TFT) T75 is all electrically connected at first node Q (N) with drain electrode, and source electrode is electrically connected at the 3rd node T (N); The grid of described 76 thin film transistor (TFT) T76 is electrically connected at Section Point P (N), and drain electrode is electrically connected at the 3rd node T (N), and source electrode is electrically connected at the second constant voltage negative potential DCL.Particularly, described dual phase inverter F comprises: the 51 thin film transistor (TFT) T51, and grid and the source electrode of described 51 thin film transistor (TFT) T51 are all electrically connected at constant voltage noble potential DCH, and drain electrode is electrically connected at the 4th node S (N); 52 thin film transistor (TFT) T52, the grid of described 52 thin film transistor (TFT) T52 is electrically connected at first node Q (N), and drain electrode is electrically connected at the 4th node S (N), and source electrode is electrically connected at the first constant voltage negative potential VSS; The grid of the 53 thin film transistor (TFT) T53, described 53 thin film transistor (TFT) T53 is electrically connected at the 4th node S (N), and source electrode is electrically connected at constant voltage noble potential DCH, and drain electrode is electrically connected at Section Point P (N); 54 thin film transistor (TFT) T54, the grid of described 54 thin film transistor (TFT) T54 is electrically connected at first node Q (N), and drain electrode is electrically connected at Section Point P (N), and source electrode is electrically connected at the 5th node K (N); The grid of the 73 thin film transistor (TFT) T73, described 73 thin film transistor (TFT) T73 is electrically connected at the 4th node S (N), and source electrode is electrically connected at constant voltage noble potential DCH, and drain electrode is electrically connected at the 5th node K (N); 74 thin film transistor (TFT) T74, the grid of described 74 thin film transistor (TFT) T74 is electrically connected at first node Q (N), and source electrode is electrically connected at the second constant voltage negative potential DCL, and drain electrode is electrically connected at the 5th node K (N); Wherein said 51 thin film transistor (TFT) T51, the 52 thin film transistor (TFT) T52, the 53 thin film transistor (TFT) T53, with the 54 thin film transistor (TFT) T54 form main phase inverter, described 73 thin film transistor (TFT) T73, with the 74 thin film transistor (TFT) T74 forms assist phase inverter.
Each thin film transistor (TFT) is oxide semiconductor thin-film transistor, and preferably, described oxide semiconductor thin-film transistor is IGZO thin film transistor (TFT).
Especially, refer to Fig. 5, in the first embodiment of the present invention, in first order GOA unit circuit, the grid access scan start signal STV of described 11 thin film transistor (TFT) T11, the described source electrode of the 21 thin film transistor (TFT) T21 and the source electrode of the 22 thin film transistor (TFT) T22 are all electrically connected at first group of clock signal C K (1), the grid input of the 41 thin film transistor (TFT) T41 corresponds to the 3rd group of clock signal C K (3) of lower the two poles of the earth third level GOA unit circuit, source electrode input scanning drive signal G (1).
Please refer to Fig. 2 and Fig. 6, the course of work that the present invention is based on GOA circuit first embodiment of oxide semiconductor thin-film transistor is: self-scanning enabling signal STV starts first order GOA unit circuit, carries out turntable driving step by step successively.Turntable driving proceeds to N level GOA unit circuit, when the level number of the delivering a letter ST (N-1) of upper level N-1 level GOA unit circuit is for noble potential, 11 thin film transistor (TFT) T11 conducting, first node Q (N) is lifted to noble potential by the 11 thin film transistor (TFT) T11 by constant voltage noble potential DCH, and charges to electric capacity Cb.Subsequently, the level number of the delivering a letter ST (N-1) of N-1 level GOA unit circuit transfers electronegative potential to, 11 thin film transistor (TFT) T11 disconnects, first node Q (N) maintains noble potential by electric capacity Cb, makes the 21 thin film transistor (TFT) T21 and the 22 thin film transistor (TFT) T22 conducting.Then, m group clock signal C K (m) corresponding to this N level GOA unit circuit transfers high level to, the drain electrode of the 21 thin film transistor (TFT) T21 exports the scanning drive signal G (N) of noble potential, the drain electrode of the 22 thin film transistor (TFT) T22 exports the level number of the delivering a letter ST (N) of noble potential, simultaneously m group clock signal C K (m) continues to charge to electric capacity Cb by the 21 thin film transistor (TFT) T21, makes first node Q (N) rise to a more noble potential.Then, scanning drive signal G (N) changes electronegative potential into along with m group clock signal C K (m), m+2 group clock signal C K (m+2) corresponding to lower the two poles of the earth N+2 level GOA unit circuit is noble potential, 41 thin film transistor (TFT) T41 and the 40 thin film transistor (TFT) T40 conducting, first node Q (N) is discharged by drop-down module 400, changes electronegative potential into.
The general time slot being noble potential by scanning drive signal G (N) was called between action period.Between action period, because first node Q (N) is noble potential, the source electrode access constant voltage noble potential DCH of the 11 thin film transistor (TFT) T11, therefore first node Q (N) can not produce electric leakage by the 11 thin film transistor (TFT) T11; Simultaneously, because first node Q (N) is noble potential, after dual phase inverter F is anti-phase, obtain Section Point P (N) is electronegative potential, 42 thin film transistor (TFT) T42 and the 32 thin film transistor (TFT) T32 all disconnects, and guarantees the output noble potential that first node Q (N) and scanning drive signal G (N) is stable; The noble potential of first node Q (N) is passed to the source electrode of the 42 thin film transistor (TFT) T42 by the 75 thin film transistor (TFT) T75, therefore first node Q (N) can not produce electric leakage by the 42 thin film transistor (TFT) T42; 41 thin film transistor (TFT) T41 is now off state, and the scanning drive signal G (N) of the source electrode of the 41 thin film transistor (TFT) T41 input noble potential, first node Q (N) also can not be leaked electricity by the tandem paths of the 41 thin film transistor (TFT) T41 and the 40 thin film transistor (TFT) T40.
Between inaction period, namely when first node Q (N) changes electronegative potential into, phase inverter F exports as noble potential, namely Section Point P (N) is noble potential, 42 thin film transistor (TFT) T42, the 32 thin film transistor (TFT) T32 and the equal conducting of the 76 thin film transistor (TFT) T76, first node Q (N) is dragged down further by the 42 thin film transistor (TFT) T42 and the 76 thin film transistor (TFT) T76 and is maintained the second constant voltage negative potential DCL; Scanning drive signal G (N) is dragged down further by the 32 thin film transistor (TFT) T32 and is maintained the first constant voltage negative potential VSS.Now, because the 40 thin film transistor (TFT) T40 have employed secondary body connection, by grid and the source shorted of the 40 thin film transistor (TFT) T40, the gate-source voltage Vgs of described 40 thin film transistor (TFT) T40 equals 0V, compared to existing technology the grid of the 40 thin film transistor (TFT) T40 is connected the scanning drive signal G (N+2) of N+2 level GOA unit circuit, the crossfire caused by the second constant voltage negative potential DCL can be avoided to flow through the 40 thin film transistor (TFT) T40.Drain electrode due to the 75 thin film transistor (TFT) T75 is electrically connected at first node Q (N), the source electrode of the 42 thin film transistor (TFT) T42 is electrically connected at the drain electrode of the 75 thin film transistor (TFT) T75, compared to existing technology the drain electrode of the 75 thin film transistor (TFT) T75 is electrically connected at constant voltage noble potential DCH, constant voltage noble potential DCH impact on first node Q (N) drop-down maintenance between inaction period can be avoided.
Further, described second constant voltage negative potential DCL is set lower than the first constant voltage negative potential VSS, so that carry out separately independent control.When during acting on, first node Q (N) is for noble potential, the 52 thin film transistor (TFT) T52 in the main phase inverter of described dual phase inverter F and the equal conducting of the 54 thin film transistor (TFT) T54, 53 thin film transistor (TFT) T53 disconnects, the 74 thin film transistor (TFT) T74 conducting in auxiliary main phase inverter, 73 thin film transistor (TFT) T73 closes, the current potential of Section Point P (N) is pulled down to the second constant voltage negative potential DCL lower than the first constant voltage negative potential VSS, guarantee the output noble potential that first node Q (N) and scanning drive signal G (N) is stable, when when between inaction period, first node Q (N) is for electronegative potential, the 52 thin film transistor (TFT) T52 in the main phase inverter of described dual phase inverter F and the 54 thin film transistor (TFT) T54 all disconnects, 51 thin film transistor (TFT) T51 and the equal conducting of the 53 thin film transistor (TFT) T53, the 74 thin film transistor (TFT) T74 in auxiliary main phase inverter disconnects, 73 thin film transistor (TFT) T73 conducting, prevent the 54 thin film transistor (TFT) T54 from leaking electricity, the current potential of Section Point P (N) is made to remain on constant voltage noble potential DCH, the electronegative potential of first node Q (N) and scanning drive signal G (N) can be maintained.
Please refer to Fig. 3, Fig. 5, Fig. 6 and Fig. 7, for the present invention is based on the second embodiment of the GOA circuit of oxide semiconductor thin-film transistor, the difference of this second embodiment and the first embodiment is, has set up one and has emptied replacement module 700.Concrete, the described replacement module 700 that empties comprises one the 9th thin film transistor (TFT) T9, the grid access scan start signal STV of described 9th thin film transistor (TFT) T9, drain electrode is electrically connected at first node Q (N), and source electrode is electrically connected at the first constant voltage negative potential VSS.This empties and resets module 700 for utilizing scan start signal STV to empty replacement to first node Q (N) before each frame picture produces, remove residual charge to the interference of GOA circuit, before the first frame picture produces, also can empty first node Q (N) simultaneously, prevent the unsettled impact that GOA circuit is exported of the first frame picture, ensure the normal output of GOA circuit and the normal display of picture.
Especially, it should be noted that, if described clock signal comprises M group altogether, M is the integral multiple of 4, then, as N > M, arrange and empty replacement module 700 in N level GOA unit circuit.Such as, Fig. 6 and Fig. 7 comprises four groups altogether for described clock signal, from level V GOA unit circuit, all arrange to empty in level V to afterbody GOA unit circuit and reset module 700, accordingly, level V to afterbody GOA unit circuit all needs to access and empties for controlling the scan start signal STV resetting module 700; And all do not arrange in the first order to fourth stage GOA unit circuit to empty and reset module 700, only there is first order GOA unit circuit need access scan start signal STV for starting turntable driving.Particularly, described four groups of clock letters are respectively: first group of clock signal C K (1), second group of clock signal C K (2), the 3rd group of clock signal C K (3) and the 4th group of clock signal C K (4); When described m group clock signal C K (m) is the 3rd clock signal C K (3), described m+2 group clock signal C K (m+2) is first group of clock signal C K (1), when described clock signal C K (m) is the 4th group clock signal C K (4), described m+2 group clock signal C K (m+2) is second group of clock signal C K (2); The waveform duty cycle of described four groups of clock signals is 25/75, and to avoid clock signal waveform on the impact of the first drop-down module 400, the waveform at first node Q (N) place is in " convex " font.
In like manner, if described clock signal comprises eight groups altogether, then from the 9th grade of GOA unit circuit, all arrange to empty in the 9th grade to afterbody GOA unit circuit and reset module 700, accordingly, the 9th grade all needs access to empty for controlling the scan start signal STV resetting module 700 to afterbody GOA unit circuit; And all do not arrange in the first order to the 8th grade of GOA unit circuit to empty and reset module 700, only there is first order GOA unit circuit need access scan start signal STV for starting turntable driving.
Remaining circuit structure and the course of work are all identical with the first embodiment, repeat no more herein.
Please refer to Fig. 4, Fig. 5, Fig. 6 and Fig. 7, for the present invention is based on the 3rd embodiment of the GOA circuit of oxide semiconductor thin-film transistor, the difference of the 3rd embodiment and the second embodiment is only, the source electrode of the 9th thin film transistor (TFT) T9 is electrically connected at m group clock signal C K (m) of corresponding N level GOA unit circuit, the benefit done like this can reduce the 9th thin film transistor (TFT) T9 to first node Q (N) effect of leakage between action period.All the other are all identical with the second embodiment, repeat no more herein.
Please refer to Fig. 8, Fig. 9, Figure 10 and Figure 11, for the present invention is based on the 4th embodiment of the GOA circuit of oxide semiconductor thin-film transistor, 4th embodiment arranges equally to empty and resets module 700, with the 3rd embodiment unlike, the described grid resetting the 9th thin film transistor (TFT) T9 in module 700 that empties accesses reset signal Reset, namely the 4th embodiment needs increase by be different from the reset signal Reset of scan start signal STV, and as shown in Figure 10, described reset signal Reset produced before scan start signal STV.In this case, can the first order to the every one-level in afterbody GOA unit circuit all arrange empty reset module 700.
Comprise four groups altogether for described clock signal, as shown in Fig. 9, Figure 11, the access of first order GOA unit circuit for control to empty the reset signal Reset that resets module 700 with for starting the scan start signal STV of turntable driving; The second level empties for controlling the reset signal Reset resetting module 700 to the every one-level access in afterbody GOA unit circuit, can realize equally utilizing reset signal Reset to empty replacement to first node Q (N) before each frame picture produces, remove residual charge to the interference of GOA circuit, before the first frame picture produces, also can empty first node Q (N) simultaneously, prevent the unsettled impact that GOA circuit is exported of the first frame picture, ensure the normal output of GOA circuit and the normal display of picture.
In sum, the GOA circuit of based oxide semiconductor thin film transistor (TFT) of the present invention, electric leakage can not only be prevented, improve the reliability of GOA circuit, also by avoiding GOA unit circuit to produce crossfire between inaction period the grid of the 40 thin film transistor (TFT) in the first drop-down module and source shorted, avoid constant voltage noble potential on the impact of the drop-down maintenance of first node by the grid of the 75 thin film transistor (TFT) in drop-down maintenance module is all electrically connected at first node with drain electrode, empty replacement module by setting, before each frame picture produces, replacement is emptied to first node, to remove the interference of residual charge to GOA circuit, ensure the normal output of GOA circuit and the normal display of picture.
The above; for the person of ordinary skill of the art; can make other various corresponding change and distortion according to technical scheme of the present invention and technical conceive, and all these change and be out of shape the protection domain that all should belong to the accompanying claim of the present invention.
Claims (10)
1. the GOA circuit of a based oxide semiconductor thin film transistor (TFT), it is characterized in that, comprise multiple GOA unit circuit of cascade, every one-level GOA unit circuit includes: pull-up control module (100), pull-up module (200), lower transmission module (300), the first drop-down module (400), bootstrap capacitor module (500) and drop-down maintenance module (600);
If N is positive integer, except first order GOA unit circuit, in N level GOA unit circuit:
Described pull-up control module (100) comprises the 11 thin film transistor (TFT) (T11), the grid of described 11 thin film transistor (TFT) (T11) receives the level number of delivering a letter (ST (N-1)) of upper level N-1 level GOA unit circuit, source electrode is electrically connected at constant voltage noble potential (DCH), and drain electrode is electrically connected at first node (Q (N));
Described pull-up module (200) comprising: the 21 thin film transistor (TFT) (T21), the grid of described 21 thin film transistor (TFT) (T21) is electrically connected at first node (Q (N)), source electrode is electrically connected at should the m group clock signal (CK (m)) of N level GOA unit circuit, and drain electrode exports scanning drive signal (G (N));
Described lower transmission module (300) comprising: the 22 thin film transistor (TFT) (T22), the grid of described 22 thin film transistor (TFT) (T22) is electrically connected at first node (Q (N)), source electrode is electrically connected at should the m group clock signal (CK (m)) of N level GOA unit circuit, the drain electrode output stage number of delivering a letter (ST (N));
Described first drop-down module (400) comprise the 40 thin film transistor (TFT) (T40), with the 41 thin film transistor (TFT) (T41); The grid of described 40 thin film transistor (TFT) (T40) and source electrode are all electrically connected at first node (Q (N)), and drain electrode is electrically connected at the drain electrode of the 41 thin film transistor (TFT) (T41); The grid input of described 41 thin film transistor (TFT) (T41) corresponds to the m+2 group clock signal (CK (m+2)) of lower the two poles of the earth N+2 level GOA unit circuit, source electrode input scanning drive signal (G (N));
Described bootstrap capacitor module (500) comprises electric capacity (Cb), one end of described electric capacity (Cb) is electrically connected at first node (Q (N)), and the other end is electrically connected at scanning drive signal (G (N));
Described drop-down maintenance module (600) comprising: a dual phase inverter (F) be made up of multiple thin film transistor (TFT), the 42 thin film transistor (TFT) (T42), the 32 thin film transistor (TFT) (T32), the 75 thin film transistor (TFT) (T75), with the 76 thin film transistor (TFT) (T76); The input end of described dual phase inverter (F) is electrically connected at first node (Q (N)), and output terminal is electrically connected at Section Point (P (N)); The grid of described 42 thin film transistor (TFT) (T42) is electrically connected at Section Point (P (N)), drain electrode is electrically connected at first node (Q (N)), and source electrode is electrically connected at the 3rd node (T (N)); The grid of described 32 thin film transistor (TFT) (T32) is electrically connected at Section Point (P (N)), drain electrode is electrically connected at scanning drive signal (G (N)), and source electrode is electrically connected at the first constant voltage negative potential (VSS); The grid of described 75 thin film transistor (TFT) (T75) is all electrically connected at first node (Q (N)) with drain electrode, and source electrode is electrically connected at the 3rd node (T (N)); The grid of described 76 thin film transistor (TFT) (T76) is electrically connected at Section Point (P (N)), drain electrode is electrically connected at the 3rd node (T (N)), and source electrode is electrically connected at the second constant voltage negative potential (DCL);
Described second constant voltage negative potential (DCL) is lower than the first constant voltage negative potential (VSS);
Each thin film transistor (TFT) is oxide semiconductor thin-film transistor.
2. the GOA circuit of based oxide semiconductor thin film transistor (TFT) as claimed in claim 1, it is characterized in that, also comprise one and empty replacement module (700), for emptying replacement to first node (Q (N)) before each frame picture produces.
3. the GOA circuit of based oxide semiconductor thin film transistor (TFT) as claimed in claim 2, it is characterized in that, described empty reset module (700) comprise one the 9th thin film transistor (TFT) (T9), grid access scan start signal (STV) of described 9th thin film transistor (TFT) (T9), drain electrode is electrically connected at first node (Q (N)), and source electrode is electrically connected at the first constant voltage negative potential (VSS).
4. the GOA circuit of based oxide semiconductor thin film transistor (TFT) as claimed in claim 2, it is characterized in that, described empty reset module (700) comprise one the 9th thin film transistor (TFT) (T9), grid access scan start signal (STV) of described 9th thin film transistor (TFT) (T9), drain electrode is electrically connected at first node (Q (N)), and source electrode is electrically connected at the m group clock signal (CK (m)) of corresponding N level GOA unit circuit.
5. the GOA circuit of based oxide semiconductor thin film transistor (TFT) as claimed in claim 2, it is characterized in that, described empty reset module (700) comprise one the 9th thin film transistor (TFT) (T9), grid access reset signal (Reset) of described 9th thin film transistor (TFT) (T9), drain electrode is electrically connected at first node (Q (N)), and source electrode is electrically connected at the m group clock signal (CK (m)) of corresponding N level GOA unit circuit; Described reset signal (Reset) produced before scan start signal (STV).
6. the GOA circuit of the based oxide semiconductor thin film transistor (TFT) as described in claim 3 or 4, it is characterized in that, if described clock signal comprises M group altogether, M is the integral multiple of 4, then as N > M, arrange in N level GOA unit circuit and empty replacement module (700).
7. the GOA circuit of based oxide semiconductor thin film transistor (TFT) as claimed in claim 5, is characterized in that, all arranges to empty to reset module (700) in every one-level GOA unit circuit.
8. the GOA circuit of based oxide semiconductor thin film transistor (TFT) as claimed in claim 6, it is characterized in that, described clock signal comprises four groups: first group of clock signal (CK (1)), second group of clock signal (CK (2)), the 3rd group of clock signal (CK (3)) and the 4th group of clock signal (CK (4)) altogether; When described m group clock signal (CK (m)) is the 3rd clock signal (CK (3)), described m+2 group clock signal (CK (m+2)) is first group of clock signal (CK (1)), when described clock signal (CK (m)) is the 4th group of clock signal (CK (4)), described m+2 group clock signal (CK (m+2)) is second group of clock signal (CK (2)); The waveform duty cycle of described four groups of clock signals is 25/75;
Arrange to empty in level V to afterbody GOA unit circuit and reset module (700).
9. the GOA circuit of based oxide semiconductor thin film transistor (TFT) as claimed in claim 1, it is characterized in that, described dual phase inverter (F) comprising: the 51 thin film transistor (TFT) (T51), grid and the source electrode of described 51 thin film transistor (TFT) (T51) are all electrically connected at constant voltage noble potential (DCH), and drain electrode is electrically connected at the 4th node (S (N)); 52 thin film transistor (TFT) (T52), the grid of described 52 thin film transistor (TFT) (T52) is electrically connected at first node (Q (N)), drain electrode is electrically connected at the 4th node (S (N)), and source electrode is electrically connected at the first constant voltage negative potential (VSS); 53 thin film transistor (TFT) (T53), the grid of described 53 thin film transistor (TFT) (T53) is electrically connected at the 4th node (S (N)), source electrode is electrically connected at constant voltage noble potential (DCH), and drain electrode is electrically connected at Section Point (P (N)); 54 thin film transistor (TFT) (T54), the grid of described 54 thin film transistor (TFT) (T54) is electrically connected at first node (Q (N)), drain electrode is electrically connected at Section Point (P (N)), and source electrode is electrically connected at the 5th node (K (N)); 73 thin film transistor (TFT) (T73), the grid of described 73 thin film transistor (TFT) (T73) is electrically connected at the 4th node (S (N)), source electrode is electrically connected at constant voltage noble potential (DCH), and drain electrode is electrically connected at the 5th node (K (N)); 74 thin film transistor (TFT) (T74), the grid of described 74 thin film transistor (TFT) (T74) is electrically connected at first node (Q (N)), source electrode is electrically connected at the second constant voltage negative potential (DCL), and drain electrode is electrically connected at the 5th node (K (N)); Wherein said 51 thin film transistor (TFT) (T51), the 52 thin film transistor (TFT) (T52), the 53 thin film transistor (TFT) (T53), with the 54 thin film transistor (TFT) (T54) form main phase inverter, described 73 thin film transistor (TFT) (T73), with the 74 thin film transistor (TFT) (T74) forms assist phase inverter.
10. the GOA circuit of based oxide semiconductor thin film transistor (TFT) as claimed in claim 1, it is characterized in that, in first order GOA unit circuit, grid access scan start signal (STV) of described 11 thin film transistor (TFT) (T11).
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510292125.0A CN104851403B (en) | 2015-06-01 | 2015-06-01 | The GOA circuits of based oxide semiconductor thin film transistor (TFT) |
| KR1020177013214A KR101933332B1 (en) | 2015-06-01 | 2015-06-23 | Goa circuit based on oxide semiconductor thin film transistor |
| GB1706062.5A GB2546044B (en) | 2015-06-01 | 2015-06-23 | GOA circuit based on oxide semiconductor thin film transistor |
| US14/771,501 US9858880B2 (en) | 2015-06-01 | 2015-06-23 | GOA circuit based on oxide semiconductor thin film transistor |
| JP2017544641A JP6518335B2 (en) | 2015-06-01 | 2015-06-23 | GOA circuit based on oxide semiconductor thin film transistor |
| PCT/CN2015/082007 WO2016192139A1 (en) | 2015-06-01 | 2015-06-23 | Goa circuit based on oxide semiconductor thin film transistor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510292125.0A CN104851403B (en) | 2015-06-01 | 2015-06-01 | The GOA circuits of based oxide semiconductor thin film transistor (TFT) |
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| CN104851403B CN104851403B (en) | 2017-04-05 |
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| JP (1) | JP6518335B2 (en) |
| KR (1) | KR101933332B1 (en) |
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| CN113168880A (en) * | 2018-12-28 | 2021-07-23 | 深圳市柔宇科技股份有限公司 | GOA unit, GOA circuit thereof and display device |
| CN113674656A (en) * | 2021-08-13 | 2021-11-19 | Tcl华星光电技术有限公司 | GOA circuit and electrical aging test method thereof |
| CN114882849A (en) * | 2022-05-13 | 2022-08-09 | 广州华星光电半导体显示技术有限公司 | GOA circuit and display panel |
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| US10446102B2 (en) * | 2017-08-16 | 2019-10-15 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd | GOA driving circuit and LCD device |
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| GB2546044A (en) * | 2015-06-01 | 2017-07-05 | Shenzhen China Star Optoelect | GOA circuit based on oxide semiconductor thin film transistor |
| WO2016192139A1 (en) * | 2015-06-01 | 2016-12-08 | 深圳市华星光电技术有限公司 | Goa circuit based on oxide semiconductor thin film transistor |
| GB2546044B (en) * | 2015-06-01 | 2021-03-24 | Shenzhen China Star Optoelect | GOA circuit based on oxide semiconductor thin film transistor |
| CN106057157A (en) * | 2016-08-01 | 2016-10-26 | 深圳市华星光电技术有限公司 | Goa circuit and liquid crystal display panel |
| CN106057157B (en) * | 2016-08-01 | 2018-10-16 | 深圳市华星光电技术有限公司 | GOA circuits and liquid crystal display panel |
| CN106251816A (en) * | 2016-08-31 | 2016-12-21 | 深圳市华星光电技术有限公司 | A kind of gate driver circuit and liquid crystal indicator |
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| US10453414B2 (en) * | 2017-08-16 | 2019-10-22 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd | GOA circuit and LCD device |
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| CN113674656A (en) * | 2021-08-13 | 2021-11-19 | Tcl华星光电技术有限公司 | GOA circuit and electrical aging test method thereof |
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Also Published As
| Publication number | Publication date |
|---|---|
| KR101933332B1 (en) | 2018-12-27 |
| GB201706062D0 (en) | 2017-05-31 |
| WO2016192139A1 (en) | 2016-12-08 |
| GB2546044B (en) | 2021-03-24 |
| CN104851403B (en) | 2017-04-05 |
| KR20170068581A (en) | 2017-06-19 |
| GB2546044A (en) | 2017-07-05 |
| JP2018513400A (en) | 2018-05-24 |
| JP6518335B2 (en) | 2019-05-22 |
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