CN104811413B

CN104811413B - Double DAGC factors pressure solution device of LTE CPRI interfaces

Info

Publication number: CN104811413B
Application number: CN201510236086.2A
Authority: CN
Inventors: 王艳欢; 黄维; 杨浩; 周世军
Original assignee: Wuhan Research Institute of Posts and Telecommunications Co Ltd
Current assignee: Wuhan Research Institute of Posts and Telecommunications Co Ltd
Priority date: 2015-05-11
Filing date: 2015-05-11
Publication date: 2018-05-01
Anticipated expiration: 2035-05-11
Also published as: CN104811413A

Abstract

The present invention provides double DAGC factors pressure solution device and method of LTE CPRI interfaces, and the compression end includes compression module and CPRI interface transmitting terminals, and compression module, for being compressed to original I circuit-switched datas and Q circuit-switched datas, and produces double DAGC factors；The compression module includes I roads FIFO, Q road FIFO, maximum value search module, effective Bit acquisition modules and quantifies interception module；CPRI interface transmitting terminals, are encoded for compressed I circuit-switched datas, Q circuit-switched datas and double DAGC factors and framing handles and is transferred to decompressor end by optical link；The decompressor end includes CPRI interface iSCSI receiving ends and decompression module；CPRI interface iSCSI receiving ends, for completing decoding and frame decoding processing, parse compressed I circuit-switched datas, Q circuit-switched datas and double DAGC factors；Decompression module, for compressed I circuit-switched datas and Q circuit-switched datas, according to double DAGC factor reductions.

Description

Double DAGC factors pressure solution device of LTE CPRI interfaces

Technical field

The present invention relates to field of communication technology, exactly, is related to a kind of pair of CPRI interfaces in LTE BBU and RRU The DAGC factors are compressed and decompression technique scheme.

Background technology

In field of communication technology, the essential term of LTE system represents to be described as follows：

1st, LTE (Long Term Evolution) Long Term Evolution

2nd, RRU (Radio Remote Unit) Remote Radio Unit

3rd, BBU (Base Band Unit) baseband processing unit

4th, DAGC (Digital Automatic Gain Control) digital resources obtainment

5th, DDC (Digital Down Converter) Digital Down Convert

6th, CPRI (Common Public Radio Interface) common public radio interface

7th, EVM (Error Vector Magnitude) error vector magnitude

8th, BLER (Block Error Rate) bLock error rate

LTE is the Long Term Evolution of 3G, i.e., said 4G, and a variety of innovative technologies are introduced in LTE improves systematicness Can, such as multi-antenna technology, multipoint cooperative, carrier aggregation, these technologies needed while lifting system performance increase base station with Between base station connection number and baseband processing unit and Remote Radio Unit between transmitted data amount, at present industry propose A variety of solutions, wherein most representational have a three classes, first, the hardware of updating apparatus, supports the physics of 10G even more highs Optical port scheme；Second, new RRU products are designed and developed, increases CPRI optical port quantity, is supported in a manner of more optical ports meet and share Higher transfer rate；3rd, the transfer resource that I/Q data takes is reduced by compression algorithm, improves the pressure of data transmission efficiency Contracting scheme, wherein I are in-phase modulation, and Q is orthogonal modulation.Need to increase extra hardware cost for first and second points, increase The big complexity realized, so by compression algorithm come to improve efficiency of transmission be a kind of cheaper and efficient method, but Be, at present there has been no simplicity and can actually solve the problems, such as appropriate technical solution appearance.

The content of the invention

The present invention proposes a kind of new CPRI links pressure solution technical solution for LTE optical transports, for solving LTE system In growing transmission demand, can in the case where keeping linear velocity constant, by improve data transmission resources so as to Achieve the purpose that to improve system performance.

Technical scheme provides a kind of double DAGC factors pressure solution device of LTE CPRI interfaces, including compression end with Decompressor end,

The compression end includes compression module and CPRI interface transmitting terminals,

Compression module, for being compressed to original I circuit-switched datas and Q circuit-switched datas, and produces double DAGC factors；The pressure Contracting module includes I roads FIFO, Q road FIFO, maximum value search module, effective Bit acquisition modules and quantifies interception module, and CPRI connects Mouth transmitting terminal, is encoded for compressed I circuit-switched datas, Q circuit-switched datas and double DAGC factors and framing handles and passes through light Link transmission is to decompressor end；

The decompressor end includes CPRI interface iSCSI receiving ends and decompression module,

CPRI interface iSCSI receiving ends, for complete decoding and frame decoding processing, parse compressed I circuit-switched datas, Q circuit-switched datas with And double DAGC factors；

Decompression module, for compressed I circuit-switched datas and Q circuit-switched datas, according to double DAGC factor reductions.

The present invention also provides the pressure solution side that a kind of double DAGC factors pressure solution device based on above-mentioned LTE CPRI interfaces is realized Method, if the maximum search cycle is N, targeted compression Bit numbers are S, are comprised the following steps,

Step 1, the I roads for entering compression module and Q circuit-switched datas are denoted as I_in, Q_in respectively, mono- tunnels of I_in enter corresponding I roads FIFO, all the way into maximum value search module；Mono- tunnels of Q_in enter corresponding Q roads FIFO, all the way into maximum value search Module；

Step 2, in maximum value search module, maximum Max_I, the Max_Q initial value of I circuit-switched datas and Q circuit-switched datas is set For 0, counting statistics, realization side are carried out according to sampling rate respectively to the I circuit-switched datas and Q circuit-switched datas for entering maximum value search module Formula is as follows,

I roads maximum and Q roads maximum search are carried out respectively first in N number of sampled point, to I circuit-switched datas, Max_I's Currency and first I circuit-switched data sampled points I1 carry out modulus value comparison, maximum if the currency of Max_I is more than or equal to I1 Value keeps the currency of Max_I, if the currency of Max_I is less than I1, maximum Max_I renewal values are I1, Ran Houzai The currency of Max_I and second I circuit-switched data sampled points I2 are compared, the maximum ... after obtaining second relatively compares successively Compared with and update Max_I and complete the I roads maximum arrived in this search cycle of a search cycle N number of sampled point；

To Q circuit-switched datas, the currency of Max_Q and first Q circuit-switched data sampled points Q1 are carried out modulus value comparison, if Max_ The currency of Q is more than or equal to Q1, then maximum keeps the currency of Max_Q, maximum if the currency of Max_Q is less than Q1 Value Max_Q renewal values are Q1, and then the currency of Max_Q and second Q circuit-switched data sampled points Q2 are compared again, obtain second Maximum ... after secondary comparison relatively and updates Max_Q and completes a search cycle N number of sampled point and obtain this search cycle successively Interior Q roads maximum；

In N number of sampled point after the completion of I roads maximum and Q roads maximum search, I circuit-switched datas and Q circuit-switched datas difference are exported Maximum Max_I and Max_Q to effective Bit acquisition modules, provide an enabler flags Max_En；

Step 3, when Max_I, Max_Q and Max_En enter effective Bit acquisition modules, Max_En notifies effective Bit to obtain Module carries out following processing,

The effective Bit start bits of I circuit-switched datas and the effective Bit start bits of Q circuit-switched datas are obtained respectively,

Since the highest order of Max_Q, previous position xth Bit and latter position xth -1Bit is contrasted, is if unequal Determine that previous position starts as effective Bit and terminates to compare, while it is x to mark effective Bit initial position, is made if equal X=x-1 continues to compare, and when x=x-1=S-2, is directly labeled as Pos_q=S-2；

After synchronously obtaining the effective Bit start bits of I circuit-switched datas and the effective Bit start bits of Q circuit-switched datas, a complement mark is produced Pos_vad, the reading that FIFO is produced with complement mark Pos_vad enable Rden_i, Rden_q；

Pos_i and Pos_q is exported to interception module is quantified from effective Bit acquisition modules, exports Rden_i to I road FIFO, Export Rden_q to Q road FIFO；

Step 4, Rden_i, Rden_q are enabled from corresponding according to the reading of the FIFO exported from effective Bit acquisition module FIFO reads I circuit-switched datas Out_i and Q circuit-switched data Out_q, I circuit-switched data Out_i, Q circuit-switched data Out_q and effective Bit acquisition modules Pos_i, Pos_q of output, which synchronously enter, quantifies interception module；

Step 5, quantify interception module and carry out following processing,

Quantization interception is carried out first,

Quantization interception carries out Out_i according to Pos_i, including S Bit are intercepted downwards as pressure using Pos_i as start bit Data Dagc_outi after contracting；

Quantization interception carries out Out_q according to Pos_q, including S Bit are intercepted downwards as pressure using Pos_q as start bit Data Dagc_outq after contracting；

Then Pos_i and Pos_q is combined into DAGC factor Ds agc_iq in pairs；

Step 6, CPRI interfaces transmitting terminal is compressed data Dagc_outi, Dagc_outq and double DAGC factors Dagc_iq is inserted into basic frame, forms superframe and radio frames are sent by optical link；

Step 7, CPRI interface iSCSI receiving ends parse double DAGC factor Ds agc_iq and compressed data Dagc_dati, Dagc_datq；

Step 8, decompression module is reduced according to double DAGC factors and compressed data Dagc_dati, Dagc_datq To original I circuit-switched datas and Q circuit-switched datas.

Moreover, double DAGC factors are placed on after each basic frame control word in first character section by CPRI interfaces transmitting terminal.

Above-mentioned technical proposal improves the data volume of transmission, specifically the present invention has as follows by reducing IQ Bit numbers Advantage：

1st, realize simple and convenient, it is only necessary to which less process resource can just be completed.The present invention realized in FPGA only need compared with Few BRAM resources and logical resource can be achieved with, and method is simple, better performances, and exploitativeness is strong.

2nd, the Bit numbers of I/Q data have been greatly reduced, have greatly improved the transmission quantity of data, need not increase additionally into The system performance of LTE is improved in the case of this.

3rd, using double DAGC factor methods, each DAGC factor of I, Q, ensure that the stability in compression process, reduce Influence to distorted signals.

4th, while LTE system performance is lifted, the indexs such as LTE receivers medium sensitivity, dynamic range, BLER are not produced Raw infringement.

Brief description of the drawings

Fig. 1 is double DAGC factors pressure solution device entire block diagram of the embodiment of the present invention.

Fig. 2 is double DAGC factors pressure solution method specific implementation block diagram of the embodiment of the present invention.

Embodiment

, can be in linear velocity by reducing IQ Bit numbers this paper presents a kind of double DAGC factors pressure solution technical solutions of LTE More data resources are transmitted in the case of remaining unchanged.Below in conjunction with drawings and examples the present invention will be described in detail technical side Case.

Those skilled in the art can voluntarily predefine some parameters according to system requirements before being implemented, and first, pressure Contracting Bit numbers determine, determine targeted compression Bit numbers according to the requirement of system indices, targeted compression Bit in the embodiment of the present invention Number is 7Bit；Second, I, Q maximum search cycle N, choosing it is smaller to the error vector magnitude EVM and signal of signal and interference Plus noise deteriorates smaller than SINR, but the DAGC factors accordingly increase, so as to take more transfer resources, choosing it is bigger to signal EVM and SINR deteriorate more serious, but the DAGC factors are accordingly reduced, so as to take less transfer resource, therefore for I, Q is most The selection in big value search cycle will make choice according to system requirements, generally can with a basic IQ number included in frame as Its maximum search cycle N, the transmission of the so more convenient DAGC factors, the present invention in the selected N values of embodiment be 32.

Fig. 1 is double DAGC factors pressure solution device entire block diagram of embodiment, is mainly formed just like lower part：

Compression end has compression module and CPRI interface transmitting terminals,

Compression module, it is main to complete to be compressed original I circuit-switched datas and Q circuit-switched datas, including 15Bit I circuit-switched datas 7Bit is compressed to, 15Bit Q circuit-switched datas are compressed to 7Bit, and produce double DAGC factors；

CPRI interface transmitting terminals, it is main to complete compressed I circuit-switched datas, Q circuit-switched datas and double DAGC factors to be compiled Code and framing handle and are transferred to decompressor end by optical link.

Decompressor end has CPRI interface iSCSI receiving ends and decompression module,

CPRI interface iSCSI receiving ends, it is main to complete decoding and frame decoding processing, parse compressed I circuit-switched datas, Q circuit-switched datas with And double DAGC factors；

Decompression module, it is main to complete compressed 7Bit I circuit-switched datas and 7Bit Q circuit-switched datas, according to sending Double DAGC factor reductions into 15Bit I and 15Bit Q circuit-switched datas.

When it is implemented, those skilled in the art can realize compression module and decompression module using FPGA, mould is compressed Block may include I roads FIFO, Q road FIFO, maximum value search module, effective Bit acquisition modules and quantify interception module.CPRI interfaces Transmitting terminal and CPRI interface iSCSI receiving ends can compress Bit numbers etc. according to objectives and realize.

I roads FIFO, for caching I circuit-switched datas；

Q roads FIFO, for caching Q circuit-switched datas；

Maximum value search module, for searching maximum from I circuit-switched datas, maximum is searched from Q circuit-switched datas；

Effective Bit acquisition modules, for obtaining the effective Bit start bits of I circuit-switched datas according to I circuit-switched datas maximum, according to Q roads Data maximums obtain the effective Bit start bits in Q roads, and output reading enables I roads FIFO and Q roads FIFO；

Quantify interception module, for being carried out according to the effective Bit start bits of I circuit-switched datas to the I circuit-switched datas read from I roads FIFO Compression, is compressed the Q circuit-switched datas read from Q roads FIFO according to the effective Bit start bits of Q circuit-switched datas, and I circuit-switched datas is effective Bit start bits and the effective Bit start bits of Q circuit-switched datas combine the DAGC factors in pairs.

Fig. 2 is double DAGC factors pressure solution method specific implementation block diagram of embodiment, and embodiment flow is as follows：

Step 1~5 are performed in the compression module of compression end first, step 6 is performed in CPRI interfaces transmitting terminal, is then solving The CPRI interface iSCSI receiving ends of compression end perform step 7, and step 8 is performed in decompression module.

Step 1：Data into compression module are divided into two-way, are cached all the way into FIFO, and another way enters maximum It is worth search module (Find Max), the I/Q data into maximum value search module carries out the lookup of maximum respectively；As in Fig. 2 into Enter the I roads of compression module and Q circuit-switched datas are denoted as I_in, Q_in respectively, mono- tunnels of I_in enter corresponding I roads FIFO, enter all the way Maximum value search module, to carry out the lookup of I circuit-switched data maximums, mono- tunnels of Q_in enter corresponding Q roads FIFO, enter all the way Maximum value search module, to carry out the lookup of Q circuit-switched data maximums.

Step 2：In maximum value search module, maximum Max_I, the Max_Q initial value of I circuit-switched datas and Q circuit-switched datas is set For 0, that is, Max_I=0, Max_Q=0 are initialized, the I circuit-switched datas and Q circuit-switched datas come in are counted according to sampling rate respectively Number statistics, implementation is as follows,

First according to default N values, I roads maximum and Q roads maximum search are carried out respectively in N number of sampled point,

To I circuit-switched datas, the currency of Max_I is carried out modulus value comparison with the first I circuit-switched data sampled points I1 to come in, such as The currency of fruit Max_I is more than or equal to I1, then maximum keeps the currency of Max_I, if the currency of Max_I is less than I1, It is I1 that then maximum Max_I, which updates value, then again obtained maximum (i.e. the currency of Max_I) and second I way Compare according to sampled point I2, obtain second relatively after maximum ... successively relatively and update Max_I complete a search cycle N=32 sampled point just obtains the I roads maximum in this search cycle；

The method of Q roads maximizing is consistent with I roads, to Q circuit-switched datas, the currency of Max_Q and come in the One Q circuit-switched data sampled points Q1 carries out modulus value comparison, if the currency of Max_Q is more than or equal to Q1, maximum keeps Max_Q Currency, if the currency of Max_Q is less than Q1, maximum Max_Q renewal values are Q1, then again obtained maximum Value (i.e. the currency of Max_Q) and second Q circuit-switched data sampled points Q2 compare, obtain second relatively after maximum ... according to It is secondary relatively and to update Max_Q and complete N=32 sampled point of a search cycle and just obtain Q roads maximum in this search cycle.

In N number of sampled point after the completion of maximum search, export I circuit-switched datas and Q circuit-switched datas maximum Max_I respectively and Max_Q, provides the completion that an enabler flags Max_En is used to refer to a cycle maximum value search, when this enabler flags continues Between be a clock cycle (corresponding with a sampled point) for maximum value search module, and Max_I and Max_Q are carried out clear 0 and grasped Make, then start the processing in next maximum search cycle.

Step 3：Max_I, Max_Q and Max_En enter effective Bit acquisition modules (Get Use Bit), Max_En notices Effective Bit acquisition modules are handled as follows,

Obtain the effective Bit start bits of I circuit-switched datas and the effective Bit start bits of Q circuit-switched datas respectively first,

Each sampled point of I circuit-switched datas 15Bit data altogether, subscript is since 0 defined in FPGA, and wherein highest order is the 14Bit, lowest order are the 0th, and 14Bit must be sign bit, and 14Bit and 13Bit are compared, if not phase Deng illustrating to be exactly Bit effective since 14Bit, and mark effective Bit initial position Pos_i=14；If equal theory Also later, then continue 14Bit and 12Bit to compare, if unequal, illustrate from the in bright effectively Bit initial positions 13Bit starts to be exactly Bit effective, and marks Pos_i=13, equal to continue to downwards relatively, be handled, always compared according to this Relatively untill targeted compression Bit numbers S-2, regardless of whether it is equal, do not continue to compare, be directly labeled as Pos_i=S-2.Implement Example S values selected as 7, Pos_i=5 is just directly marked less than S-2,

The acquisition methods of the effective Bit start bits in Q roads are consistent with I roads, since the highest order of Max_Q, by previous position Xth Bit and latter position xth -1Bit is contrasted, and determines that previous position starts as effective Bit and terminates to compare if unequal, It is x to mark effective Bit initial position at the same time, makes x=x-1 continue to compare if equal, when x=x-1=S-2, directly Connect and be labeled as Pos_q=S-2；

After synchronously obtaining the effective Bit start bits of I circuit-switched datas and the effective Bit start bits of Q circuit-switched datas, a complement mark is produced Pos_vad, this mark duration for effective Bit acquisition modules a clock cycle (and one of maximum value search module Clock cycle is similar)；The reading that FIFO is produced with complement mark Pos_vad enables Rden_i, Rden_q,

So the data from the output of effective Bit acquisition modules include Pos_i, Pos_q, Rden_i, Rden_q, including from having Imitate Bit acquisition modules and export Pos_i and Pos_q to interception module is quantified, export Rden_i to I road FIFO, export Rden_q to Q Road FIFO.

Step 4：Rden_i, Rden_q are enabled according to the reading of the FIFO exported from effective Bit acquisition module, from corresponding FIFO reads I circuit-switched datas Out_i and Q circuit-switched data Out_q, I circuit-switched data Out_i, Q circuit-switched data Out_q and effective Bit acquisition modules Pos_i, Pos_q of output, which synchronously enter, quantifies interception module；

The i.e. corresponding N number of I circuit-switched datas sampled points of I circuit-switched datas Out_i, the Q circuit-switched data Out_q that corresponding FIFO is read and N number of Q Circuit-switched data sampled point.

Step 5：Quantifying the input of interception module includes, Pos_i, Pos_q, Out_i, Out_q, according to Pos_i to Out_i Quantization interception is carried out, intercepts S Bit downwards using Pos_i as start bit as compressed data Dagc_outi, S is target pressure Contracting Bit numbers, the processing of Q circuit-switched datas is consistent with I roads, intercepts S Bit downwards using Pos_q as start bit as compressed data Dagc_outq；Since this embodiment targeted compression Bit number S selected as 7Bit, Pos_i share 4Bit, Pos_q is also shared 4Bit, by Pos_i as high 4bit, Pos_q is combined into 8Bit data Dagc_iq, Dagc_iq as low 4bit and is referred to as double DAGC The factor；

Quantify data Dagc_outi, Dagc_outq after interception module output squeezing and double DAGC factor Ds agc_iq To CPRI interface transmitting terminals.

Step 6：CPRI interfaces transmitting terminal is compressed data Dagc_outi, Dagc_outq and double DAGC factors Dagc_iq is inserted into basic frame, forms superframe and radio frames are sent by optical link, double DAGC factors can be placed on each After a basic frame control word in first character section.

Step 7：Frame decoding of the CPRI interface iSCSI receiving ends Jing Guo CPRI agreements, parses double DAGC factor Ds agc_iq and compression Data Dagc_dati, Dagc_datq (corresponding in step 6 gained Dagc_outi, Dagc_outq with transmitting terminal) afterwards；

The double DAGC factor Ds agc_iq of CPRI interface iSCSI receiving ends output and compressed data Dagc_dati, Dagc_datq To decompression module.

Step 8：Decompression module reduces I according to double DAGC factors and compressed data Dagc_dati, Dagc_datq With Q circuit-switched datas to 15Bit,

Such as Dagc_i=14 in the DAGC factors, then output data for I_out=, { fill, compressed data, mends by sign bit 0 filling }+{ offset }={ 0bit sign bits, Dagc_dati, 8 ' d0 }+{ (2-1) }, wherein I_out Part I is symbol Position filling, determines the how many a sign bits (1 can be mended during filling) of filling, embodiment is 0bit sign bits according to the value of Dagc_i； Part II is the 7Bit data parsed after compression from CPRI, and Part III is to mend 0 to be filled into 15Bit, and embodiment is pair 8bit mends 0, and Part IV is offset, and embodiment is (2-1)；Dagc_i is also to be made of this four part when being other values, according to This analogizes decompression data when can draw other Dagc_i values；

The decompression method on Q roads is consistent, output data Q_out with I roads.

The effect of wherein offset is primarily used to prevent the generation of direct current biasing, the deterioration to EVM is reduced, after decompression Data give again subsequent module use.

In the step 1 of above flow, the storage of a search cycle is carried out to I and Q circuit-switched datas；In step 2, find out respectively I roads and Q roads maximum absolute value value in search cycle；Step 3, effective Bit start bits of the maximum of I and Q are obtained；Step 4, read the I roads of storage and Q circuit-switched datas and be sent into after aliging with the DAGC factors and quantify interception module；Step 5, in the search cycle All I roads and Q circuit-switched datas carry out quantization interception according to effective Bit start bits of acquisition；Step 6~7, CPRI framing is conciliate Frame；Step 8, I roads and Q roads are decompressed to original Bit digits according to the DAGC factors on I roads and Q roads.As it can be seen that step 1~5 and step 8 In, the suitable search cycle is selected, finds out maximum, effective Bit start bit is obtained and carries out quantifying the mesh that interception reaches compression , decompressor end is according to DAGC factor reductions data to Bit original.

By above scheme, the present invention is keeping the constant feelings of current linear speed by reducing the Bit numbers of IQ to reach Under condition, the transmission quantity of data is improved, obtains the system performance of higher.In LTE, single antenna list carries the line between 20M CPRI interfaces Property rate calculations formula is LineRate=(30.72) × (30) × (10/8) × (16/15)=1.2288Gbit/s, wherein 30.72Msps is 20M bandwidth sampling rates, and 30 be Bit numbers total IQ, and 10/8 encodes for 8b10b, 16/15 sub- redundancy in order to control, From calculation formula it can be seen that as the Bit numbers of IQ transmission are reduced, keeping to transmit more in the case that linear velocity is constant More data resources, is contracted I/Q data from 15Bit by data bits by compression algorithm (double DAGC factor methods) in embodiment 7Bit is reduced to, even if introducing a small amount of resource taken in view of the DAGC factors, linear velocity 1.2288Gbit/s is constant keeping In the case of using the compression method can also transmit the data resource that two antenna lists carry 20M, compression ratio reaches 2 times.

There are uniform quantization method, non-uniform quantizing method, adaptive quantizing for CPRI interface compression methods more common at present Method and vector quantization method, it is contemplated that BBU and RRU system uplinks have larger reception dynamic range requirements, and need to ensure The sensitivity of receiver disclosure satisfy that index, so selection adaptive quantizing method is proper, and what the present invention was said Double DAGC factors pressure solution methods fall within one kind in adaptive quantizing method, and the method has the following advantages that：First, Neng Gougen It is believed that number changes in amplitude dynamic change quantify cut position start stop bit, ensure that quantified precision, to recipient to sensitivity do not have Have an impact, can adapt to larger reception dynamic range；Second, quantization cut position is carried out respectively to I and Q circuit-switched datas, is produced respectively The DAGC factors, reduce quantization error and the influence to signal EVM；3rd, the suitable search cycle is chosen, obtains and is adopted in the cycle The maximum of sampling point and its effective Bit starting position, then other points are also according to maximum effective Bit positions quantification section Position, will not so cause to quantify the situation that cut position overflows, the storage resource and other resource requirements to FPGA be not high, reception chain The processing delay on road will not increase very much, have very strong exploitativeness.

Examples detailed above is the preferable embodiment of the present invention, but embodiments of the present invention and from the limit of above-described embodiment System, other any Spirit Essences for not running counter to the present invention with made under principle change, modification, replacement, combine, simplify it is equal Equivalent substitute mode is should be, is included within protection scope of the present invention.

Claims

A kind of 1. double DAGC factors pressure solution device of LTE CPRI interfaces, it is characterised in that：Including compression end and decompressor end,

The compression end includes compression module and CPRI interface transmitting terminals,

Compression module, for being compressed to original I circuit-switched datas and Q circuit-switched datas, and produces double DAGC factors；The compression mould Block includes I roads FIFO, Q road FIFO, maximum value search module, effective Bit acquisition modules and quantifies interception module,

CPRI interface transmitting terminals, for compressed I circuit-switched datas, Q circuit-switched datas and double DAGC factors encoded and framing at Manage and decompressor end is transferred to by optical link；

The decompressor end includes CPRI interface iSCSI receiving ends and decompression module,

CPRI interface iSCSI receiving ends, for completing decoding and frame decoding processing, parse compressed I circuit-switched datas, Q circuit-switched datas and double The DAGC factors；

Decompression module, for compressed I circuit-switched datas and Q circuit-switched datas, according to double DAGC factor reductions；

Pressure solution preocess is as follows, if the maximum search cycle is N, targeted compression Bit numbers are S, are comprised the following steps,

Step 1, the I roads for entering compression module and Q circuit-switched datas are denoted as I_in, Q_in respectively, mono- tunnels of I_in enter corresponding I roads FIFO, all the way into maximum value search module；Mono- tunnels of Q_in enter corresponding Q roads FIFO, all the way into maximum value search module；

Step 2, in maximum value search module, it is 0 to set maximum Max_I, the Max_Q initial value of I circuit-switched datas and Q circuit-switched datas, Counting statistics is carried out according to sampling rate respectively to the I circuit-switched datas and Q circuit-switched datas for entering maximum value search module, implementation is such as Under,

Carry out I roads maximum and Q roads maximum search respectively first in N number of sampled point,

To I circuit-switched datas, the currency of Max_I and first I circuit-switched data sampled points I1 are carried out modulus value comparison, if Max_I Currency is more than or equal to I1, then maximum keeps the currency of Max_I, if the currency of Max_I is less than I1, maximum Max_I renewal values are I1, and then the currency of Max_I and second I circuit-switched data sampled points I2 are compared again, are obtained second Maximum ... after comparing relatively and updates Max_I and completes a search cycle N number of sampled point and obtain in this search cycle successively I roads maximum；

To Q circuit-switched datas, the currency of Max_Q and first Q circuit-switched data sampled points Q1 are carried out modulus value comparison, if Max_Q Currency is more than or equal to Q1, then maximum keeps the currency of Max_Q, if the currency of Max_Q is less than Q1, maximum Max_Q renewal values are Q1, and then the currency of Max_Q and second Q circuit-switched data sampled points Q2 are compared again, are obtained second Maximum ... after comparing relatively and updates Max_Q and completes a search cycle N number of sampled point and obtain in this search cycle successively Q roads maximum；

In N number of sampled point after the completion of I roads maximum and Q roads maximum search, I circuit-switched datas and Q circuit-switched datas are exported respectively most Big value Max_I and Max_Q provides an enabler flags Max_En to effective Bit acquisition modules；

Step 3, when Max_I, Max_Q and Max_En enter effective Bit acquisition modules, Max_En notifies effective Bit acquisition modules Following processing is carried out,

The effective Bit start bits of I circuit-switched datas and the effective Bit start bits of Q circuit-switched datas are obtained respectively,

Since the highest order of Max_I, previous position xth Bit and latter position xth -1Bit is contrasted, is determined if unequal Previous position starts as effective Bit and terminates to compare, while it is x to mark effective Bit initial position, and x=is made if equal X-1 continues to compare, and when x=x-1=S-2, is directly labeled as Pos_i=S-2；

Since the highest order of Max_Q, previous position xth Bit and latter position xth -1Bit is contrasted, is determined if unequal Previous position starts as effective Bit and terminates to compare, while it is x to mark effective Bit initial position, and x=is made if equal X-1 continues to compare, and when x=x-1=S-2, is directly labeled as Pos_q=S-2；

After synchronously obtaining the effective Bit start bits of I circuit-switched datas and the effective Bit start bits of Q circuit-switched datas, a complement mark Pos_ is produced Vad, the reading that FIFO is produced with complement mark Pos_vad enable Rden_i, Rden_q；

Pos_i and Pos_q is exported to interception module is quantified from effective Bit acquisition modules, exports Rden_i to I road FIFO, output Rden_q to Q roads FIFO；

Step 4, Rden_i, Rden_q is enabled according to the reading of the FIFO exported from effective Bit acquisition module to read from corresponding FIFO Go out I circuit-switched datas Out_i and Q circuit-switched data Out_q, I circuit-switched data Out_i, Q circuit-switched data Out_q and effective Bit acquisition modules output Pos_i, Pos_q, which synchronously enter, quantifies interception module；

Step 5, quantify interception module and carry out following processing,

Quantization interception is carried out first,

Quantization interception carries out Out_i according to Pos_i, including after intercepting S Bit downwards as compression using Pos_i as start bit Data Dagc_outi；

Quantization interception carries out Out_q according to Pos_q, including after intercepting S Bit downwards as compression using Pos_q as start bit Data Dagc_outq；

Then Pos_i and Pos_q is combined into DAGC factor Ds agc_iq in pairs；

Step 6, CPRI interfaces transmitting terminal is compressed data Dagc_outi, Dagc_outq and double DAGC factor Ds agc_ Iq is inserted into basic frame, forms superframe and radio frames are sent by optical link；

Step 7, CPRI interface iSCSI receiving ends parse double DAGC factor Ds agc_iq and compressed data Dagc_dati, Dagc_ datq；

Step 8, decompression module reduces to obtain original according to double DAGC factors and compressed data Dagc_dati, Dagc_datq The I circuit-switched datas and Q circuit-switched datas of beginning.
2. double DAGC factors pressure solution device of LTE CPRI interfaces according to claim 1, it is characterised in that：CPRI interfaces are sent out Double DAGC factors are placed on after each basic frame control word in first character section by sending end.