CN104810266B - The forming method of semiconductor devices - Google Patents
The forming method of semiconductor devices Download PDFInfo
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- CN104810266B CN104810266B CN201410042193.7A CN201410042193A CN104810266B CN 104810266 B CN104810266 B CN 104810266B CN 201410042193 A CN201410042193 A CN 201410042193A CN 104810266 B CN104810266 B CN 104810266B
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A kind of forming method of semiconductor devices, including：Substrate is provided, substrate surface is formed with gate structure；Doped region is formed in the substrate of gate structure both sides；The first metal layer is formed on doped region surface；The first metal contact layer is formed on doped region surface；Second metal layer is formed on the first metal contact layer surface；Second annealing is carried out to second metal layer, the metal in second metal layer is set to diffuse in the first metal contact layer, convert the first metal contact layer to the second metal contact layer, the schottky barrier height between the second metal contact layer and substrate is less than the schottky barrier height between the first metal contact layer and substrate.The present invention makes metallic atom diffuse in the first metal contact layer using annealing treating process, the metallic atom of the second metal contact layer formed is evenly distributed, ability with schottky barrier height between the second metal contact layer of stronger reduction and substrate, to reduce the contact resistance of semiconductor devices, optimize the driveability of semiconductor devices.
Description
Technical field
The present invention relates to field of semiconductor manufacture technologies, the more particularly to forming method of semiconductor devices.
Background technology
As semiconductor devices integrated level constantly increases, the relevant critical dimension of semiconductor devices constantly reduces, accordingly
There are many problems, if the sheet resistance and contact resistance of device drain source area accordingly increase, the response speed of device is caused to drop
Low, signal postpones.Therefore, the interconnection structure of low-resistivity is critical to as manufacture highly intergrated semiconductor device one
Element.
In order to reduce the contact resistance of device drain source area, the process of metal silicide, the metal silication are introduced
Object has lower resistivity, can be substantially reduced the contact resistance of hourglass source electrode.Metal silicide and self-aligned metal silicate
And formation process is widely used for reducing the sheet resistance and contact resistance of device source electrode and drain electrode, to reduce resistance electricity
Hold delay time.
In existing self-aligned metal silicate technology, frequently with nickle silicide as metal silicide.Described in utilization
The metal silicide that nickle silicide is formed has smaller contact resistance, the consumption of smaller silicon, is easy to reach relatively narrow line width, because
This, nickle silicide is considered as a kind of ideal metal silicide.
However, with the continuous reduction of feature sizes of semiconductor devices, formed using prior art metal silicide technology
Semiconductor devices, contact resistance has been difficult to meet process requirements, there is an urgent need for seeking the forming method of new metal silicide, with
The contact resistance for reducing semiconductor devices, improves the speed of service of semiconductor devices.
Invention content
Problems solved by the invention is to provide a kind of forming method of semiconductor devices, reduces the contact electricity of semiconductor devices
Resistance, optimizes the driveability of semiconductor devices.
To solve the above problems, the present invention provides a kind of forming method of semiconductor devices, including：Substrate is provided, it is described
Substrate surface is formed with gate structure；The substrate of the gate structure both sides is doped, forms doping in the substrate
Area；The first metal layer is formed on the doped region surface；First annealing is carried out to the first metal layer, in doped region table
Face forms the first metal contact layer；Second metal layer, the second metal layer tool are formed on first metal contact layer surface
Play the role of adjusting the schottky barrier height between the first metal contact layer and substrate；Second is carried out to the second metal layer to move back
Fire processing, makes the metallic atom in second metal layer diffuse in the first metal contact layer, converts the first metal contact layer to
Second metal contact layer, and the schottky barrier height between the second metal contact layer and substrate is less than the first metal contact layer and lining
Schottky barrier height between bottom.
Optionally, the metallic atom of the second metal layer includes Al, Pt, Pd or rare earth metal, wherein rare earth metal is
Yb or Er.
Optionally, when the metallic atom of the second metal layer includes Al, the material of the second metal layer is Al, TiAl
Or TaAl.
Optionally, the material of second metal contact layer is NiAlSi.
Optionally, second metal is formed using atomic layer deposition, chemical vapor deposition or physical gas-phase deposition
Layer.
Optionally, the thickness of the second metal layer is 5 angstroms to 20 angstroms.
Optionally, second annealing is immersion annealing, spike annealing, Millisecond annealing or laser annealing.
Optionally, the technological parameter of the immersion annealing is：Annealing temperature is 200 degree to 600 degree, anneal duration 5
Second was to 120 seconds；The technological parameter of the spike annealing is：Annealing temperature is 300 degree to 800 degree；The Millisecond annealing or laser
The technological parameter of annealing is：Annealing temperature is 500 degree to 900 degree, and anneal duration is 0.1 millisecond to 1 second.
Optionally, further include step before forming second metal layer：Prerinse is carried out to the first metal contact layer surface
The technique of processing, the prerinse processing is wet etching or plasma cleaning.
Optionally, the material of the first metal layer is the monometallic or alloy of Ni, W, Ti, Ta, Pt, Co.
Optionally, first annealing is step annealing processing or multiple step anneal processing.
Optionally, the multiple step anneal processing includes first step annealing and second step annealing.
Optionally, the first step annealing is that immersion is annealed, and annealing temperature is 250 degree to 350 degree, anneal duration
It is 20 seconds to 90 seconds；Or the first step annealing is Millisecond annealing, annealing temperature is 650 degree to 950 degree, and anneal duration is
0.25 millisecond to 20 milliseconds.
Optionally, the second step annealing is that immersion is annealed, and annealing temperature is 350 degree to 500 degree, anneal duration
It is 20 seconds to 90 seconds；Or the second step annealing is spike annealing, annealing temperature is 350 degree to 550 degree.
Optionally, further include step before the first annealing is carried out after forming the first metal layer：In the first metal
Layer surface forms protective layer.
Optionally, the material of the protective layer is Ti, Ta, TiN or TaN.
Optionally, after forming the first metal contact layer, the protective layer is removed.
Optionally, further include step before forming doped region：Groove is formed in the substrate of gate structure both sides；It adopts
The stressor layers of the full groove of filling are formed with selective epitaxial process.
Optionally, the semiconductor devices of formation is NMOS transistor, PMOS transistor or CMOS transistor.
Compared with prior art, technical scheme of the present invention has the following advantages：
The present invention forms the first metal layer on doped region surface；The is formed after carrying out the first annealing to the first metal layer
One metal contact layer；Second metal layer is formed on the first metal contact layer surface, and second metal layer has the first metal of adjusting
The effect of schottky barrier height between contact layer and substrate；Second annealing is carried out to second metal layer so that the second gold medal
Metallic atom in category diffuses in the first metal contact layer, also, since under the action of annealing, metallic atom is
Distribution uniform in two metal contact layers, equally distributed metallic atom, which is more advantageous to, reduces the effective of the second metal contact layer
Work function so that the ability that metallic atom adjusts the schottky barrier height between the second metal contact layer and substrate obtains effectively
It plays, the reduction of schottky barrier height advantageously reduces contact resistivity, to reduce the contact resistance of semiconductor devices, carries
The speed of service of high semiconductor devices.
Further, the material of second metal layer of the present invention is TiAl, wherein the effective work function of metallic atom Al is relatively low,
It diffuses in the first metal contact layer and is formed after the second metal contact layer, Xiao between the second metal contact layer and substrate can be reduced
Special base barrier height；Also, the Ti in second metal layer plays certain inhibiting effect to the diffusion of Al atoms, prevents Al atoms
Spread too fast, diffusion velocity appropriate is more advantageous to Al atoms being uniformly distributed in the second metal contact layer, to further
The schottky barrier height between the second metal contact layer and substrate is reduced, and then reduces the contact resistance of semiconductor devices, optimization
The driveability of semiconductor devices.
Further, it forms the technique of the first metal contact layer to handle for double annealing, the material of the first metal contact layer
For NiSi, NiSi characteristics relatively low with resistivity and high stability in nickle silicide series material, so that the second gold medal
Belonging to contact layer also has the characteristic that resistivity is low, stability is high, advanced optimizes the electric property of semiconductor devices.
Description of the drawings
Fig. 1 to Fig. 3 is the cross-sectional view for the semiconductor devices forming process that one embodiment of the invention provides；
Fig. 4 to Fig. 9 is the cross-sectional view of the forming process for the semiconductor devices that another embodiment of the present invention provides.
Specific implementation mode
By background technology it is found that the contact resistance for the semiconductor devices that the prior art is formed is big, the operation of semiconductor devices
Speed is slow.
The contact resistance of semiconductor devices has two-dimensional dependence, with constantly subtracting for feature sizes of semiconductor devices
Small, contact resistance is increasing in the ratio of the total dead resistance of semiconductor devices, seriously affects the driving capability of semiconductor devices,
Conventional metal silicide technology is used to be not enough to reduce the contact resistance of semiconductor devices.
It carries out analysis for the influence factor of contact resistance and finds that contact resistance is determined by contact resistivity and contact area
It is fixed, specifically, contact resistance and contact resistivity direct proportionality and the inversely proportional relationship of contact area.With semiconductor
The scaled down of device, contact area accelerates to reduce with the speed of the velocity squared of device dimensions shrink, accordingly, it is difficult to pass through
Increase the method for contact area to reduce contact resistance, and reduce contact resistivity and be easier to realize, to be connect by reducing
Resistivity is touched to reduce the contact resistance of semiconductor devices.
Contact resistance of the contact resistance of semiconductor devices between metal-semiconductor, from Metals-semiconductor contacts theory
The semiconductor energy gap of angle analysis, the interface that semiconductor is in contact with metal bends, as soon as a high potential energy area is formed, this
It is Schottky barrier（SB：Schottky Barrier）, the electronics in semiconductor substrate must have the energy higher than this potential barrier
Amount can just cross potential barrier and flow into metal.The schottky barrier height of contact resistivity and Metals-semiconductor contacts（SBH：
Schottky Barrier Height）And the doping concentration of semiconductor is closely related, specifically, contact resistivity and Xiao Te
Base barrier height direct proportionality and the inversely proportional relationship of doping concentration.
Using conventional Metals-semiconductor contacts system, the material of metal is NiSi, semi-conducting material Si, metal with
The schottky barrier height of semiconductor is about 0.6ev to 0.75ev, and schottky barrier height is definite value, if desired reduces contact electricity
Resistance rate then need improve source-drain area doping concentration, and the doping concentration of source-drain area by Doped ions in substrate material
The limitation of solid solubility, also, the doping concentration for improving source-drain area can influence other electric properties of semiconductor devices, and it is therefore, difficult
To reduce contact resistance by improving the method for doping concentration.
The above analysis is it is found that it is to reduce most having for contact resistivity to reduce metal -- semiconductor Schottky barrier height
Efficacious prescriptions method.And metal -- semiconductor Schottky barrier height is directlyed proportional to the difference of metal and the effective work function of semiconductor, passes through drop
The effective work function of low metal reduces metal -- semiconductor Schottky barrier height, therefore, by selecting suitable low potential barrier to connect
Touch material（Low-work-function material）The purpose that reduction metal -- semiconductor Schottky barrier height can be achieved, to reduce contact electricity
Resistance rate reduces the contact resistance of semiconductor devices, improves the speed of service of semiconductor devices, optimizes the driven nature of semiconductor devices
Energy.
For this purpose, one embodiment of the invention provides a kind of forming method of semiconductor devices, Fig. 1 to Fig. 3 carries for the present embodiment
The cross-sectional view of the semiconductor devices forming process of confession.
Referring to FIG. 1, providing substrate 100, it is formed with isolation structure 101 in substrate 100,100 surface of the substrate is formed
It includes positioned at the gate dielectric layer 111 on 100 surface of substrate and positioned at 111 table of gate dielectric layer to have gate structure, the gate structure
The gate electrode layer 112 in face；Side wall 102 is formed on 100 surface of the substrate, the side wall 102 is located at gate structure both sides side wall
On；The substrate 100 of the gate structure both sides is doped, forms doped region in the substrate 100 of gate structure both sides
103。,
Referring to FIG. 2, in 103 forming metal layer on surface of the doped region；The metal layer is made annealing treatment, is formed
First metal contact layer 104.
The material of the metal layer is the monometallic or alloy of Ni, W, Ti, Ta, Pt, Co, for being subsequently formed metal contact
Layer provides metallic atom.In the present embodiment, the material of the metal layer is Ni.
In the present embodiment, the material of the metal layer is Ni, and the material of the substrate 100 is Si, in the work of annealing
Under, with the material of substrate 100 silicification reaction occurs for the material of metal layer, forms the first metal contact layer 104, first gold medal
The material for belonging to contact layer 104 is NiSi.
Referring to FIG. 3, to first metal contact layer 104（It please refers to Fig.2）Ion implanting 106 is carried out, by the first gold medal
Belong to contact layer 104 and is converted into the second metal contact layer 107.
In order to reduce the schottky barrier height between the first metal contact layer 104 and substrate 100, can be used work function compared with
Low the first metal contact layer of atom pair 104 carries out ion implanting 106, to reduce the second metal contact layer formed after doping
Schottky barrier height between 107 and substrate 100.
The injection ion of the ion implanting 106 is Al, Pt, Pd or rare earth metal, wherein rare earth metal is Yb or Er.
However, the limitation that the contact resistance for the semiconductor devices that the above method is formed reduces, still cannot be satisfied and carries
The requirement of high semiconductor devices driveability.
For above-mentioned semiconductor device forming method carry out the study found that injection the first metal contact layer 105 in from
Son is unevenly distributed in the semiconductor device, and since the characteristic of peak value is presented in the ion concentration distribution of ion implantation technology, the
The distribution character of similar Gaussian Profile is also presented in injection ion in one metal contact layer 105 so that adjusts the contact of the second metal
The ability of schottky barrier height between layer 107 and substrate 100 is limited, and the contact resistance of semiconductor devices is still larger.Also,
Since the controllability of ion implantation technology is poor, the injection ion concentration of 107 bottom of the second metal contact layer may be caused too small
Or in ion implanting to doped region 103, the schottky barrier height between the second metal contact layer 107 and substrate 100 is not only reduced
Ability it is limited, but also other electric properties of semiconductor devices may be caused to become due in ion implanting to doped region 103
Difference.
For this purpose, another embodiment of the present invention also provides a kind of forming method of semiconductor devices, connect forming the first metal
After contact layer, second metal layer is formed on the first metal contact layer surface, the second annealing is carried out to second metal layer, makes the
Metal in two metal layers diffuses in the first metal contact layer, converts the first metal contact layer to the second metal contact layer,
And the second schottky barrier height between metal contact layer and substrate is less than the Schottky gesture between the first metal contact layer and substrate
Build height.The present invention makes the method that metal diffuses to the second metal contact layer using annealing so that metal is in the second metal
It is evenly distributed in contact layer, effectively reduces metal-semiconductor schottky barrier height, to reduce connecing for semiconductor devices
It gets an electric shock and hinders, improve the speed of service of semiconductor devices, optimize the driveability of semiconductor devices.
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
The semiconductor devices that the present invention is formed be NMOS transistor, PMOS transistor or CMOS transistor, the present embodiment with
The semiconductor devices of formation does exemplary illustrated for NMOS transistor.
Fig. 4 to Fig. 9 is the cross-sectional view of semiconductor devices forming process provided in this embodiment.
Referring to FIG. 4, providing substrate 200,200 surface of the substrate is formed with gate structure.
Specifically, specifically, the material of the substrate 200 be silicon on monocrystalline silicon, polysilicon, non-crystalline silicon or insulator its
In one kind；The substrate 200 or Si substrates, Ge substrates, GeSi substrates or GaAs substrates.
200 surface of the substrate can also form several epitaxial interface layers or strained layer to improve the electricity of semiconductor devices
Performance.
In the present embodiment, the substrate 200 is Si substrates.In other embodiments of the present invention, can also be shape in substrate
At the substrate for having device, for example, being formed with transistor, capacitance or resistance etc. in substrate.
In the present embodiment, also there is isolation structure 201 in the substrate 200, electricity connects between preventing adjacent active regions
It connects.The material of the isolation structure 201 can be one or more of silica, silicon nitride or silicon oxynitride.
The gate structure includes：Gate dielectric layer 211 positioned at 200 surface of substrate, the grid positioned at 211 surface of gate dielectric layer
Electrode layer 212.
The gate structure can be replacement gate structure, metal gate structure or polysilicon gate construction.
In the present embodiment, the material of the gate dielectric layer 211 is silica or silicon oxynitride, the gate electrode layer 212
Material be polysilicon.
In his embodiment of the invention, the material of gate dielectric layer is the high k dielectric materials such as hafnium oxide, the material of gate electrode layer
For metal or other conductive materials.
Subsequent technique causes to damage to the side wall of gate structure in order to prevent, side wall shape of the present embodiment in gate structure
At side wall 202, play the role of protecting gate structure sidewall.The side wall 202 is single layer structure or multilayered structure, side wall 202
Material be silica, silicon nitride or silicon oxynitride.
Can also include step it should also be noted that, before forming side wall 202：To the substrate of gate structure both sides
200 are doped to form lightly doped district（LDD：Lightly Doped Drain）, the lightly doped district can alleviate semiconductor device
The hot carrier's effect of part（HCE：Hot carrier Effect）, improve the electric property of semiconductor devices.
Referring to FIG. 5, being doped to the substrate 200 of the gate structure both sides, doping is formed in the substrate 200
Area 203.
In the present embodiment, the doping is carried out using ion implantation technology.Semiconductor device of the embodiment of the present invention to be formed
Part be NMOS transistor do it is exemplary illustrated, then the injection ion of ion implanting be N-type ion, the N-type ion be P, As or
Sb。
As one embodiment, the technological parameter of the ion implantation technology is：Injection ion is P, and Implantation Energy is
10kev to 50kev, implantation dosage 1E18atom/cm2To 5E20atom/cm2。
In other embodiments, when the semiconductor devices of formation is PMOS transistor, the injection ion of ion implanting is p-type
Ion, the p-type ion are B, Ga or In.As one embodiment, the technological parameter of the ion implantation technology is：Inject from
Son is B, and Implantation Energy is 5kev to 50kev, implantation dosage 1E17atom/cm2To 5E19atom/cm2。
Can also include step after forming doped region 203：The substrate 200 is made annealing treatment, activation doping
Ion makes Doped ions be redistributed in substrate 200；Meanwhile ion processes are repaired to lattice damage caused by substrate 200.
In other embodiments of the present invention, further include step before forming doped region：In the gate structure both sides
Groove is formed in substrate；The stressor layers of the full groove of filling are formed using selective epitaxial process.As one embodiment, shape
At semiconductor devices be NMOS transistor, the materials of the stressor layers is SiC or SiCP, and the stressor layers are to semiconductor devices
Channel region applies tensile stress effect, the electron mobility of channel region is improved, to improve the speed of service of semiconductor devices；Make
Semiconductor devices for another embodiment, formation is PMOS transistor, and the material of the stressor layers is SiGe or SiGeB, described
Stressor layers apply compression stress effect to semiconductor devices, the hole mobility of channel region are improved, to improve semiconductor devices
The speed of service, optimize the electric property of semiconductor devices.
Referring to FIG. 6, forming the first metal layer 204 on 203 surface of the doped region.
The material of the first metal layer 204 is the monometallic or alloy of Ni, W, Ti, Ta, Pt, Co.First metal
The formation process of layer 104 is physical vapour deposition (PVD), metal sputtering or atomic layer deposition.
The first metal layer 204 is used to provide metallic atom, the first metal layer to be subsequently formed the first metal contact layer
204 material subsequently occurs chemical reaction with the material of substrate 200 and forms the first metal contact layer, the material of the first metal layer 204
When material is Ni, the material of the follow-up substrate 200 for carrying out consumption of chemical reaction is low and the line width of the first metal contact layer that is formed
It is narrow, and process costs are relatively low.
In the present embodiment, the material of the first metal layer 204 is Ni, and thickness is 50 angstroms to 200 angstroms, using physical vapor
Depositing operation forms the first metal layer 204,
In the present embodiment, the material of the first metal layer 204 is by the O in environment in order to prevent2It is aoxidized, is forming the first gold medal
Belong to layer 204 after, 204 surface of the first metal layer formed protective layer 205, the protective layer 205 so that the first metal layer 204 with
O2Isolation is opened；The material of the protective layer 205 is Ti, Ta, TiN or TaN.
Also, in order to make the first metal layer to be formed 204 be contacted closely with 203 surface of doped region, forming the first metal
Can also include step before layer 204：203 surface of doped region is started the cleaning processing.In the present embodiment, the cleaning treatment
Technique be wet etching, the impurity on removal doped region 203 surface provides good interfacial state to form the first metal layer 204,
To make the first metal layer 204 and 203 intimate surface contact of doped region, the first metal contact layer being subsequently formed is advantageously reduced
With the contact resistance between doped region 203, the electric property of semiconductor devices is improved.
Referring to FIG. 7, to the first metal layer 204（Please refer to Fig. 6）The first annealing is carried out, in doped region 203
Surface forms the first metal contact layer 206.
First metal contact layer 206 for reducing semiconductor devices contact resistance.
First annealing is step annealing processing or multiple step anneal processing.The multiple step anneal processing includes first
Step annealing processing and second step annealing.The present embodiment handles presenting a demonstration property to carry out multiple step anneal to the first metal layer 204
Explanation.
The first step annealing can be that immersion is annealed, and annealing temperature is 250 degree to 350 degree, and anneal duration is
20 seconds to 90 seconds；The first step annealing or Millisecond annealing, annealing temperature are 650 degree to 950 degree, anneal duration
It is 0.25 millisecond to 20 milliseconds.
After the first step makes annealing treatment, nickel and the silicon on 203 surface of doped region in the first metal layer 204 react,
Form Ni2Si layers；To the Ni of formation2Si layers of progress second step annealing.
The second step annealing can be that immersion is annealed, and annealing temperature is 350 degree to 500 degree, and anneal duration is
20 seconds to 90 seconds；The second step annealing or spike annealing, annealing temperature are 350 degree to 550 degree.
After second step makes annealing treatment, the Ni2Si and the silicon on 103 surface of doped region continue to react, doped region
203 surfaces form the first metal contact layer 206.The material of first metal contact layer 206 is NiSi, and the resistivity of NiSi is small
And stability ratio Ni2Si high.Therefore, the material of the first metal contact layer 206 formed after double annealing is handled is NiSi,
Be conducive to improve the stability of the first metal contact layer 206 and reduce resistance.
Further include step after forming the first metal contact layer 206：What removal was not chemically reacted with substrate 200
The first metal layer 204.In the present embodiment, matcoveredn 205 is formed on 204 surface of the first metal layer（Please refer to Fig. 6）, then going
While except unreacted the first metal layer 204, protective layer 205 is removed, unreacted first is removed using wet-etching technology
Metal layer 204 and protective layer 205.As one embodiment, the etch liquids of the wet-etching technology are sulfuric acid and hydrogen peroxide
Mixed solution.
Referring to FIG. 8, forming second metal layer 207, the second metal layer on 206 surface of the first metal contact layer
207 have the function of adjusting the schottky barrier height between the first metal contact layer 206 and substrate 200.
Although foring the first metal contact layer 206 on 203 surface of doped region, the first metal contact layer formed
206 are still not enough to the contact resistance of semiconductor devices being reduced in expected range.Due to contact resistance and contact resistivity at
Proportional relationship can effectively reduce the contact resistance of semiconductor devices by reducing contact resistivity, and the present embodiment, which uses, to be subtracted
The method of small contact resistivity reduces the purpose of contact of semiconductor device resistance to realize.Due to contact resistivity and Schottky gesture
It is related to build height, can reduce contact resistivity by reducing schottky barrier height.
In order to reduce the schottky barrier height between the first metal contact layer 206 and substrate 200, low barrier material can be used
（Low effective work function material）First metal contact layer 206 is doped, to reduce contact resistivity, to reduce semiconductor
The contact resistance of device；Also, the low barrier material also needs to meet the shadow to the first metal contact layer 206 resistance of itself
Small characteristic is rung, to prevent from but causing the first metal contact layer 206 resistance itself while reducing schottky barrier height
The problem of drastically becoming larger prevents from carrying out harmful effect to reducing contact of semiconductor device resistance band.Therefore, second metal layer 207
The effective work function of metallic atom is less than the effective work function of the metallic atom of the first metal layer.
In summary consider, the metallic atom of second metal layer 207 includes Al, Pt, Pd or rare earth metal, wherein rare earth
Metal is Yb or Er.
Since Al costs are lower, in the present embodiment, the metallic atom of the second metal layer 207 includes Al, when the second gold medal
When the metallic atom for belonging to layer 207 includes Al, the material of the second metal layer 207 can be Al, TiAl or TaAl.
Al in follow-up second metal layer 207 can be diffused in the first metal contact layer 206, if second metal layer 207
When material is Al, then follow-up Al diffusion velocities may be too fast, causes the Al in the second metal contact layer being subsequently formed to exist and divides
Cloth uneven phenomenon is unfavorable for improving schottky barrier height；Therefore, the material of second metal layer 207 is TiAl in the present embodiment
Or TaAl inhibits diffusion velocities of the follow-up Al in the first metal contact layer 206 so that Al to the greatest extent may be used by forming alloy material
Energy is evenly distributed in the second metal contact layer, and the material homogeneity of the second metal contact layer of formation is good, is more advantageous to
Reduce the schottky barrier height between the second metal contact layer and substrate 200.
The second metal layer 207 is formed using atomic layer deposition, chemical vapor deposition or physical gas-phase deposition.
In the present embodiment, the material of the second metal layer 207 is TiAl, and the thickness of the second metal layer 207 is 5 angstroms
To 20 angstroms.
Further include step it should also be noted that, before forming second metal layer 207：To the first metal contact layer 206
Surface carries out prerinse processing, and the technique of the prerinse processing is wet etching or plasma cleaning.First metal is contacted
The purpose that 206 surface of layer carry out prerinse processing is：The impurity for removing 206 surface of the first metal contact layer, to form second
Metal layer 207 provides good interfacial state so that the Al in follow-up second metal layer 207 is easier to diffuse to the first metal contact layer
In 206.This is because：
If 206 surface of the first metal contact layer has impurity, in the 206 surface shape of the first metal contact layer with impurity
At second metal layer 207 and the first metal contact layer 206 between there is hole, the Al in second metal layer 207 is difficult to pass through
Hole and diffuse in the first metal contact layer 206.
Referring to FIG. 9, to the second metal layer 207（Please refer to Fig. 8）The second annealing is carried out, second metal layer is made
Metal in 207 diffuses to the first metal contact layer 206（Please refer to Fig. 8）It is interior, the first metal contact layer 206 is converted into second
Metal contact layer 208.
In the present embodiment, the material of second metal layer 207 is TiAl, and the material of the first metal contact layer 206 is NiSi；
Under the process conditions of second annealing, Ti atoms are difficult to spread, and Al atoms are spread into the first metal contact layer 206, shape
At the second metal contact layer 208, the material of second metal contact layer 208 is NiAlSi.
Due to the lower effective work function of Al, effective work function is 4.1ev to 4.3ev, the second metal contact layer 208
Compared with the first metal contact layer 206, effective work function reduces, the Effective power of the second metal contact layer 208 and substrate 200
The difference of function is reduced, and to reduce the schottky barrier height between the second metal contact layer 208 and substrate 200, reaches drop
The purpose of lower contact resistance, and then the contact resistance of semiconductor devices is reduced, improve the driveability of semiconductor devices.
In the present embodiment, after being initially formed the first metal contact layer 206 with low-resistivity, then in the first gold medal
Belong to the method that contact layer 206 surface forms second metal layer 207 so that the second metal contact layer 208 resistance of of formation itself
It is low, be conducive to the speed of service for improving semiconductor devices.
Need to illustrate when, the second annealing of this implementation and the first annealing above-mentioned are different annealing step
Suddenly, it is not completed in the technique with along with.If forming metal layer containing Ni and metal layer containing Al and then carrying out at annealing
Reason forms the second metal contact layer material（AlNiSi）, then since the diffusivity of the diffusivity of Al ratio Ni is strong, Al at first with
The material of substrate 200 reacts to form the silicide of Al so that the material of substrate 200 that residue can react with Ni compared with
Few, the suicide of Ni is too low, due to the resistivity of silicide of the resistivity much larger than Ni of the silicide of Al so that formed
The second metal contact layer itself resistance it is excessive, be unfavorable for optimize semiconductor devices electric property.
Also, the present embodiment forms second metal contact layer 208 using the technique of the second annealing so that diffusion
It is evenly distributed to the metallic atom in the first metal contact layer 206, particularly, in the second metal contact layer 208 and substrate 200
The Al atoms of intersection are evenly distributed, and it is high to be more advantageous to the Schottky barrier reduced between the second metal contact layer 208 and substrate 200
Degree.
Second annealing is immersion annealing, spike annealing, Millisecond annealing or laser annealing.
When second annealing is immersion annealing, the technological parameter of the immersion annealing is：Annealing temperature is
200 degree to 600 degree, anneal duration is 5 seconds to 120 seconds.
When second annealing is spike annealing, the technological parameter of the spike annealing is：Annealing temperature is 300 degree
To 800 degree.
When second annealing is Millisecond annealing or laser annealing, the technique ginseng of the Millisecond annealing or laser annealing
Number is：Annealing temperature is 500 degree to 900 degree, and anneal duration is 0.1 millisecond to 1 second.
Further include step after forming the second metal contact layer 208：The second gold medal after the second annealing of removal experience
Belong to layer 207,207 material of second metal layer at this time is mainly Ti atoms.
To sum up, the technical solution of semiconductor devices provided by the invention has the following advantages：
First, the present invention forms the first metal layer on doped region surface；After the first annealing being carried out to the first metal layer
Form the first metal contact layer；Second metal layer is formed on the first metal contact layer surface, and second metal layer has and adjusts the
The effect of schottky barrier height between one metal contact layer and substrate；Second annealing is carried out to second metal layer so that
Metallic atom in second metal diffuses in the first metal contact layer, also, since under the action of annealing, metal is former
Distribution uniform of the son in the second metal contact layer, equally distributed metallic atom, which is more advantageous to, reduces the second metal contact layer
Effective work function so that the ability that metallic atom adjusts the schottky barrier height between the second metal contact layer and substrate obtains
Effective to play, the reduction of Schottky barrier advantageously reduces contact resistivity, to reduce the contact resistance of semiconductor devices,
Improve the speed of service of semiconductor devices.
Secondly, the material of second metal layer of the present invention is TiAl, wherein the effective work function of metallic atom Al is relatively low, expands
It is dissipated in the first metal contact layer and is formed after the second metal contact layer, the Xiao Te between the second metal contact layer and substrate can be reduced
Base barrier height；Also, the Ti in second metal layer plays certain inhibiting effect to the diffusion of Al atoms, prevents Al atoms from expanding
Scattered too fast, diffusion velocity appropriate is more advantageous to Al atoms being uniformly distributed in the second metal contact layer, to further drop
Schottky barrier height between low second metal contact layer and substrate reduces the contact resistance of semiconductor devices, optimizes semiconductor
The driveability of device.
Again, it forms the technique of the first metal contact layer to handle for double annealing, the material of the first metal contact layer is
NiSi, the NiSi characteristic relatively low with resistivity and high stability in nickle silicide series material, so that the second metal
Contact layer also has the characteristic that resistivity is low, stability is high, advanced optimizes the electric property of semiconductor devices.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (18)
1. a kind of forming method of semiconductor devices, which is characterized in that including：
Substrate is provided, the substrate surface is formed with gate structure；
The substrate of the gate structure both sides is doped, doped region is formed in the substrate；
The first metal layer is formed on the doped region surface；
First annealing is carried out to the first metal layer, the first metal contact layer is formed on doped region surface；
Second metal layer is formed on first metal contact layer surface, the second metal layer, which has, adjusts the contact of the first metal
The effect of schottky barrier height between layer and substrate, and the material of the second metal layer is TiAl or TaAl；
Second annealing is carried out to the second metal layer, so that the metallic atom in second metal layer is diffused to the first metal and connects
In contact layer, it converts the first metal contact layer to the second metal contact layer, and the Schottky between the second metal contact layer and substrate
Barrier height is less than the schottky barrier height between the first metal contact layer and substrate.
2. the forming method of semiconductor devices according to claim 1, which is characterized in that the metal of the second metal layer
The effective work function of atom is less than the effective work function of the metallic atom of the first metal layer.
3. the forming method of semiconductor devices according to claim 1, which is characterized in that second metal contact layer
Material is NiAlSi.
4. the forming method of semiconductor devices according to claim 1, which is characterized in that using atomic layer deposition, chemistry
Vapor deposition or physical gas-phase deposition form the second metal layer.
5. the forming method of semiconductor devices according to claim 1, which is characterized in that the thickness of the second metal layer
It is 5 angstroms to 20 angstroms.
6. the forming method of semiconductor devices according to claim 1, which is characterized in that second annealing is leaching
Enter formula annealing, spike annealing, Millisecond annealing or laser annealing.
7. the forming method of semiconductor devices according to claim 6, which is characterized in that the technique of the immersion annealing
Parameter is：Annealing temperature is 200 degree to 600 degree, and anneal duration is 5 seconds to 120 seconds；The technological parameter of the spike annealing is：
Annealing temperature is 300 degree to 800 degree；The Millisecond annealing or the technological parameter of laser annealing are：Annealing temperature be 500 degree extremely
900 degree, anneal duration is 0.1 millisecond to 1 second.
8. the forming method of semiconductor devices according to claim 1, which is characterized in that formed second metal layer it
Before, further include step：Prerinse processing is carried out to the first metal contact layer surface, the technique of the prerinse processing is carved for wet method
Erosion or plasma cleaning.
9. the forming method of semiconductor devices according to claim 1, which is characterized in that the material of the first metal layer
For the monometallic or alloy of Ni, W, Ti, Ta, Pt, Co.
10. the forming method of semiconductor devices according to claim 1, which is characterized in that it is described first annealing be
The processing of one step annealing or multiple step anneal processing.
11. the forming method of semiconductor devices according to claim 10, which is characterized in that the multiple step anneal processing packet
Include first step annealing and second step annealing.
12. the forming method of semiconductor devices according to claim 11, which is characterized in that the first step annealing
It anneals for immersion, annealing temperature is 250 degree to 350 degree, and anneal duration is 20 seconds to 90 seconds；Or the first step annealing
For Millisecond annealing, annealing temperature is 650 degree to 950 degree, and anneal duration is 0.25 millisecond to 20 milliseconds.
13. the forming method of semiconductor devices according to claim 11, which is characterized in that the second step annealing
It anneals for immersion, annealing temperature is 350 degree to 500 degree, and anneal duration is 20 seconds to 90 seconds；Or the second step annealing
For spike annealing, annealing temperature is 350 degree to 550 degree.
14. the forming method of semiconductor devices according to claim 1, which is characterized in that formed the first metal layer it
Further include step before carrying out the first annealing afterwards：Protective layer is formed on the first metal layer surface.
15. the forming method of semiconductor devices according to claim 14, which is characterized in that the material of the protective layer is
Ti, Ta, TiN or TaN.
16. the forming method of semiconductor devices according to claim 14, which is characterized in that forming the contact of the first metal
After layer, the protective layer is removed.
17. the forming method of semiconductor devices according to claim 1, which is characterized in that before forming doped region, also
Including step：Groove is formed in the substrate of gate structure both sides；The full groove of filling is formed using selective epitaxial process
Stressor layers.
18. the forming method of semiconductor devices according to claim 1, which is characterized in that the semiconductor devices of formation is
NMOS transistor, PMOS transistor or CMOS transistor.
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| CN102983163A (en) * | 2011-09-07 | 2013-03-20 | 中国科学院微电子研究所 | Low source-drain contact resistance MOSFETs and method of making same |
| CN103000675A (en) * | 2011-09-08 | 2013-03-27 | 中国科学院微电子研究所 | Low source-drain contact resistance MOSFETS and method of making same |
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| CN102983163A (en) * | 2011-09-07 | 2013-03-20 | 中国科学院微电子研究所 | Low source-drain contact resistance MOSFETs and method of making same |
| CN103000675A (en) * | 2011-09-08 | 2013-03-27 | 中国科学院微电子研究所 | Low source-drain contact resistance MOSFETS and method of making same |
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