CN104810026A - 一种读头传感器 - Google Patents
一种读头传感器 Download PDFInfo
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Abstract
本发明的公开一般涉及一种读头传感器,特别是在记录磁头中的读头传感器。读头传感器包括传感器叠层内的双包覆层,用于减少磁耦合从而增强读头传感器中的磁偏置场,例如,域控制。更进一步,具有不同膜特性的多个膜叠层的上屏蔽也被用于增强对读头传感器产生的偏置场。另外,线圈结构定位在侧屏蔽附近,用于增强读头传感器中的偏置场产生。
Description
技术领域
本发明的实施例涉及用于硬盘驱动器的磁读头传感器。读头传感器是磁阻效应类型。进一步地,实施例涉及传感器中使用双包覆层的读头传感器。
背景技术
计算机的核心是磁盘驱动器,磁盘驱动器通常包括旋转磁盘、具有读头和写头的滑动块、在旋转磁盘上方的吊臂和致动器臂,其中致动器臂摆动吊臂从而将读头和/或写头放置在旋转磁盘的选定环形磁道上方。当磁盘不旋转时,吊臂使滑动块偏离磁盘的表面;但当磁盘旋转时,空气被邻近滑动块的空气轴承表面(ABS)的旋转磁盘盘旋,引发滑动块在空气轴承上沿旋转磁盘的表面滑行轻微的距离。当滑动块骑行在空气轴承上时,写头和读头用于写和读对应于宿主数据的磁性转变。读头和写头连接至信号处理电路,该信号处理电路根据计算机程序运行以实现写入和读取功能。
硬盘驱动器的读头包括使用磁阻效应的自旋阀元件。通过感测夹有中间层的两个铁磁膜(诸如自由磁层和钉扎[pinned]磁层)的相对磁化,磁信息可从磁盘上纳米级的磁体中读取。传感器元件的各种尺寸的缩减和膜特性的改进已帮助改进记录密度,使得当前的记录磁道达到宽度小于约100纳米。然而,由于磁道宽度变小,在自由磁层的磁化过程中由热振动产生的噪声(磁噪mag-noise)对磁头的信噪比(SNR)的影响变得过分地大。由于磁噪的增加与回播输出的增加成比例,因此磁头SNR在某一最大值时饱和。因而,减少磁噪已变得尤其重要。自由磁层的磁偏置(域控制)和用于低磁耦合的控制对于减少磁噪是有效的。
因此,在本技术领域中需要能够利用传感器结构中的低磁耦合最小化磁噪的传感器结构。
发明内容
本发明涉及记录磁头中的读头传感器。读头传感器具有双包覆层,其可减少磁耦合从而增强读头传感器中的磁偏置场,例如域控制。并且,具有不同膜特性的多个膜叠层的上屏蔽也被用于增强读头传感器中的偏置场产生。另外,线圈结构可定位于侧屏蔽附近。定位于侧屏蔽附近的线圈结构可有效地改变和调整对传感器产生的偏置场,从而有效地控制信噪比(SNR)并增加读头传感器的域控制。
在一个实施例中,读头传感器具有下屏蔽、设置在下屏蔽上方的上屏蔽和设置在下屏蔽和上屏蔽之间的传感器叠层。其中传感器叠层包括钉扎磁层、设置在钉扎磁层上方的间隔层、设置在间隔层上方的自由磁层、和设置在自由磁层上的双包覆层,双包覆层包括设置在非磁层上的磁层和设置在下屏蔽上方和上屏蔽下方的传感器叠层附近的侧屏蔽。
在另一实施例中,读头传感器包括下屏蔽、设置在下屏蔽上方的上屏蔽、设置在下屏蔽和上屏蔽之间的传感器叠层、和在下屏蔽上方和上屏蔽下方的传感器叠层附近的侧屏蔽。其中上屏蔽包括底部磁层、设置在底部磁层上的第一非磁层、设置在第一非磁层上的具有三层磁性膜叠层的顶部磁层和设置在顶部磁层上的反铁磁层。底部磁层包括第一磁层和设置在第一磁层上的第二磁层。
在另一实施例中,读头传感器包括下屏蔽、设置在下屏蔽上方的上屏蔽、设置在下屏蔽和上屏蔽之间的传感器叠层、在下屏蔽上方和上屏蔽下方的传感器叠层附近的侧屏蔽、以及耦合到侧屏蔽的线圈结构。
附图说明
为了具体理解本公开的上述特性,可以通过参考实施例获得上述简要地总结的本公开的更详尽的描述。其中的一些实施例将以附图说明。然而,应注意的是附图仅说明了本公开的典型实施例,因而并不局限于此范围,本公开允许其他相同效果的实施例。
图1说明了根据本发明实施例的示例性磁盘驱动器;
图2是根据本发明一实施例的图1磁盘驱动器的读头/写头和磁盘的侧视图;
图3是根据本发明一实施例的读头的示意图;
图4是根据本发明另一实施例的读头的示意图;
图5是非磁层厚度变化与读头传感器中产生的偏置场大小之间关系的图形描述;以及
图6是根据一实施例的侧屏蔽的三维示意图,其中,侧屏蔽是设置在图3或图4的读头传感器中并带有设置在侧屏蔽附近的线圈结构。
为便于理解,不同附图中使用相同附图标记来指示相似或相同的元件。在一实施例中公开的元件也同样用于其他实施例而无须明确的说明。然而,要注意的是附图仅说明了本发明的典型实施例,因而并不局限于此范围,本公开允许在涉及磁传感器的任何领域中的其他相同效果的实施例;
具体实施方式
在下文中,参考本公开的实施例。但应了解本发明并不限于所述的具体实施例。相反,任何以下特征和元件的组合,不论是否与各实施例有关,都可用来实施本发明。此外,虽然本发明各实施例相对其它可能的方案和/或现有技术可能有一些优点,但某个实施例能否实现某具体优点并不是本发明的一个限制。因此,下面的方面、特征、实施例和优点只是示例性的,且除非在某一个或多个权利要求中明确指出,它们都不能被认为是所附权利要求书的元件或限制。类似地,提到“本公开”并不应解释为这里公开的任何本发明主题的概括,也不应解释为是所附权利要求的元件或限制,除非在一个或多个权利要求中明确记载以外。
本发明一般涉及记录磁头中的读头传感器。除了夹于上屏蔽和下屏蔽之间的传感器叠层之外,读头传感器还包括侧屏蔽。上屏蔽是带有反铁磁耦合的多层结构。从上屏蔽到传感器叠层的磁耦合被控制得低,从而增强了产生的磁偏置场和在传感器叠层中形成的自由层的域控制。在一个实施例中,低磁耦合是通过使用传感器叠层中自由层上形成的上部双包覆层获得的。另外,具有不同膜特性布置的多个膜层也可用于上屏蔽中。线圈结构也被设置于侧屏蔽附近以增强偏置场的产生。
图1是根据本公开的实施例的示例性硬盘驱动器(HDD)100的顶部视图。如图所示,HDD 100包括一个或多个磁盘110、致动器120、与每一磁盘110关联的致动器臂130和附着于底盘150中的主轴电机140。如图1所示,一个或多个磁盘110可垂直放置。此外,一个或多个磁盘110可耦合于主轴电机140。
磁盘110可包括在盘110的顶部和底部表面上的数据环形磁道。磁头180被装配并耦合至致动器臂130。当每一磁盘110旋转时,数据可写入到数据磁道和/或从数据磁道读取。致动器臂130被配置为围绕致动器轴131旋转,从而将磁头180放置到磁盘110中的特定数据磁道上。
图2是面向磁盘202的读头/写头200的中心的部分横截面视图。读头/写头200和磁盘202分别对应于图1中的磁头180和磁盘110。在一些实施例中,磁盘202是“双层”介质,包括垂直的磁数据记录层(RL)204,该层位于“软的”或低矫顽性的导磁底层(PL)206上。读头/写头200包括例如空气轴承表面(ABS)的面向介质的表面(MFS)209、磁写头220和磁读头传感器222,并且安装为面向介质的表面(MFS)209面向磁盘202。在图2中,磁盘202以箭头232所示方向移过磁头200。磁数据记录层(RL)204用垂直记录的或磁化的区域212说明,使相邻的区域212具有位于磁数据记录层(RL)204中的箭头211代表的磁化方向。相邻的磁化区域212的磁场可由感测元件230检测为记录的比特。写头220包括磁路224,该磁路224由主极232和嵌入在无磁材料219的部分中所示的薄膜线圈218组成。
在这里讨论的实施例中,读头传感器222是侧屏蔽读头传感器。侧屏蔽读头传感器包括在自旋阀元件的磁道宽度方向上的软磁体,从而导致在磁道宽度方向上读敏感性分布的磁裙区域的读敏感性减小。出现读敏感性分布的磁裙减小是由于自旋阀元件捕获在记录磁道的中心部分产生的磁场并且由软磁体形成的磁屏蔽吸收由除中心部分之外的记录磁道的部分产生的磁场。通过减少敏感性分布的磁裙,可以改进磁道密度,因为能够减少读噪声和邻近磁道的干涉。
在一实施例中,读头传感器222具有与上屏蔽S2的强磁耦合,信号噪声通常高,这不利于数据读/写容量。因而,维持读头传感器222与上屏蔽S2之间的低磁耦合有利于增强它们之间产生的偏置场,并因此增加域控制能力。
图3是磁读头传感器300的面向介质的表面(MFS)的视图,与图2描述的读头/写头200相似,具有形成在传感器叠层350中的双包覆层314。如上面图2中详细描述,读头300包括传感器叠层350,传感器叠层350形成在下屏蔽S1和上屏蔽S2之间。传感器叠层350包括设置在下屏蔽S1上的底层301和第一反铁磁层302。底层301可以包括Ta、Ru或Ta和Ru的化合物,并且厚度大约是3纳米。在一个实施例中,第一反铁磁层302包括PtMn、IrMn、PtPdMn、NiMn或其组合,并且厚度大约是60埃。在一个实施例中,第一反铁磁层302的厚度可以大约是4纳米。而后,钉扎磁层304设置在第一反铁磁层302上。钉扎磁层304的厚度可以大约是2纳米。钉扎磁层304包括固定层的若干类型之一,例如简单固定的、逆平行固定的、自固定的或反铁磁固定的传感器。固定和参考层可由多种磁材料构建,例如,NiFe、CoFe、CoFeB或稀释磁合金。
间隔层306,在隧道结磁阻(TMR)传感器的情况下是氧化物阻挡层或者在巨磁阻(GMR)传感器的情况下是导电层,其设置在自由磁层308的下面的钉扎磁层304上。如果读头300是TMR传感器,则间隔层306包括MgO、HfO2、TiO2或Al2O3。如果读头300是GMR传感器,则间隔层306包括非导磁材料,例如铜。间隔层306的厚度约为1纳米。
自由磁层308设置在间隔层306上。自由磁层308包括Co、Fe、Ni、B或其组合,例如CoFe、CoFeB或CoFeNiB。自由磁层308的厚度在大约15埃和大约75埃之间。在一个实施例中,厚度大约是6纳米。
双包覆层314形成在自由磁层308上。在一个实施例中,双包覆层314包括设置在非磁层310上的磁层312。与常规的磁包覆层不同,双包覆层314包括设置在非磁层310上的磁层312。相信包括在双包覆层314中的非磁层310可以有效地减少自由磁层308和上屏蔽S2之间的磁耦合,并因而增加邻近传感器叠层350产生的偏置场。理想的是将磁耦合保持在最小的范围内,因为所产生的磁耦合将导致非期望的磁噪声增加和信噪比(SNR)减少的结果。因而,通过使用包括形成在其中并在自由磁层308上的非磁层310的双包覆层314,可有效实现磁解耦,从而增加了对传感器叠层350产生的偏置场并增强了自由磁层308中的域控制能力。由此,通过使用在自由磁层308上的双包覆层314中的非磁层310,自由磁层308和上屏蔽S1之间的磁耦合能有效减弱(例如,磁解耦),因而消除了磁噪声并增加了域控制能力。非磁层310还提供了自由磁层308和上屏蔽S2之间额外的磁间隔,从而减弱了它们之间的磁耦合。由非磁层310创建的额外磁间隔可保持为最小(例如,非磁层310的薄的厚度),从而消除了读间隙。读间隙会不利地减小数据密度。在一个实施例中,非磁层310的厚度控制在小于1纳米,比如小于0.8纳米,例如在大约0.1纳米和大约0.5纳米之间。
在一个实施例中,非磁层310可由非磁(例如,去磁)材料制造,非磁材料可从包括Ta、Ma等的组中选取。在一个示例中,非磁层310是厚度在大约0.1纳米和大约0.5纳米之间的Ta层。
此外,设置在非磁层310上的磁层312还可由选定的磁材料制造,其可以铁磁耦合到上屏蔽S2,以根据需要提供增强的磁偏置。在一个实施例中,磁层312是从包括NiFe、CoFe和FeCoNi的组中选取的磁材料制造的。在一实施例中,磁层312是厚度在大约1纳米和大约6纳米之间的NiFe层。
由导电材料构成设置在传感器叠层350的下面和上面的下屏蔽S1和上屏蔽S2,该导电材料的功能是作为电导线为传感器叠层350提供感测电流,另外还作为磁屏蔽。在一个实施例中,下屏蔽S1由磁材料构造,例如NiFe。
上屏蔽S2包括多层。上屏蔽S2包括由非磁间隔层318间隔开的底部磁层316和顶部磁层320。第二反铁磁层330设置在顶部磁层320上。第二反铁磁层330包括PtMn、IrMn、PtPdMn、NiMn或其组合,并且厚度大约是60埃。非磁间隔层318包括Ta、TaO、Ru、Rh、NiCr、SiC或Al2O3。底部磁层316和顶部磁层320均包括铁磁材料。可供使用的合适的铁磁材料包括Ni、Fe、Co、NiFe、NiFeCo、NiCo、CoFe和其组合。顶部磁层320与底部磁层316反铁磁性地耦合,并且顶部磁层320的磁化由第二反铁磁层330单向地固定。在一个实施例中,上屏蔽S2包括作为三层结构的IrMn/NiFe/Ru/NiFe。
绝缘层321沿传感器叠层350的侧壁并在下屏蔽S1的上面设置。绝缘层321包括绝缘材料,例如氧化铝或氮化硅。绝缘层321可通过例如原子层沉积(ALD)、化学气相沉积(CVD)和离子束溅射(IBD)的已知的沉积方法沉积。
侧屏蔽322设置在绝缘层321上。侧屏蔽322包括铁磁材料。可供使用的合适的铁磁材料包括Ni、Fe、Co、NiFe、NiFeCo、NiCo、CoFe和其组合。上屏蔽S2的底部磁层316和侧屏蔽322是铁磁耦合的。采取此结构的原因是实现自旋阀元件中自由磁层308的足够的域稳定性。上屏蔽S2由于反铁磁耦合结构是磁稳定的。侧屏蔽322也是稳定的,因为其是铁磁耦合到稳定的上屏蔽S2。在此情况下,从侧屏蔽322到自由磁层308的偏置场变得稳定并具有足够的自由磁层的域稳定性。
图4描述了读头传感器400的另一实施例,读头传感器400具有沿形成在传感器叠层350中的双包覆层314的上屏蔽S2的不同的多膜结构。相信通过使用具有特定选择材料的多层的上屏蔽S2,由于反铁磁耦合结构,可以保持期望范围的磁导率而不会出现不利的减少。来自反铁磁耦合结构的上屏蔽S2的磁稳定状态将潜在地减小磁导率。当磁导率小时,屏蔽效果变小,从而读取分辨率变差。当读取记录的信号时,如果读取分辨率变差,则由于增加的磁转换噪声,信噪比(SNR)降低,引起误差率变大。因而,通过使用图4中描述的读头传感器400中的上屏蔽S2的多膜结构,可以获得期望范围的磁导率和高读取分辨率,同时提供了足够的域稳定性。
在一实施例中,读头传感器400的上屏蔽S2具有由非磁间隔层318间隔开的底部磁层408和顶部磁层405。非磁间隔层318与图3中描述的非磁间隔层318相似。第二反铁磁层330设置在顶部磁层405上。第二反铁磁层330包括PtMn、MnIr、PtPdMn、NiMn或其组合,并且厚度大约是60埃。非磁间隔层318包括Ta、TaO、Ru、Rh、NiCr、SiC或Al2O3。
与图3中描述的底部磁层316和顶部磁层320的单层结构不同,读头传感器400的底部磁层408和顶部磁层405包括多个层。在一个实施例中,底部磁层408包括设置在第二磁层407上的第一磁层406。顶部磁层405包括复合结构,该复合结构具有包括三种磁材料403、402、401的膜叠层。每一磁材料401、402、403、406、407包括铁磁材料。可供使用的合适的铁磁材料包括Ni、Fe、Co、NiFe、NiFeCo、NiCo、CoFe和其组合。在一个特别的实施例中,顶部磁层405包括CoFe/NiFe/CoFe膜叠层(磁层403、402、401)并且底部磁层408包括CoFe/NiFe膜叠层(磁层406、407)。因而,读头传感器400的上屏蔽S2包括从上部第二反铁磁层330到底部磁层408的Mnlr/CoFe/NiFe/CoFe/Ru/CoFe/NiFe膜结构。
在图3-4中,自由磁层308中的偏置场方向是反平行于上屏蔽S2的底部磁层316、408的磁化方向。通过反方向的偏置场有效地弱化了上屏蔽S2的底部磁层316、408的磁各向异性和磁耦合,从而上屏蔽S2的磁导率增加,同时其结果是改进了读取分辨率。
通过使用传感器叠层350中的双包覆层314,弱化了自由磁层308和上屏蔽S2之间的磁耦合,提供了增加的偏置场。如图5所示,包括设置在非磁层310上的磁层312的双包覆层314,利用非磁层310的薄厚度,有效地将偏置场(方点)增加至大约80 Oe,与之相比,没有非磁层310的常规的包覆层(圆点)为大约20 Oe。在双包覆层314中沿着磁层312的非磁层310的使用,与常规的应用相比,增加了约2倍至4倍的偏置场强度。因此,由于偏置场增加,改进了自由磁层308的域可控性以及读取分辨率。
图6是根据一个实施例的侧屏蔽322的三维示意图,其中侧屏蔽322设置在图3或4的读头300、400中,并带有设置于侧屏蔽322附近的线圈结构602。侧屏蔽322沿传感器叠层350的侧壁并在下屏蔽S1的上面和上屏蔽S2的下面设置。如上所述,为了保持低的磁噪,保持自由磁层308和上屏蔽S2之间低的磁耦合,从而增加了它们之间产生的偏置场。更进一步,相信所产生的偏置场高度地与侧屏蔽322贡献的磁场相关。因而,通过添加设置于侧屏蔽322附近的线圈结构602,当通过在通电时的线圈结构602的增强增加了来自侧屏蔽的磁场时,可以进一步增加和调整偏置场强度。
在一个实施例中,线圈结构602包括具有螺旋形配置的多个线圈绕组604。线圈结构602围绕在侧屏蔽322的***。线圈结构602可定位在侧屏蔽322附近任何合适的位置,以便增强侧屏蔽322产生的磁场的位置控制,这将影响和有利于对传感器叠层350的偏置场产生的水平。在运行中,线圈结构602通过发电机606由为线圈结构602供应的电压功率提供能量。施加到线圈结构602的电压功率影响由侧屏蔽322产生的磁场的水平。随着侧屏蔽322贡献的磁场的强度(例如,大小)改变并增强,传感器叠层350中产生的偏置场会增强和增加。因而,通过使用设置在侧屏蔽322附近的线圈结构602和施加到线圈结构602的功率电平,可控制传感器叠层350中产生的偏置场的不同水平,从而改进和优化了信噪比和磁存储密度。在一个实施例中,线圈结构602由金属材料制造。该金属材料可增强对侧屏蔽322的磁场产生。在一个实施例中,线圈结构602可由从包括不锈钢、铜、铝、镍、其合金等的材料的组中选取从材料制造。
因此,通过为上屏蔽S2以及双包覆层314使用多个层,可获得弱化的磁耦合。更进一步,线圈结构可进一步设置在侧屏蔽322附近(例如,围绕),从而增强了读头传感器300、400中的对传感器叠层350的偏置场产生。这样的读头传感器具有读写器使用可控性。通过保持低磁耦合和从侧屏蔽产生的增强磁场,可获得强偏置场。因此,下一代产品可采用超高密度记录的结构。
虽然上面针对本发明实施例,但是在不脱离本发明基本范围的情况下,可以获得本发明其他或进一步的实施例,因此本发明的范围由所附权利要求限定。
Claims (20)
1.一种读头传感器,包括:
下屏蔽;
上屏蔽,设置在所述下屏蔽上方;以及
传感器叠层,设置在所述下屏蔽和所述上屏蔽之间,其中所述传感器叠层包括:
钉扎磁层;
间隔层,设置在所述钉扎磁层之上;
自由磁层,设置在所述间隔层之上;以及
双包覆层,设置在所述自由磁层上,所述双包覆层包括设置在非磁层上的磁层;以及
侧屏蔽,设置在所述下屏蔽之上和所述上屏蔽下方的传感器叠层附近。
2.如权利要求1所述的读头传感器,其中,所述双包覆层中的磁层包括NiFe、CoFe或NiCoFe。
3.如权利要求1所述的读头传感器,其中,所述非磁层是Ta。
4.如权利要求1所述的读头传感器,其中,所述非磁层的厚度小于1纳米。
5.如权利要求1所述的读头传感器,其中,所述上屏蔽进一步包括:
底部磁层,所述底部磁层包括第一磁层和设置在所述第一磁层上的第二磁层;
第一非磁层,设置在所述底部磁层上;
顶部磁层,设置在所述第一非磁层上,所述顶部磁层包括三层磁性膜叠层;以及
反铁磁层,设置在所述顶部磁层上。
6.如权利要求5所述的读头传感器,其中,所述底部磁层中的第一和第二磁层选自NiFe、CoFe或NiCoFe中的至少一种。
7.如权利要求5所述的读头传感器,其中,所述第一磁层是CoFe并且所述第二磁层是NiFe。
8.如权利要求5所述的读头传感器,其中,所述顶部磁层中的三层磁性膜叠层包括被夹在CoFe层之间的NiFe层。
9.如权利要求8所述的读头传感器,进一步包括与所述侧屏蔽耦合的线圈结构。
10.如权利要求1所述的读头传感器,进一步包括与所述侧屏蔽耦合的线圈结构。
11.一种读头传感器,包括:
下屏蔽;
上屏蔽,设置在所述下屏蔽上方,其中所述上屏蔽包括:
底部磁层,所述底部磁层包括第一磁层和设置在所述第一磁层上的第二磁层;
第一非磁层,设置在所述底部磁层上;
顶部磁层,设置在所述第一非磁层上,所述顶部磁层包括三层磁性膜叠层;以及
反铁磁层,设置在所述顶部磁层上;
传感器叠层,设置在所述下屏蔽和所述上屏蔽之间;以及
侧屏蔽,设置在所述下屏蔽之上和所述上屏蔽下方的传感器叠层附近。
12.如权利要求11所述的读头传感器,其中,所述底部磁层中的第一和第二磁层选自NiFe、CoFe或NiCoFe中的至少一种。
13.如权利要求11所述的读头传感器,其中,所述第一磁层是CoFe、而所述第二磁层是NiFe。
14.如权利要求11所述的读头传感器,其中,所述顶部磁层中的三层磁性膜叠层包括被夹在CoFe层之间的NiFe层。
15.如权利要求11所述的读头传感器,其中,所述传感器叠层进一步包括:
钉扎磁层;
间隔层,设置在所述钉扎磁层之上;
自由磁层,设置在所述间隔层之上;以及
双包覆层,设置在所述自由磁层上,所述双包覆层包括设置在非磁层上的磁层。
16.如权利要求15所述的读头传感器,其中,所述双包覆层中的磁层包括NiFe、CoFe或NiCoFe。
17.如权利要求15所述的读头传感器,其中,所述非磁层是Ta。
18.如权利要求15所述的读头传感器,其中,所述非磁层厚度小于1纳米。
19.一种读头传感器,包括:
下屏蔽;
上屏蔽,设置在所述下屏蔽上方;
传感器叠层,设置在所述下屏蔽和所述上屏蔽之间;以及
侧屏蔽,设置在所述下屏蔽之上和所述上屏蔽下方的传感器叠层附近;以及
线圈结构,被设置为与所述侧屏蔽耦合。
20.如权利要求19所述的读头传感器,其中,所述传感器叠层进一步包括:
钉扎磁层;
间隔层,设置在所述钉扎磁层之上;
自由磁层,设置在所述间隔层之上;以及
双包覆层,设置在所述自由磁层上,所述双包覆层包括设置在Ta层上的NiFe层。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/166,699 | 2014-01-28 | ||
US14/166,699 US9183858B2 (en) | 2014-01-28 | 2014-01-28 | Dual capping layer utilized in a magnetoresistive effect sensor |
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JP (1) | JP5944022B2 (zh) |
KR (1) | KR20150089973A (zh) |
CN (1) | CN104810026A (zh) |
DE (1) | DE102015001085A1 (zh) |
GB (2) | GB2531906A (zh) |
IE (1) | IE20150021A1 (zh) |
IN (1) | IN2015DE00237A (zh) |
SG (1) | SG10201500652TA (zh) |
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US10032365B1 (en) | 2017-10-16 | 2018-07-24 | Universal Electronics Inc. | Apparatus, system and method for using a universal controlling device for displaying a graphical user element in a display device |
KR102354021B1 (ko) * | 2017-10-16 | 2022-01-24 | 티디케이가부시기가이샤 | 터널 자기 저항 효과 소자, 자기 메모리, 및 내장형 메모리 |
US10872626B2 (en) | 2018-03-06 | 2020-12-22 | Western Digital Technologies, Inc. | MAMR stack shape optimization for magnetic recording |
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- 2015-01-27 SG SG10201500652TA patent/SG10201500652TA/en unknown
- 2015-01-27 IE IE20150021A patent/IE20150021A1/en not_active IP Right Cessation
- 2015-01-28 JP JP2015014108A patent/JP5944022B2/ja active Active
- 2015-01-28 KR KR1020150013618A patent/KR20150089973A/ko active IP Right Grant
- 2015-01-28 CN CN201510100220.6A patent/CN104810026A/zh active Pending
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Also Published As
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GB2531906A (en) | 2016-05-04 |
GB201516399D0 (en) | 2015-10-28 |
JP2015141732A (ja) | 2015-08-03 |
IE20150021A1 (en) | 2015-07-29 |
GB201501239D0 (en) | 2015-03-11 |
KR20150089973A (ko) | 2015-08-05 |
GB2523467A (en) | 2015-08-26 |
US20150213816A1 (en) | 2015-07-30 |
US9183858B2 (en) | 2015-11-10 |
IN2015DE00237A (zh) | 2015-07-31 |
JP5944022B2 (ja) | 2016-07-05 |
SG10201500652TA (en) | 2015-08-28 |
DE102015001085A1 (de) | 2015-07-30 |
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