CN104795382A - 半导体封装 - Google Patents

半导体封装 Download PDF

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CN104795382A
CN104795382A CN201410784429.4A CN201410784429A CN104795382A CN 104795382 A CN104795382 A CN 104795382A CN 201410784429 A CN201410784429 A CN 201410784429A CN 104795382 A CN104795382 A CN 104795382A
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semiconductor chip
interlayer hole
weld pad
hole connector
semiconductor
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林子闳
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MediaTek Inc
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MediaTek Inc
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Abstract

本发明公开一种半导体封装。所述半导体封装包括：第一半导体芯片，其上具有多个焊垫；以及第一介层孔插塞和第二介层孔插塞，分别设置于所述第一半导体芯片上，所述第一介层孔插塞连接至所述第一半导体芯片的所述多个焊垫中的至少两个。本发明所公开的半导体封装，利用介层孔插塞连接至配置于半导体芯片的多个焊垫，上述介层孔插塞的设计可用来改善信号完整性。

Description

半导体封装
技术领域
本发明有关于一种半导体封装，特别是有关于一种半导体封装的介层孔插塞设计。
背景技术
对半导体封装的设计而言，需要因应多功能芯片而增加输入/输出(I/O)连接数量。上述的影响会迫使印刷电路板制造商缩小线宽或线距或发展出芯片直接接触(direct chip attach，DCA)半导体。然而，多功能芯片封装因增加了输入/输出(I/O)连接数量会导致热电特性问题，举例来说，散热问题、串音(crosstalk)、信号传输延迟(signal propagation delay)或射频(RF)电路的电磁干扰等问题。上述热电特性问题会影响产品的可靠度和品质。
因此，在此技术领域中，有需要一种高密度的半导体封装，以改善上述缺点。
发明内容
有鉴于此，本发明提供一种改良式的半导体封装。
依据本发明一实施方式，提供一种半导体封装，包括：第一半导体芯片，其上具有多个焊垫；第一介层孔插塞和一第二介层孔插塞，分别设置于所述第一半导体芯片上，其中所述第一介层孔插塞连接至所述第一半导体芯片的所述多个焊垫中的至少两个。
依据本发明另一实施方式，提供一种半导体封装，包括：第一半导体芯片，其上具有第一焊垫和第二焊垫，其中所述第一焊垫和所述第二焊垫均为电源垫或接地垫；第一介层孔插塞，设置于所述第一半导体芯片上，其中所述第一介层孔插塞连接至所述第一焊垫和所述第二焊垫。
依据本发明又一实施方式，提供一种半导体封装，包括：第一半导体芯片，其上具有多个焊垫；第一介层孔插塞，设置于所述第一半导体芯片上，其中所述第一介层孔插塞连接至所述第一半导体芯片的所述焊垫，所述第一介层孔插塞的俯视形状为网筛形或环形。
本发明所提供的半导体封装利用介层孔插塞连接至配置于半导体芯片的多个焊垫，上述介层孔插塞的设计可用来改善信号完整性。
对于已经阅读后续由各附图及内容所显示的较佳实施方式的本领域的技术人员来说，本发明的各目的是明显的。
附图说明
图1为本发明一实施例的半导体封装的剖示图。
图2为本发明一实施例的半导体封装的第一半导体芯片的俯视图，其显示半导体封装的第一半导体芯片的介层孔插塞的布局。
具体实施方式
在权利要求书及说明书中使用了某些词汇来指称特定的组件。所属领域中的技术人员应可理解，硬件制造商可能会用不同的名词来称呼同样的组件。本权利要求书及说明书并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的准则。在权利要求书及说明书中所提及的「包括」为开放式的用语，故应解释成「包括但不限定于」。另外，「耦接」一词在此包括任何直接及间接的电气连接手段。因此，若文中描述第一装置耦接于第二装置，则代表所述第一装置可直接电连接于所述第二装置，或通过其他装置或连接手段间接地电连接至所述第二装置。
为了让本发明的目的、特征、及优点能更明显易懂，下文特举实施例，并配合所附图示，做详细的说明。本发明说明书提供不同的实施例来说明本发明不同实施方式的技术特征。其中，实施例中的各元件的配置为说明的用，并非用以限制本发明。且实施例中图式标号的部分重复，为了简化说明，并非意指不同实施例的间的关联性。
图1为本发明一实施例的半导体封装500的剖示图。在本实施例中，上述半导体封装500可为芯片级封装组件(wafer level package assembly)，其使用介层孔插塞将半导体元件连接至重布线层(redistribution layer，RDL)结构。如图1所示，在本发明一实施例中，半导体封装500包括重布线层结构300、第一半导体芯片310、第二半导体芯片312以及介层孔插塞218a～218c。然而，注意如图1所示的第一半导体芯片310和第二半导体芯片312仅做为实施例，且并未限制用于半导体封装中的半导体芯片的数量。在本发明一实施例中，半导体封装500可包括单一半导体芯片或包括多于两个半导体芯片。并且，为了清楚显示用于半导体芯片的电源焊垫或接地焊垫的介层孔插塞，用于半导体芯片的信号焊垫(signal pad)的电性连接的介层孔插塞在附图(图1、2)中不予显示。
如图1所示，第一半导体芯片310和第二半导体芯片312彼此隔开且通过粘着层(图未示)贴附至载板(图未示)。第一半导体芯片310的背面310a和第二半导体芯片312的背面312a接触上述载板。第一半导体芯片310的顶面310b和第二半导体芯片312的顶面312b可背向远离于上述载板。上述载板可用于提供结构刚性或用于沉积后续非刚性层的基座。
如图1所示，第二半导体芯片312设置于第一半导体芯片310的旁边。在本发明一些其他实施例中，第二半导体芯片312可设置于第一半导体芯片310上。第一半导体芯片310和第二半导体芯片312的电路分别设置接近于其顶面310b和顶面312b。在本发明一些实施例中，焊垫202a～202d和焊垫202g设置于第一半导体芯片310的顶面310b上，以电性连接至第一半导体芯片310的电路。焊垫202e、202f、202h设置于第二半导体芯片312的顶面312b上，以电性连接至第二半导体芯片312的电路。在本发明一实施例中，焊垫202a～202d和焊垫202g属于第一半导体芯片310的内连线结构(interconnection structure)(图未示)的最顶层金属层。类似地，焊垫202e、202f和202h属于第二半导体芯片312的内连线结构(图未示)的最顶层金属层。在本发明一实施例中，焊垫202a～202d和焊垫202g配置于第一半导体芯片310的中间区域内，用以传输第一半导体芯片310的接地信号或电源信号。焊垫202e、202f和202h配置于第二半导体芯片312的中间区域内，用以传输第二半导体芯片312的接地信号或电源信号。因此，焊垫202a～202h可视为接地焊垫或电源焊垫。
如图1所示，成型材料308a，施加于上述载板上，且可围绕第一半导体芯片310和第二半导体芯片312，并填充位于第一半导体芯片310和第二半导体芯片312周围的任何间隙，以形成成型基板308。上述成型基板308也可覆盖第一半导体芯片310的顶面310b和第二半导体芯片312的顶面312b。在本发明一实施例中，成型基板308可由任何非导电材料形成，例如环氧树脂(epoxy)、树脂(resin)、可塑型聚合物(moldable polymer)或类似的材料。成型材料308a可于实质上为液体时施加于上述载板上，之后可通过在例如环氧树脂或树脂中的化学反应将成型材料308a硬化。在本发明一实施例中，成型材料308a可为紫外光硬化型聚合物(ultraviolet cured polymer)或热硬化型聚合物，其于施加于上述载板时为胶状(gel)或为可延展的固体(malleable solid)，以设置围绕第一半导体芯片310和第二半导体芯片312。在成型材料308a为紫外光硬化型聚合物或热硬化型聚合物的实施例中，例如可使用模型来形成成型基板308，上述模型相邻于例如为晶圆或封装的成型基板形成区域的边界。
如图1所示，可通过微影制程，从成型基板308的接近第一半导体芯片310的顶面310b和第二半导体芯片312的顶面312b的表面形成开口212a～212c，开口212a～212c穿过成型基板308的一部分。在本发明一实施例中，开口212a～212c分别相应于焊垫202a～202h形成。更详细来说，开口212a相应于四个焊垫202a～202c、202g形成。开口212b相应于焊垫202d。开口212c相应于三个焊垫202e、202f、202h形成。在本发明一实施例中，开口的面积可设计大于第一半导体芯片310和第二半导体芯片312的任何焊垫的面积。举例来说，开口212a的面积设计大于第一半导体芯片310的焊垫202a～202c的面积。开口212c的面积设计大于第二半导体芯片312的焊垫202e、202f、202h的面积。
如图1所示，介层孔插塞218a～218c分别填充开口212a～212c而形成。因此，介层孔插塞218a～218c可被成型基板308围绕而形成。在本发明一实施例中，介层孔插塞218a～218c可由铜、铝、金、钯、银、前述导电材料的合金或其他导电材料形成。
在本发明一实施例中，介层孔插塞218a设计电性耦接至设置于第一半导体芯片310上的四个焊垫，例如焊垫202a～202c、202g。介层孔插塞218c设计连接至设置于第二半导体芯片312上的三个焊垫，例如焊垫202e、202f、202h。如图1所示，介层孔插塞218b设计接触单一个(single)设置于第一半导体芯片310上的焊垫202d。注意介层孔插塞218b通过重布线层结构300电性连接至介层孔插塞218c。然而，注意如图1所示的设计连接至相同介层孔插塞的焊垫数量仅做为实施例，然其并非用以限定本发明。在本发明一实施例中，介层孔插塞的面积可设计大于第一半导体芯片310和第二半导体芯片312的任何焊垫的面积。举例来说，介层孔插塞218a的面积设计大于第一半导体芯片310的焊垫202a～202c的面积。介层孔插塞218c的面积设计大于第二半导体芯片312的焊垫202e、202f、202h的面积。
注意设计用以连接至相同介层孔插塞的焊垫具有相同的功能。举例来说，指定连接至单一介层孔插塞218a的第一半导体芯片310上的焊垫202a～202c、202g可视为接地焊垫202a～202c、202g。在本发明其他实施例中，指定连接至单一介层孔插塞218a的第一半导体芯片310上的焊垫202a～202c、202g也可视为用以提供相同电压的电源焊垫202a～202c、202g。类似地，指定连接至介层孔插塞218c的第二半导体芯片312的焊垫202e、202f、202h可视为接地焊垫202e、202f、202h或电源焊垫202e、202f、202h。然而，如图1所示的介层孔插塞和导线的间的连接仅做为一实施例，然其并非用以限定本发明。
如图1所示，注意半导体封装500的一些介层孔插塞设计具有绕线功能。因此，位于第一半导体芯片310或第二半导体芯片312上的一些介层孔插塞可设计连接数个具有相同功能的焊垫。举例来说，介层孔插塞可设计连接位于第一半导体芯片310或第二半导体芯片312上邻近的接地焊垫。在本发明其他实施例中，介层孔插塞可设计连接位于第一半导体芯片310或第二半导体芯片312上邻近且用以提供相同电压的电源焊垫。因此，介层孔插塞可视为重布线层图案或传输网络，以连接配置于第一半导体芯片310或第二半导体芯片312的某个区域的相邻的接地焊垫/电源焊垫。在本发明一实施例中，在俯视图中，由介层孔插塞构成的重布线层图案的形状配置具有为网筛形(mesh-shape)或环形。
如图1所示，重布线层结构300设置于成型基板308的接近于焊垫202a～202h的侧面308b上。重布线层结构300可接触成型基板308以及第一半导体芯片310和第二半导体芯片312的焊垫202a～202h。在本发明一实施例中，重布线层结构300可具有一个或多个导线302，设置于金属层间介电层(intermetaldielectric layer)304中。导线302分别电性连接至重布线接触焊垫305a～305d。然而，注意设计连接至如图1所示的相同介层孔插塞的导线302、金属层间介电层304及重布线接触焊垫305a～305d的数量仅做为实施例，并非用以限定本发明。在本发明一实施例中，半导体封装500使用介层孔插塞218a～218c分别将第一半导体芯片310和第二半导体芯片312的接地焊垫和电源焊垫(例如焊垫202a～202h)连接至重布线层结构300的导线302(用于半导体芯片的信号焊垫的介层孔插塞并未显示于图1中)。导线302可设计为从介层孔插塞218a～218c中的一个或多个扇出(fan out)，且提供第一半导体芯片310和第二半导体芯片312的焊垫202a～202h以及重布线接触焊垫305a～305d之间的电性连接物。因此，相较于第一半导体芯片310和第二半导体芯片312的焊垫202a～202h的焊垫间距，重布线接触焊垫305a～305d可以具有较大的焊垫间距，而可适用于球栅阵列(ball grid array)或其他封装粘着***(package mounting system)。在本发明一实施例中，重布线层结构300可具有将一个或多个介层孔插塞218a～218c连接至重布线接触焊垫305a～305d的导线302。举例来说，其中一个导线302可将第一半导体芯片310的介层孔插塞218b和第二半导体芯片312的介层孔插塞218c电性连接至重布线接触焊垫305c和305d。举例来说，其中一个导线302可将介层孔插塞218a电性连接至重布线接触焊垫305a和305b。
如图1所示，封装粘着物306a～306d可分别设置于重布线接触焊垫305a～305d上，而后可测试第一半导体芯片310和第二半导体芯片312。封装粘着物306a～306d可设置于重布线层结构300的远离于第一半导体芯片310和第二半导体芯片312的表面303上。封装粘着物306a～306d分别耦接至导线302。在本发明一实施例中，例如为封装粘着物306a～306d可配置为包括球栅阵列(ballgrid array，BGA)的焊球。在本发明一其他实施例中，封装粘着物306a～306d可为平面网格阵列(land grid array，LGA)、插针网格阵列(pin grid array，PGA)或其他适当的封装粘着***。
图2为本发明一实施例的半导体封装500的第一半导体芯片310的俯视图。图2也显示本发明一实施例的半导体封装500的第一半导体芯片310的介层孔插塞218-P和218-G的布局。注意为了清楚显示用于第一半导体芯片310的电源和接地焊垫(例如焊垫210a～210d)的介层孔插塞218-P和218-G，用于第一半导体芯片310的信号焊垫(signal pad)的介层孔插塞在图2中不予显示。注意第二半导体芯片312的介层孔插塞218c的布局可类似于第一半导体芯片310的介层孔插塞218-P和218-G的布局。
在如图2所示的一实施例中，介层孔插塞218-P设计做为用于第一半导体芯片310的电源焊垫的重布线绕线。在本发明一实施例中，介层孔插塞218-G设计做为用于第一半导体芯片310的接地焊垫的重布线绕线。如图2所示，在本发明一实施例中，第一半导体芯片310的介层孔插塞218-P和218-G设计设置于接近第一半导体芯片310的中间区域以连接第一半导体芯片310的相应的电源焊垫或接地焊垫。在本发明其他实施例中，第一半导体芯片310的介层孔插塞218-P和218-G设计配置于周边区域(例如如图2所示的围绕介层孔插塞218-P和218-G的区域)，且相应于电源焊垫或接地焊垫的配置。
在如图2所示的一实施例中，第一半导体芯片310的介层孔插塞218-P和218-G设计连接至数个具有相同功能的焊垫。举例来说，介层孔插塞218-G可设计连接至第一半导体芯片310的相邻的接地焊垫。在本发明的其他实施例中，介层孔插塞218-P可设计连接至第一半导体芯片310的相邻的电源焊垫，用以提供相同的电压。因此，介层孔插塞218-P/218-G可设计做为电源/接地传输网络，其用以连接至配置于第一半导体芯片310的中间区域的相邻的电源/接地焊垫。如图2所示，在本发明一实施例中，配置为第一半导体芯片310的电源/接地传输网络的介层孔插塞218-P和218-G可具有网筛形或环形。注意在俯视图中，第二半导体芯片312的介层孔插塞218c的形状可类似于如图2所示的第一半导体芯片310的介层孔插塞218-P和218-G。
在如图2所示的一实施例中，介层孔插塞218-P可配置为电源传输网络，以进一步扩大用于第一半导体芯片310的电源焊垫的绕线面积。当电源信号从第一半导体芯片310至重布线层结构300或至第二半导体芯片312(如图1所示)时，介层孔插塞218-P可改善电源信号的信号完整性。注意当如图1所示的介层孔插塞218c设计连接至第二半导体芯片312的电源焊垫时，介层孔插塞218c也可改善电源信号的信号完整性。
在如图2所示的一些实施例中，介层孔插塞218-G可配置为接地传输网络，以进一步扩大用于第一半导体芯片310的接地焊垫的绕线面积。由介层孔插塞218-G构成的扩大接地传输网络可提升对介层孔插塞218-P的屏蔽能力。注意当如图1所示的介层孔插塞218c设计连接至第二半导体芯片312的接地焊垫时，介层孔插塞218c也可提升对用于连接电源焊垫的其他介层孔插塞的屏蔽能力。
本发明的实施例提供一种半导体封装。上述半导体封装使用介层孔插塞，每一个介层孔插塞设计将半导体芯片的多个电源焊垫或接地焊垫连接至重布线层结构。在本发明一实施例中，上述介层孔插塞可视为重布线层图案或传输网络，其用以连接至配置于半导体芯片的中间区域的相邻的电源/接地焊垫。在本发明一实施例中，上述介层孔插塞可配置为半导体芯片的重布线网络，且在俯视图中的形状为网筛形或环形。在本发明一实施例中，当电源信号从半导体芯片至重布线层结构300或至另一半导体芯片时，配置为电源重布线网络图案/传输网络的介层孔插塞可改善电源信号的信号完整性。在本发明一实施例中，配置为接地重布线网络图案/传输网络的介层孔插塞可提升对用于连接电源焊垫的其他介层孔插塞的屏蔽能力。
以上所述仅为本发明的较佳实施方式，凡依本发明权利要求所做的均等变化和修饰，均应属本发明的涵盖范围。

Claims (25)

1.一种半导体封装，其特征在于，包括：
第一半导体芯片，其上具有多个焊垫；以及
第一介层孔插塞和第二介层孔插塞，分别设置于所述第一半导体芯片上，其中所述第一介层孔插塞连接至所述第一半导体芯片的所述多个焊垫中的至少两个。
2.如权利要求1所述的半导体封装，其特征在于，所述第二介层孔插塞连接至所述第一半导体芯片的所述多个焊垫的其中一个。
3.如权利要求1所述的半导体封装，其特征在于，所述第一介层孔插塞的俯视形状为网筛形或环形。
4.如权利要求1所述的半导体封装，其特征在于，所述第一介层孔插塞的面积大于所述第二介层孔插塞的面积。
5.如权利要求1所述的半导体封装，其特征在于，所述多个焊垫的所述至少两个为电源焊垫或接地焊垫。
6.如权利要求1所述的半导体封装，其特征在于，所述第一介层孔插塞的面积大于所述多个焊垫中任一个的面积。
7.如权利要求1所述的半导体封装，其特征在于，还包括：
重布线层结构，其上具有第一导线和第二导线，其中所述第一介层孔插塞和所述第二介层孔插塞分别接触所述第一导线和所述第二导线。
8.如权利要求1所述的半导体封装，其特征在于，还包括：
成型材料，围绕所述第一半导体芯片，且接触所述重布线层结构和所述第一半导体芯片；以及
第一封装粘着物和第二封装粘着物，设置于所述重布线层结构的远离于所述第一半导体芯片的表面上，其中所述第一封装粘着物和所述第二封装粘着物分别耦接至所述第一导线和所述第二导线。
9.如权利要求1所述的半导体封装，其特征在于，还包括：
第二半导体芯片，设置于所述第一半导体芯片旁或设置于所述第一半导体芯片上。
10.一种半导体封装，其特征在于，包括：
第一半导体芯片，其上具有第一焊垫和第二焊垫，其中所述第一焊垫和所述第二焊垫均为电源焊垫或接地焊垫；以及
第一介层孔插塞，设置于所述第一半导体芯片上，其中所述第一介层孔插塞连接至所述第一焊垫和所述第二焊垫。
11.如权利要求10所述的半导体封装，其特征在于，还包括：
第二介层孔插塞，设置于所述第一半导体芯片上，其中所述第二介层孔插塞仅连接至所述第一半导体芯片的第三焊垫。
12.如权利要求10所述的半导体封装，其特征在于，所述第一介层孔插塞的俯视形状为网筛形或环形。
13.如权利要求11所述的半导体封装，其特征在于，所述第一介层孔插塞的面积大于所述第一焊垫和所述第二焊垫中任一个的面积。
14.如权利要求11所述的半导体封装，其特征在于，所述第一介层孔插塞的面积大于所述第二介层孔插塞的面积。
15.如权利要求10所述的半导体封装，其特征在于，还包括：
重布线层结构，其上具有第一导线和第二导线，其中所述第一介层孔插塞和所述第二介层孔插塞分别接触所述第一导线和所述第二导线。
16.如权利要求10所述的半导体封装，其特征在于，还包括：
成型材料，围绕所述第一半导体芯片，且接触所述重布线层结构和所述第一半导体芯片；以及
第一封装粘着物和第二封装粘着物，设置于所述重布线层结构的远离于所述第一半导体芯片的表面上，其中所述第一封装粘着物和所述第二封装粘着物分别耦接至所述第一导线和所述第二导线。
17.如权利要求10所述的半导体封装，其特征在于，还包括：
第二半导体芯片，设置于所述第一半导体芯片旁或设置于所述第一半导体芯片上。
18.一种半导体封装，其特征在于，包括：
第一半导体芯片，其上具有多个焊垫；以及
第一介层孔插塞，设置于所述第一半导体芯片上，其中所述第一介层孔插塞连接至所述第一半导体芯片的所述多个焊垫，所述第一介层孔插塞的俯视形状为网筛形或环形。
19.如权利要求18所述的半导体封装，其特征在于，还包括：
第二介层孔插塞，设置于所述第一半导体芯片上，其中所述第二介层孔插塞仅连接至所述第一半导体芯片的额外的焊垫。
20.如权利要求19所述的半导体封装，其特征在于，所述多个焊垫为电源焊垫或接地焊垫。
21.如权利要求19所述的半导体封装，其特征在于，所述第一介层孔插塞的面积大于所述多个焊垫中任一个的面积。
22.如权利要求19所述的半导体封装，其特征在于，所述第一介层孔插塞的面积大于所述第二介层孔插塞的面积。
23.如权利要求19所述的半导体封装，其特征在于，还包括：
重布线层结构，其上具有第一导线和第二导线，其中所述第一介层孔插塞和所述第二介层孔插塞分别接触所述第一导线和所述第二导线。
24.如权利要求23所述的半导体封装，其特征在于，还包括：
成型材料，围绕所述第一半导体芯片，且接触所述重布线层结构和所述第一半导体芯片；以及
第一封装粘着物和第二封装粘着物，设置于所述重布线层结构的远离于所述第一半导体芯片的表面上，其中所述第一封装粘着物和所述第二封装粘着物分别耦接至所述第一导线和所述第二导线。
25.如权利要求18所述的半导体封装，其特征在于，还包括：
第二半导体芯片，设置于所述第一半导体芯片旁或设置于所述第一半导体芯片上。
CN201410784429.4A 2014-01-22 2014-12-17 半导体封装 Pending CN104795382A (zh)

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106061118A (zh) * 2016-06-28 2016-10-26 广东欧珀移动通信有限公司 移动终端中印刷电路板pcb的开孔方法和开孔装置
CN106373953A (zh) * 2016-09-23 2017-02-01 湖北三江航天红峰控制有限公司 一种模拟舵机控制装置
CN106449611A (zh) * 2015-08-11 2017-02-22 艾马克科技公司 半导体装置
CN106601702A (zh) * 2017-01-23 2017-04-26 合肥雷诚微电子有限责任公司 无基板高散热性的多芯片线性功率放大器结构及其制作方法
CN108010898A (zh) * 2017-11-02 2018-05-08 上海玮舟微电子科技有限公司 一种芯片封装结构
WO2019096093A1 (en) * 2017-11-16 2019-05-23 Huawei Technologies Co., Ltd. Semiconductor package having reduced internal power pad pitch
CN111785700A (zh) * 2020-09-07 2020-10-16 成都知融科技股份有限公司 一种超宽带互连结构
US11652038B2 (en) 2013-11-19 2023-05-16 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor package with front side and back side redistribution structures and fabricating method thereof

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9653406B2 (en) 2015-04-16 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive traces in semiconductor devices and methods of forming same
US9761571B2 (en) * 2015-09-17 2017-09-12 Deca Technologies Inc. Thermally enhanced fully molded fan-out module
CN105161468A (zh) * 2015-10-10 2015-12-16 中国电子科技集团公司第三十八研究所 一种射频芯片及其无源器件的封装结构和封装方法
US9748184B2 (en) * 2015-10-15 2017-08-29 Micron Technology, Inc. Wafer level package with TSV-less interposer
US10679949B2 (en) * 2016-03-11 2020-06-09 Mediatek Inc. Semiconductor package assembly with redistribution layer (RDL) trace
TWI611530B (zh) * 2016-10-14 2018-01-11 鈺橋半導體股份有限公司 具有散熱座之散熱增益型面朝面半導體組體及製作方法
US10163813B2 (en) * 2016-11-17 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure including redistribution structure and conductive shielding film
KR102639101B1 (ko) * 2017-02-24 2024-02-22 에스케이하이닉스 주식회사 전자기간섭 차폐 구조를 갖는 반도체 패키지
US11610855B2 (en) * 2017-11-29 2023-03-21 Pep Innovation Pte. Ltd. Chip packaging method and package structure
US11233028B2 (en) 2017-11-29 2022-01-25 Pep Inovation Pte. Ltd. Chip packaging method and chip structure
US11232957B2 (en) * 2017-11-29 2022-01-25 Pep Inovation Pte. Ltd. Chip packaging method and package structure
US11114315B2 (en) 2017-11-29 2021-09-07 Pep Innovation Pte. Ltd. Chip packaging method and package structure
US10756038B1 (en) * 2019-02-21 2020-08-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US11621236B2 (en) * 2019-12-27 2023-04-04 Intel Corporation Electrostatic discharge protection in integrated circuits using positive temperature coefficient material
US11309246B2 (en) 2020-02-05 2022-04-19 Apple Inc. High density 3D interconnect configuration

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030209797A1 (en) * 2002-05-08 2003-11-13 Anwar Ali Direct alignment of contacts
US20060157847A1 (en) * 2005-01-19 2006-07-20 Chi-Hsing Hsu Chip package
US20080111242A1 (en) * 2006-09-29 2008-05-15 Megica Corporation Integrated circuit chips with fine-line metal and over-passivation metal
CN102439719A (zh) * 2009-05-14 2012-05-02 米辑电子股份有限公司 ***级封装

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3057975B2 (ja) * 1993-09-27 2000-07-04 日本電気株式会社 集積回路の配線
US6351040B1 (en) * 1998-01-22 2002-02-26 Micron Technology, Inc. Method and apparatus for implementing selected functionality on an integrated circuit device
US6281108B1 (en) * 1999-10-15 2001-08-28 Silicon Graphics, Inc. System and method to provide power to a sea of gates standard cell block from an overhead bump grid
US6912778B2 (en) * 2001-07-19 2005-07-05 Micron Technology, Inc. Methods of fabricating full-wafer silicon probe cards for burn-in and testing of semiconductor devices
JP3860000B2 (ja) * 2001-09-07 2006-12-20 Ｎｅｃエレクトロニクス株式会社 半導体装置およびその製造方法
SG107567A1 (en) * 2001-11-07 2004-12-29 Advanced Systems Automation Method and apparatus for forming a flip chip semiconductor package and method for producing a substrate for the flip chip semiconductor package
TW517361B (en) * 2001-12-31 2003-01-11 Megic Corp Chip package structure and its manufacture process
US6730540B2 (en) * 2002-04-18 2004-05-04 Tru-Si Technologies, Inc. Clock distribution networks and conductive lines in semiconductor integrated circuits
JP3580803B2 (ja) * 2002-08-09 2004-10-27 沖電気工業株式会社 半導体装置
US7321167B2 (en) * 2003-06-04 2008-01-22 Intel Corporation Flex tape architecture for integrated circuit signal ingress/egress
EP1519411A3 (en) * 2003-09-26 2010-01-13 Panasonic Corporation Semiconductor device and method for fabricating the same
US8853001B2 (en) * 2003-11-08 2014-10-07 Stats Chippac, Ltd. Semiconductor device and method of forming pad layout for flipchip semiconductor die
US7042077B2 (en) * 2004-04-15 2006-05-09 Intel Corporation Integrated circuit package with low modulus layer and capacitor/interposer
US7465654B2 (en) * 2004-07-09 2008-12-16 Megica Corporation Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures
US8022544B2 (en) * 2004-07-09 2011-09-20 Megica Corporation Chip structure
US7271479B2 (en) * 2004-11-03 2007-09-18 Broadcom Corporation Flip chip package including a non-planar heat spreader and method of making the same
JP2007184449A (ja) * 2006-01-10 2007-07-19 Renesas Technology Corp 半導体装置及びその製造方法
TWI298532B (en) * 2006-04-14 2008-07-01 Silicon Integrated Sys Corp Conductive structure for electronic device
US7514684B2 (en) * 2006-08-28 2009-04-07 L-3 Communications Corporation Surface mounted infrared image detector systems and associated methods
US7842542B2 (en) * 2008-07-14 2010-11-30 Stats Chippac, Ltd. Embedded semiconductor die package and method of making the same using metal frame carrier
JP5147677B2 (ja) * 2008-12-24 2013-02-20 新光電気工業株式会社 樹脂封止パッケージの製造方法
DE102010045649A1 (de) * 2010-09-17 2012-03-22 Texas Instruments Deutschland Gmbh Elektronische Vorrichtung und Verfahren zum direkten Montieren passiver Komponenten
US8709933B2 (en) * 2011-04-21 2014-04-29 Tessera, Inc. Interposer having molded low CTE dielectric
US8946888B2 (en) * 2011-09-30 2015-02-03 Taiwan Semiconductor Manufacturing Company, Ltd. Package on packaging structure and methods of making same
JP5729290B2 (ja) * 2011-12-16 2015-06-03 富士通株式会社 半導体装置の製造方法、電子装置の製造方法及び基板
US8742597B2 (en) * 2012-06-29 2014-06-03 Intel Corporation Package substrates with multiple dice
US20140133105A1 (en) * 2012-11-09 2014-05-15 Nvidia Corporation Method of embedding cpu/gpu/logic chip into a substrate of a package-on-package structure
US9478474B2 (en) * 2012-12-28 2016-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for forming package-on-packages
US9070644B2 (en) * 2013-03-15 2015-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging mechanisms for dies with different sizes of connectors

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030209797A1 (en) * 2002-05-08 2003-11-13 Anwar Ali Direct alignment of contacts
US20060157847A1 (en) * 2005-01-19 2006-07-20 Chi-Hsing Hsu Chip package
US20080111242A1 (en) * 2006-09-29 2008-05-15 Megica Corporation Integrated circuit chips with fine-line metal and over-passivation metal
CN102439719A (zh) * 2009-05-14 2012-05-02 米辑电子股份有限公司 ***级封装

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11652038B2 (en) 2013-11-19 2023-05-16 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor package with front side and back side redistribution structures and fabricating method thereof
CN106449611A (zh) * 2015-08-11 2017-02-22 艾马克科技公司 半导体装置
CN106449611B (zh) * 2015-08-11 2022-10-04 艾马克科技公司 半导体装置
CN106061118A (zh) * 2016-06-28 2016-10-26 广东欧珀移动通信有限公司 移动终端中印刷电路板pcb的开孔方法和开孔装置
CN106061118B (zh) * 2016-06-28 2018-09-11 广东欧珀移动通信有限公司 移动终端中印刷电路板pcb的开孔方法和开孔装置
CN106373953A (zh) * 2016-09-23 2017-02-01 湖北三江航天红峰控制有限公司 一种模拟舵机控制装置
CN106601702A (zh) * 2017-01-23 2017-04-26 合肥雷诚微电子有限责任公司 无基板高散热性的多芯片线性功率放大器结构及其制作方法
CN108010898A (zh) * 2017-11-02 2018-05-08 上海玮舟微电子科技有限公司 一种芯片封装结构
WO2019096093A1 (en) * 2017-11-16 2019-05-23 Huawei Technologies Co., Ltd. Semiconductor package having reduced internal power pad pitch
US10304792B1 (en) 2017-11-16 2019-05-28 Futurewei Technologies, Inc. Semiconductor package having reduced internal power pad pitch
US10672730B2 (en) 2017-11-16 2020-06-02 Futurewei Technologies, Inc. Semiconductor package having reduced internal power pad pitch
CN111785700A (zh) * 2020-09-07 2020-10-16 成都知融科技股份有限公司 一种超宽带互连结构

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