CN104779929B - Suitable for the low-power consumption level Four operational amplifier of LCD drive circuits - Google Patents
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Abstract
The present invention relates to large scale integrated circuit, to provide a kind of level Four operational amplifier applied to low-voltage and low-power dissipation.The level Four operation amplifier circuit can realize driving heavy load electric capacity (hundreds of pF) under the conditions of low power consumption (μ W), and with lower power consumption and more preferable slew rate.Therefore, the present invention is adopted the technical scheme that, it is adaptable to the low-power consumption level Four operational amplifier of LCD drive circuits, it is made up of four gain amplification stages, two-way feed-forward loop level and an active feedback loop level；Four gain amplification stages are respectively：Transadmittance gain input stage, the second to the 3rd high-gain stage, the 4th push-pull output stage；Two feed-forward loops level is respectively：Forward transconductance gain stage and negative sense transadmittance gain level；One active feedback loop level is made up of electric capacity and forward transconductance gain stage.Present invention is mainly applied to manufacturing and designing for large scale integrated circuit.
Description
Technical field
The present invention relates to large scale integrated circuit, low voltage and low power circuits, low pressure difference linear voltage regulator (LDO), multistage fortune
Calculate amplifier.Specifically, it is related to the low-power consumption level Four operational amplifier suitable for LCD drive circuits.
Background technology
The technical research of low-voltage and low-power dissipation multi-stage operational amplifier is the very active research neck of low-power consumption analog circuit all the time
Domain.The compensation technique of many multi-stage operational amplifiers can be widely applied to portable electric appts, for example：Battery of mobile phone and
In the equipment such as Notebook Battery, LDO, LCD.Due to Multilevel compensating method-nested type Miller of famous three-stage operational amplifier
The inherent limitations of compensation technique (NMC), i.e.,：There is Right-half-plant zero and two large compensation electric capacity in the compensation technique；In recent years
The product of low-voltage and low-power dissipation is caused to move towards small-sized, Highgrade integration come the demand drastically expanded due to market, this is just
Show that NMC weak point needs to improve.Because it significantly limit it in low-voltage and low-power dissipation multi-stage operational amplifier circuit
Application.The nearest more than ten years have emerged many on the compensation method of multi-stage operational amplifier to improve NMC technologies.In low work(
Consume under conditions of heavy load electric capacity, they can be greatly enhanced the stability of amplifier, while also having expanded the gain of amplifier
Bandwidth product and Slew Rate.But above compensation technique is there is also some shortcomings, for example：When driving heavy load electric capacity, some are compensated
Electric capacity causes chip area to increase because direct proportion is in load capacitance, and the manufacturing cost of final circuit is also improved；After institute
The compensation technique come starts the area direct proportion by compensating electric capacity in the geometric mean of load capacitance, thus greatlys save
The area of chip.
The content of the invention
To overcome the deficiencies in the prior art, there is provided a kind of level Four operational amplifier applied to low-voltage and low-power dissipation.The level Four
Operation amplifier circuit can realize driving heavy load electric capacity (hundreds of pF) under the conditions of low power consumption (μ W), and with lower
Power consumption and more preferable slew rate.Therefore, the present invention is adopted the technical scheme that, it is adaptable to the low-power consumption level Four of LCD drive circuits
Operational amplifier, is made up of four gain amplification stages, two-way feed-forward loop level and an active feedback loop level；Four gains are put
Big level is respectively：Transadmittance gain input stage, the second to the 3rd high-gain stage, the 4th push-pull output stage；Two feed-forward loop fractions
It is not：Forward transconductance gain stage and negative sense transadmittance gain level；One active feedback loop level is by electric capacity and forward transconductance gain stage
Composition；The signal of input passes through transadmittance gain input stage gm1, the second to the 3rd gain stage, eventually passes the 4th push-pull output stage
It is output to VOUT；The signal of input reaches the output end of the 3rd gain stage by forward transconductance gain stage simultaneously；In the second gain
Level output end signal is divided into two-way：The output end of the 4th push-pull output stage, Ling Yilu are reached by negative sense transadmittance gain level all the way
It is directly entered the 3rd gain stage；Increased in the signal of amplifier out by active feedback loop level by electric capacity Ca and forward transconductance
Beneficial level reaches input；
Amplifier concrete structure is：By the first to the 15th PMOS transistor M10, M11, M12, M17, M18, M20, M23,
M30, M33, M41, M411, M412, M50, M51, M52 and the first to the tenth bi-NMOS transistor M13, M14, M15, M16,
Totally 27 MOS transistors, an electric capacity are that compensating electric capacity Ca is constituted by M21, M22, M31, M32, M40, M413, M53, M54；Its
In：
Firstth, the 4th to the 15th PMOS transistor M10, M17, M18, M20, M23, M30, M33, M41, M411, M412,
M50 source electrode meets power supply VDD jointly；Except second, third, the 14th to the 15th PMOS transistor M11, M12, M51,
M52 substrate termination source electrode beyond, the first, the 4th to the 13rd PMOS transistor M10, M17, M18, M20, M23, M30, M33,
M41, M411, M412, M50 substrate termination power supply VDD；First, secondth, the 5th to the tenth bi-NMOS transistor M13,
M14, M21, M22, M31, M32, M40, M413, M53, M54 source electrode common ground GND；First to the 12nd M13, M14,
M15, M16, M21, M22, M31, M32, M40, M413, M53, M54 substrate terminal ground connection GND；
First PMOS transistor M10 grid meets the first bias voltage Vb1, drain electrode and connects the second to the 3rd PMOS transistor
M11, M12 source electrode；The grid of the first to the second PMOS transistor M11, M12 connects input voltage vin-and Vin+ ends respectively；The
One PMOS transistor M11, the first nmos pass transistor M13 drain electrode connect the 3rd nmos pass transistor M15 source electrode, the 3rd PMOS jointly
Transistor M12, the second nmos pass transistor M14 drain electrode connect M16 source electrode jointly；The first to the second nmos pass transistor M13, M14
Grid meet the second bias voltage Vb2 jointly, the 3rd to the 4th nmos pass transistor M15, M16 grid connects the 3rd biased electrical jointly
Press Vb3；6th PMOS transistor M20 grid connects the 4th nmos pass transistor M16, the 5th PMOS transistor M18 drain electrode；4th
Grid to the 5th PMOS transistor M17, M18 connects the 4th PMOS transistor M17, the 3rd nmos pass transistor M15 drain electrode jointly；
4th nmos pass transistor M16 source electrode connects compensating electric capacity Ca left end, and compensating electric capacity Ca right-hand member meets output end VOUT；
5th nmos pass transistor M21, the 6th nmos pass transistor M22 grid meet the 6th PMOS transistor M20, the 5th jointly
Nmos pass transistor M21 drain electrode；It is brilliant that 7th PMOS transistor M23, the 6th nmos pass transistor M22 drain electrode meet the 8th PMOS jointly
Body pipe M30 grid；7th PMOS transistor M23 grid meets the 4th bias voltage Vb4；7th nmos pass transistor M31, the 8th
Nmos pass transistor M32 grid connects the 8th PMOS transistor M30, the 7th nmos pass transistor M31 drain electrode jointly；9th PMOS is brilliant
Body pipe M33, the 8th nmos pass transistor M32 drain electrode connect the 9th PMOS transistor M40 grid jointly；9th PMOS transistor
M33 grid meets the 5th bias voltage Vb5；
9th nmos pass transistor M40, the tenth PMOS transistor M41 drain electrode, the 11st PMOS transistor M411 drain electrode
Output end VOUT is met jointly；Tenth nmos pass transistor M413, the 12nd PMOS transistor M412 drain electrode connect the 11st jointly
PMOS transistor M411 grid；Tenth nmos pass transistor M413 grid meets the second bias voltage Vb2；12nd PMOS crystal
Pipe M412 grid meets the 6th bias voltage Vb6；
13rd PMOS transistor M50 grid meets the 6th bias voltage Vb6, drain electrode and connects the 14th to the 15th PMOS crystalline substances
Body pipe M51, M52 source electrode；The grid of 14th to the 15th PMOS transistor M51, M52 connect respectively input voltage vin-and
Vin+ ends；11st to the tenth bi-NMOS transistor M53, M54 grid connects the 11st nmos pass transistor M53, the 14th jointly
PMOS transistor M51 drain electrode；Tenth bi-NMOS transistor M54, the 15th PMOS transistor M52 drain electrode connect the 7th jointly
Nmos pass transistor M31 grid；External load capacitance CL meets VOUT.
The first transadmittance gain input stage gm1 is constituted by two mirrored transistors M11, M12, forward direction is constituted by M16 transistors
Transadmittance gain level gma；Transistor M20, M30 are the second to the 3rd gain stage gm2, gm3 respectively；Transistor M40, M41 composition the
Four push-pull output stage gm4；M41 is negative sense transadmittance gain level gmf2；Three transistor M411-M413 constitute SR booster stages；Two
Mirrored transistor M51-M52 composition forward transconductance gain stages gmf1.
Compared with the prior art, technical characterstic of the invention and effect：
Due to using four gain amplification stages, two-way feed-forward loop level and an active feedback loop level structure, thus,
Under the conditions of low-voltage and low-power dissipation (μ W), the operational amplifier that the present invention is provided can drive heavy load electric capacity (hundreds of pF), have simultaneously
There is low power consumption and more preferable Slew Rate.
Brief description of the drawings
The topological diagram of Fig. 1 level Four operational amplifiers.
The embodiment schematic diagram of Fig. 2 level Four operational amplifiers.In figure, 1stage is differential input stage, 2stage,
3stage is gain stage, and 4stage is push-pull output stage, and SREstage is slew rate booster stage, and feedback stage are feedforward
Level.
Embodiment
In order to overcome the deficiencies in the prior art part, the present invention proposes a kind of for driving the low pressure of heavy load electric capacity low
Power consumption level Four operational amplifier, proposes the active feedforward of two-way and Cascode Miller frequency acquisition and trackings.The technology passes through double
The active feedforward in road is connected to the second level and the output end of the fourth stage introduces zero point and forms Pole-Zero Doublets, is changed with this
The big signal and small-signal performance --- gain bandwidth product and transient response of kind operational amplifier, while also introducing slew rate enhancing
Level improves the slew rate SR under low-power consumption, strives under the conditions of low-power consumption, obtains more preferable gain bandwidth product and more preferably
Transient response.
The present invention proposes a kind of low-voltage and low-power dissipation level Four operational amplifier for being used to drive heavy load electric capacity, and described puts
Big device is made up of four gain amplification stages, two-way feed-forward loop level and an active feedback loop level.Four gain amplification stages point
It is not：Transadmittance gain input stage gm1, the second to the 3rd high-gain stage gm2, gm3, the 4th push-pull output stage gm4.It is fed back to before two
Road grade is respectively：Forward transconductance gain stage gmf1 and negative sense transadmittance gain level gmf2.One active feedback loop level is by electric capacity Ca
With forward transconductance gain stage gma compositions.
Specific implementing circuit schematic diagram is as follows：Described amplifier by the first to the 15th PMOS transistor M10, M11,
M12, M17, M18, M20, M23, M30, M33, M41, M411, M412, M50, M51, M52 and the first to the 12nd NMOS crystal
Totally 27 MOS transistors, an electric capacity are by pipe M13, M14, M15, M16, M21, M22, M31, M32, M40, M413, M53, M54
Compensating electric capacity Ca is constituted；Wherein：
Firstth, the 4th to the 15th PMOS transistor M10, M17, M18, M20, M23, M30, M33, M41, M411, M412,
M50 source electrode meets power supply VDD jointly；Except second, third, the 14th to the 15th PMOS transistor M11, M12, M51,
M52 substrate termination source electrode beyond, the first, the 4th to the 13rd PMOS transistor M10, M17, M18, M20, M23, M30, M33,
M41, M411, M412, M50 substrate termination power supply VDD；First, secondth, the 5th to the tenth bi-NMOS transistor M13,
M14, M21, M22, M31, M32, M40, M413, M53, M54 source electrode common ground GND；First to the 12nd M13, M14,
M15, M16, M21, M22, M31, M32, M40, M413, M53, M54 substrate terminal ground connection GND.
First PMOS transistor M10 grid meets the first bias voltage Vb1, drain electrode and connects the second to the 3rd PMOS transistor
M11, M12 source electrode；The grid of the first to the second PMOS transistor M11, M12 connects input voltage vin-and Vin+ ends respectively；The
One PMOS transistor M11, the first nmos pass transistor M13 drain electrode connect the 3rd nmos pass transistor M15 source electrode, the 3rd PMOS jointly
Transistor M12, the second nmos pass transistor M14 drain electrode connect M16 source electrode jointly；The first to the second nmos pass transistor M13, M14
Grid meet the second bias voltage Vb2 jointly, the 3rd to the 4th nmos pass transistor M15, M16 grid connects the 3rd biased electrical jointly
Press Vb3；6th PMOS transistor M20 grid connects the 4th nmos pass transistor M16, the 5th PMOS transistor M18 drain electrode；4th
Grid to the 5th PMOS transistor M17, M18 connects the 4th PMOS transistor M17, the 3rd nmos pass transistor M15 drain electrode jointly；
4th nmos pass transistor M16 source electrode connects compensating electric capacity Ca left end, and compensating electric capacity Ca right-hand member meets output end VOUT.
5th nmos pass transistor M21, the 6th nmos pass transistor M22 grid meet the 6th PMOS transistor M20, the 5th jointly
Nmos pass transistor M21 drain electrode；It is brilliant that 7th PMOS transistor M23, the 6th nmos pass transistor M22 drain electrode meet the 8th PMOS jointly
Body pipe M30 grid；7th PMOS transistor M23 grid meets the 4th bias voltage Vb4；7th nmos pass transistor M31, the 8th
Nmos pass transistor M32 grid connects the 8th PMOS transistor M30, the 7th nmos pass transistor M31 drain electrode jointly；9th PMOS is brilliant
Body pipe M33, the 8th nmos pass transistor M32 drain electrode connect the 9th PMOS transistor M40 grid jointly；9th PMOS transistor
M33 grid meets the 5th bias voltage Vb5.
9th nmos pass transistor M40, the tenth PMOS transistor M41 drain electrode, the 11st PMOS transistor M411 drain electrode
Output end VOUT is met jointly；Tenth nmos pass transistor M413, the 12nd PMOS transistor M412 drain electrode connect the 11st jointly
PMOS transistor M411 grid；Tenth nmos pass transistor M413 grid meets the second bias voltage Vb2；12nd PMOS crystal
Pipe M412 grid meets the 6th bias voltage Vb6.
13rd PMOS transistor M50 grid meets the 6th bias voltage Vb6, drain electrode and connects the 14th to the 15th PMOS crystalline substances
Body pipe M51, M52 source electrode；The grid of 14th to the 15th PMOS transistor M51, M52 connect respectively input voltage vin-and
Vin+ ends；11st to the tenth bi-NMOS transistor M53, M54 grid connects the 11st nmos pass transistor M53, the 14th jointly
PMOS transistor M51 drain electrode；Tenth bi-NMOS transistor M54, the 15th PMOS transistor M52 drain electrode connect the 7th jointly
Nmos pass transistor M31 grid；External load capacitance CL meets VOUT.
Wherein, the first transadmittance gain input stage gm1 mainly is constituted by two mirrored transistors M11, M12, by M16 transistors
Constitute forward transconductance gain stage gma；Transistor M20, M30 are the second to the 3rd gain stage gm2, gm3 respectively；Transistor M40,
M41 constitutes the 4th push-pull output stage gm4；M41 is negative sense transadmittance gain level gmf2；Three transistor M411-M413 compositions SR increase
Intensity level；Two mirrored transistor M51-M52 composition forward transconductance gain stages gmf1.
Under the conditions of low-voltage and low-power dissipation (μ W), the level Four operational amplifier can drive heavy load electric capacity (hundreds of pF), together
When there is low power consumption and more preferable Slew Rate.To verify its effect, it is 500pF that we, which are set in heavy load electric capacity, by handing over
Stream emulation and Transient draw its open-loop frequency response and transient response, parameter and the result such as form 1 of emulation and the institute of form 2
Show.
Here is that Hspice emulators are used under SMIC 65nm CMOS technologies, during driving CL=500pF load capacitances
Transactional analysis and transient analysis simulation parameter.Therefrom it can be seen that：Gain bandwidth product GBW=2.86MHz, phase margin PM=
53.2 °, average Slew Rate SR=0.40V/ μ s, power consumption is 35 μ W.Compensating electric capacity Ca is reduced in addition, that is, reduces chip
Area, is highly beneficial for this in the circuit application of low-voltage and low-power dissipation.Therefore this money level Four operational amplifier is applied to low
Force down the high-speed applications field of power consumption.
The parameter@CL=500pF that form 1 is emulated
Form 2, the result@CL=500pF of emulation
| Parameter | This work |
| Gain(dB) | 101 |
| PM(deg.) | 53.2 |
| GBW(MHz) | 2.86 |
| SR+/-(V/μs) | 0.34/0.46 |
| Power(mW) | 0.035 |
| Supply(V) | 1.2 |
| CL(pF) | 500 |
*Typical value@TT Corner,25℃
The second to the 3rd PMOS transistor M11, M12 is chosen as signal input part, input respectively difference mode signal Vin- and
Vin+, by the first differential input stage, the second to the 3rd gain stage, eventually passes the 4th push-pull output stage and is output to VOUT；Together
When input end signal by first feedforward level reach the 3rd gain stage output end；It is divided into two in the second gain stage output signal
Road：The output end of the 4th push-pull output stage is reached by the second feedforward level all the way, two tunnels are directly entered the 3rd gain stage；In amplification
The signal of device output end reaches input by active feedback loop (electric capacity Ca, the four, the second nmos pass transistor M16, M14)；
So far signal completes the amplification from input to output end.It can test and put in the output end loading heavy load electric capacity of amplifier
The small-signal AC response and the step response of big signal of big device, can be amplified the small-signal parameter and transient state ginseng of device
Number.In addition by after SRE, the Slew Rate of signal is strengthened.As a result show that this money level Four operational amplifier reduces compensation electricity
Hold, increase gain bandwidth product and Slew Rate, this during this is applied for the circuit of low-voltage and low-power dissipation is highly beneficial.
Claims (2)
1. a kind of low-power consumption level Four operational amplifier suitable for LCD drive circuits, it is characterized in that, by four gain amplification stages,
Two-way feed-forward loop level and an active feedback loop level composition；Four gain amplification stages are respectively：Transadmittance gain input stage,
Two to the 3rd high-gain stages, the 4th push-pull output stage；Two feed-forward loops level is respectively：Forward transconductance gain stage and negative sense mutual conductance
Gain stage；One active feedback loop level is made up of electric capacity and forward transconductance gain stage；The signal of input is defeated by transadmittance gain
Enter a grade gm1, the second to the 3rd gain stage, eventually pass the 4th push-pull output stage and be output to VOUT；The signal of input passes through simultaneously
Forward transconductance gain stage reaches the output end of the 3rd gain stage；It is divided into two-way in the second gain stage output signal：Pass through all the way
Negative sense transadmittance gain level reaches the output end of the 4th push-pull output stage, and another road is directly entered the 3rd gain stage；It is defeated in amplifier
The signal for going out end reaches input by active feedback loop level by electric capacity Ca and forward transconductance gain stage；
Amplifier concrete structure is：By the first to the 15th PMOS transistor M10, M11, M12, M17, M18, M20, M23, M30,
M33, M41, M411, M412, M50, M51, M52 and the first to the tenth bi-NMOS transistor M13, M14, M15, M16, M21,
Totally 27 MOS transistors, an electric capacity are that compensating electric capacity Ca is constituted by M22, M31, M32, M40, M413, M53, M54；Wherein：
Firstth, the 4th to the 15th PMOS transistor M10, M17, M18, M20, M23, M30, M33, M41, M411, M412, M50
Source electrode meet power supply VDD jointly；Except second, third, the 14th to the 15th PMOS transistor M11, M12, M51, M52
Substrate termination source electrode beyond, the first, the 4th to the 13rd PMOS transistor M10, M17, M18, M20, M23, M30, M33,
M41, M411, M412, M50 substrate termination power supply VDD；First, secondth, the 5th to the tenth bi-NMOS transistor M13,
M14, M21, M22, M31, M32, M40, M413, M53, M54 source electrode common ground GND；First to the 12nd M13, M14,
M15, M16, M21, M22, M31, M32, M40, M413, M53, M54 substrate terminal ground connection GND；
First PMOS transistor M10 grid connect the first bias voltage Vb1, drain electrode connect the second to the 3rd PMOS transistor M11,
M12 source electrode；The grid of the first to the second PMOS transistor M11, M12 connects input voltage vin-and Vin+ ends respectively；First
PMOS transistor M11, the first nmos pass transistor M13 drain electrode connect the 3rd nmos pass transistor M15 source electrode jointly, and the 3rd PMOS is brilliant
Body pipe M12, the second nmos pass transistor M14 drain electrode connect M16 source electrode jointly；The first to the second nmos pass transistor M13, M14's
Grid meets the second bias voltage Vb2 jointly, and the 3rd to the 4th nmos pass transistor M15, M16 grid connects the 3rd bias voltage jointly
Vb3；6th PMOS transistor M20 grid connects the 4th nmos pass transistor M16, the 5th PMOS transistor M18 drain electrode；4th to
The grid of 5th PMOS transistor M17, M18 connects the 4th PMOS transistor M17, the 3rd nmos pass transistor M15 drain electrode jointly；The
Four nmos pass transistor M16 source electrode connects compensating electric capacity Ca left end, and compensating electric capacity Ca right-hand member meets output end VOUT；
5th nmos pass transistor M21, the 6th nmos pass transistor M22 grid meet the 6th PMOS transistor M20, the 5th NMOS jointly
Transistor M21 drain electrode；7th PMOS transistor M23, the 6th nmos pass transistor M22 drain electrode connect the 8th PMOS transistor jointly
M30 grid；7th PMOS transistor M23 grid meets the 4th bias voltage Vb4；7th nmos pass transistor M31, the 8th NMOS
Transistor M32 grid connects the 8th PMOS transistor M30, the 7th nmos pass transistor M31 drain electrode jointly；9th PMOS transistor
M33, the 8th nmos pass transistor M32 drain electrode connect the 9th PMOS transistor M40 grid jointly；9th PMOS transistor M33's
Grid meets the 5th bias voltage Vb5；
9th nmos pass transistor M40, the tenth PMOS transistor M41 drain electrode, the 11st PMOS transistor M411 drain electrode are common
Meet output end VOUT；It is brilliant that tenth nmos pass transistor M413, the 12nd PMOS transistor M412 drain electrode meet the 11st PMOS jointly
Body pipe M411 grid；Tenth nmos pass transistor M413 grid meets the second bias voltage Vb2；12nd PMOS transistor M412
Grid meet the 6th bias voltage Vb6；
13rd PMOS transistor M50 grid meets the 6th bias voltage Vb6, drain electrode and connects the 14th to the 15th PMOS transistor
M51, M52 source electrode；The grid of 14th to the 15th PMOS transistor M51, M52 connects input voltage vin-and Vin+ respectively
End；11st to the tenth bi-NMOS transistor M53, M54 grid meets the 11st nmos pass transistor M53, the 14th PMOS jointly
Transistor M51 drain electrode；It is brilliant that tenth bi-NMOS transistor M54, the 15th PMOS transistor M52 drain electrode meet the 7th NMOS jointly
Body pipe M31 grid；External load capacitance CL meets VOUT.
2. it is applied to the low-power consumption level Four operational amplifier of LCD drive circuits as claimed in claim 1, it is characterized in that, by two
Individual mirrored transistor M11, M12 constitutes the first transadmittance gain input stage gm1, and forward transconductance gain stage is constituted by M16 transistors
gma；Transistor M20, M30 are the second to the 3rd gain stage gm2, gm3 respectively；Transistor M40, M41 constitute the 4th recommending output mode
Level gm4；M41 is negative sense transadmittance gain level gmf2；Three transistor M411-M413 constitute SR booster stages；Two mirrored transistors
M51-M52 composition forward transconductance gain stages gmf1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510150514.XA CN104779929B (en) | 2015-03-31 | 2015-03-31 | Suitable for the low-power consumption level Four operational amplifier of LCD drive circuits |
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| CN201510150514.XA CN104779929B (en) | 2015-03-31 | 2015-03-31 | Suitable for the low-power consumption level Four operational amplifier of LCD drive circuits |
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| CN104779929B true CN104779929B (en) | 2017-07-28 |
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Non-Patent Citations (4)
| Title |
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| A CMOS Low-Distortion Fully Differential Power Amplifier with Double Nested Miller Compensation;Sergio etal;《IEEE JOURNAL OF SOLID-STATE CIRCUITS》;19930731;第28卷(第7期);758-763页 * |
| A low-power four-stage amplifier for driving large capacitive loads;Mortaza Mojarad etal;《INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS》;20130124;第42卷(第9期);978-988页 * |
| 一种低功耗微弱信号放大电路的优化设计与研究;冀大雄等;《电子器件》;20080831;第31卷(第4期);1303-1306页 * |
| 高增益四级运放频率补偿技术;陆燕锋等;《浙江大学学报（工学版）》;20101130;第44卷(第11期);2137-2141页 * |
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