CN104779271B - MOS structure and preparation method thereof and the method for making metal silicide - Google Patents
MOS structure and preparation method thereof and the method for making metal silicide Download PDFInfo
- Publication number
- CN104779271B CN104779271B CN201410010653.8A CN201410010653A CN104779271B CN 104779271 B CN104779271 B CN 104779271B CN 201410010653 A CN201410010653 A CN 201410010653A CN 104779271 B CN104779271 B CN 104779271B
- Authority
- CN
- China
- Prior art keywords
- region
- metal
- drain region
- substrate
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 283
- 239000002184 metal Substances 0.000 title claims abstract description 283
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 113
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 105
- 238000000034 method Methods 0.000 title claims abstract description 80
- 238000002360 preparation method Methods 0.000 title description 4
- 239000000758 substrate Substances 0.000 claims abstract description 81
- 239000002210 silicon-based material Substances 0.000 claims abstract description 58
- 238000009413 insulation Methods 0.000 claims abstract description 44
- 230000008569 process Effects 0.000 claims abstract description 44
- 238000000137 annealing Methods 0.000 claims abstract description 38
- 238000004140 cleaning Methods 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims description 108
- 238000006243 chemical reaction Methods 0.000 claims description 73
- 239000000463 material Substances 0.000 claims description 26
- 239000010936 titanium Substances 0.000 claims description 18
- 239000007789 gas Substances 0.000 claims description 16
- 229910052719 titanium Inorganic materials 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- 230000009466 transformation Effects 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 239000011261 inert gas Substances 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 abstract description 24
- 230000008021 deposition Effects 0.000 description 69
- 239000010410 layer Substances 0.000 description 69
- 238000004151 rapid thermal annealing Methods 0.000 description 32
- 230000000694 effects Effects 0.000 description 30
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 20
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 12
- 150000001875 compounds Chemical class 0.000 description 12
- 229910052757 nitrogen Inorganic materials 0.000 description 11
- 239000000377 silicon dioxide Substances 0.000 description 10
- 229910004339 Ti-Si Inorganic materials 0.000 description 8
- 229910010978 Ti—Si Inorganic materials 0.000 description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 7
- 239000010931 gold Substances 0.000 description 7
- 229910052737 gold Inorganic materials 0.000 description 7
- 150000002739 metals Chemical class 0.000 description 7
- 229910052786 argon Inorganic materials 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 230000002596 correlated effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000010849 ion bombardment Methods 0.000 description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- NGWKGSCSHDHHAJ-YPFQVHCOSA-N Liquoric acid Chemical compound C1C[C@H](O)C(C)(C)C2CC[C@@]3(C)[C@]4(C)C[C@H]5O[C@@H]([C@](C6)(C)C(O)=O)C[C@@]5(C)[C@@H]6C4=CC(=O)C3[C@]21C NGWKGSCSHDHHAJ-YPFQVHCOSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- -1 such as Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
It is more particularly to a kind of that metal silicide method is made in MOS structure the present invention relates to technical field of semiconductors, to solve the problems, such as that the resistance value of metal silicide that is formed in the prior art on grid region, source region and drain region is bigger.The embodiment of the present invention makes metal silicide method in MOS structure, including：Under the first temperature conditionss, the deposited metal on the substrate formed with grid region, source region, drain region and insulation layer；Metal is set on grid region, source region and drain region to react respectively with grid region, source region and drain region silicon materials generation metal silicide；Wherein the value of the first temperature is not less than the temperature value that metal reacts with grid region, source region and drain region silicon materials；First time quick thermal annealing process is carried out to substrate；Cleaning treatment is carried out to the substrate Jing Guo first time quick thermal annealing process；Second of quick thermal annealing process is carried out to the substrate Jing Guo cleaning treatment.The resistance value for the metal silicide that the embodiment of the present invention ultimately generates is smaller.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of MOS structure and preparation method thereof and MOS tie
The method that metal silicide is made in structure.
Background technology
In the semiconductor device, comprising MOS（Metal-oxide-semicondutor）The device of structure, such as MOS device, CMOS
（Complementary metal oxide semiconductor）Device, BCD（Bipolar transistor-complementary metal oxide semiconductor-double diffused metal oxidation
Thing semiconductor）Device and RF LDMOS（Rf-ldmos semiconductor）The application of device is very extensive.
Wherein, the method for making the MOS structure in semiconductor devices, including：
Step A1, source region and drain region are formed in the substrate, and form grid region and insulation layer over the substrate；Wherein,
Source region and drain region are located at the both sides in the grid region respectively, and insulation layer is between the grid region and the source region and is located at the grid
Between area and the drain region, for making source region and drain region and grid region mutually insulated；
Step A2, the oxide layer of covering grid region, source region, drain region and insulation layer is formed；
Step A3, patterned process is carried out to the oxide layer, is formed and expose first via in grid region, expose source region
The second via and expose the 3rd via in drain region；
Step A4, metal layer is formed in the oxide layer comprising first via, the second via and the 3rd via, than
Such as, Al（Aluminium）Layer；Wherein, the metal of the metal layer can be dropped into first via, contacted with the grid region, form grid
Electrode；The metal of the metal layer can be dropped into second via, with the source contact, form source electrode；The gold
Belonging to the metal of layer can drop into the 3rd via, with the drain contact, form drain electrode.
Since the material in grid region is the bigger polysilicon of resistance value, gate resistance is bigger；Further, since metal layer
The metal grid region bigger with resistance value contact, therefore the metal and the contact resistance in grid region are bigger, are additionally, since source
The material in area and drain region is monocrystalline silicon, therefore the metal and contact of the contact resistance and the metal of source region with drain region
Resistance is also bigger.Since the gate resistance and contact resistance of MOS structure are bigger, so as to cause to include the semiconductor of MOS structure
The power consumption of device is bigger.
Currently in order to reduce the gate resistance and contact resistance, to reduce the power consumption of the semiconductor devices comprising MOS structure,
Metal silicide can be generally formed on the grid region, source region and drain region, then performs step again before the step A2
A2 and subsequent step.For gate resistance, since the resistance value of the metal silicide on grid region is smaller than the gate resistance in grid region,
Therefore it is in parallel with the grid region by the metal silicide, the gate resistance value in grid region can be reduced；For contact resistance, due to
Metal silicide is located on grid region, source region and drain region, thus the metal of the metal layer in step A4 directly with the resistance
It is worth smaller Metal-silicides Contact, so as to reduce the contact resistance.
Wherein, metal silicide is formed on the grid region, source region and drain region at present, including：
Step B1, be room temperature in depositing temperature, vacuum, under conditions of deposition power is setting deposition power, formed with
Grid region, source region, drain region and insulation layer substrate on deposit one layer of metal, a length of setting deposition duration during deposition；
Wherein, in step bl is determined, set deposition power and setting deposition duration value can rule of thumb or need set
It is fixed；For example when the metal of deposition is titanium, the value for setting deposition power is generally 2.5kw（Kilowatt）, setting deposition duration
Value is generally 10s（Second）-15s；
By the value for setting setting deposition power and setting deposition duration, it is possible to achieve the thickness of deposited metal is controlled,
Such as in the value for setting deposition power as 2.5kw, when setting the value of deposition duration as 10s-15s, the thickness of the metal of deposition
Angle value is generally 200A（Angstrom）-1000A.
Wherein, in step bl is determined, metal targets are included in the reaction chamber of depositing device；Formed with grid region, source region, drain region
It is located at the substrate of insulation layer in the reaction chamber of depositing device；Depositing device is real by controlling argon gas ion to bombard metal targets
One layer of metal is deposited on substrate now formed with grid region, source region, drain region and insulation layer；Thus, depositing temperature is depositing device
Reaction chamber temperature, be vacuum state in the reaction chamber of depositing device, deposition power is argon gas ion bombardment metal targets
Energy, when deposition a length of argon gas ion bombardment metal targets duration.
Wherein, in step bl is determined, depositing device is by the instruction from the user that receives, control the depositing temperature,
The reaction chamber of depositing device is vacuum state, deposition power and deposition duration.
Step B2, be the first rapid thermal annealing temperature of setting in rapid thermal annealing temperature, under conditions of nitrogen, to grid region,
The substrate that deposition has metal on source region, drain region and insulation layer carries out first time quick thermal annealing process, and when rapid thermal annealing is a length of
Set the first rapid thermal annealing duration；So that a part of metal reacts with grid region, source region and drain region respectively, generation 49 phases gold
Belong to silicide；A part of metal reacts with nitrogen, generates metal nitride；A part of metal has neither part nor lot in reaction；
Wherein, depositing temperature is less than first time rapid thermal annealing temperature, when deposition duration is less than first time rapid thermal annealing
It is long；
Set the first rapid thermal annealing temperature and set the first rapid thermal annealing duration value can rule of thumb or need
Set；For example the value range of the first rapid thermal annealing duration is set as 20s-40s, and when the metal of deposition is titanium,
The value range of the first rapid thermal annealing temperature is set as 650 DEG C -750 DEG C.
Wherein, the substrate that being deposited in step B2, on grid region, source region, drain region and insulation layer has metal is located at fast speed heat and moves back
In the reaction chamber of fiery equipment, rapid thermal annealing temperature is the temperature of reaction chamber, the gas in the reaction chamber of rapid thermal annealers
For nitrogen；Rapid thermal annealers control the rapid thermal annealing temperature, its reaction by the instruction from the user received
The gas and duration of intracavitary.
Wherein, in step B2, the material of insulation layer is silica, when temperature is the first rapid thermal annealing temperature,
The metal and silica of deposition do not react.
Step B3, wash metal nitride and be not engaged in the metal of reaction；
Wherein, in step B3, the part metals on insulation layer have neither part nor lot in reaction, therefore, can be cleaned out.
Step B4, be the second rapid thermal annealing temperature of setting in rapid thermal annealing temperature, under conditions of nitrogen, to grid region,
The substrate formed with 49 phase metal silicides carries out second of quick thermal annealing process, rapid thermal annealing duration in source region and drain region
To set the second rapid thermal annealing duration so that the 49 phase metal silicide is changed into 54 phase metal silicides；Wherein 54 phases
The resistance value of metal silicide is about 1/3rd of 49 phase metal silicides.
Wherein, first time rapid thermal annealing temperature is less than second of rapid thermal annealing temperature, during first time rapid thermal annealing
Length can less than, greater than or equal to second rapid thermal annealing duration；
Set the second rapid thermal annealing temperature and set the second rapid thermal annealing duration value can rule of thumb or need
Set；For example the value range of the second rapid thermal annealing duration is set as 20s-40s, and when the metal of deposition is titanium,
The value range of the second rapid thermal annealing temperature is set as 800 DEG C -900 DEG C.
In above-mentioned steps B2, since the gas in the reaction chamber of rapid thermal annealers is nitrogen, thus the is being carried out
During quick thermal annealing process, part metals can react with nitrogen, generate the metal nitride that can be cleaned out, so that
Reduce the metal with grid region, source region and drain region reaction so that the reaction of grid region, source region and drain region and metal is insufficient, generation
Metal silicide thickness value it is smaller so that the resistance value of the metal silicide ultimately generated is bigger, so that subtracting
The small gate resistance and the effect of contact resistance are not so good, further, reduce the power consumption of the semiconductor devices comprising MOS structure
Effect it is also not so good.
In conclusion the resistance value of the metal silicide formed at present on grid region, source region and drain region is bigger so that subtracts
Small gate resistance and the effect of contact resistance are not so good, cause to reduce the effect of the power consumption of the semiconductor devices comprising MOS structure
Poorly.
The content of the invention
A kind of MOS structure provided in an embodiment of the present invention and preparation method thereof and metal silication is made in MOS structure
The method of thing, to solve the electricity of the metal silicide existing in the prior art formed at present on grid region, source region and drain region
Resistance value is bigger so that reduction gate resistance and the effect of contact resistance are not so good, so as to cause to reduce partly leading comprising MOS structure
The problem of effect of the power consumption of body device is also not so good.
In a first aspect, the first method that metal silicide is made in MOS structure provided in an embodiment of the present invention, bag
Include：
Step A, in the case where depositing temperature is the first temperature conditionss, in the substrate formed with grid region, source region, drain region and insulation layer
One layer of metal of upper deposition；Make the metal on the grid region, source region and the drain region respectively with the grid region, source region and drain region
Silicon materials react generation metal silicide；The value of wherein described first temperature is not less than the metal and the grid
The temperature value that the silicon materials in area, source region and drain region react；
Step B, first time quick thermal annealing process is carried out to the substrate；
Step C, cleaning treatment is carried out to the substrate after first time quick thermal annealing process；
Step D, to carrying out second of quick thermal annealing process by the cleaned substrate, the grid are changed
The phase of the metal silicide formed on area, source region and drain region.
Depositing temperature when in embodiments of the present invention, compared with prior art, in step, by deposited metal improves
For first temperature of the value not less than the temperature value that the silicon materials of metal and grid region, source region and drain region react；It can cause
In deposited metal, deposit to the silicon materials of metal on grid region, source region and drain region respectively with the grid region, source region and drain region and send out
Raw reaction generation metal silicide；That is, when performing the step of deposited metal, the metal of deposition will respectively with the grid
The silicon materials in area, source region and drain region react, and metal silicide is formed on the grid region, source region and drain region；
So that by carrying out first time quick thermal annealing process to the substrate, the metal of deposition and the grid region,
The silicon materials in source region and drain region continue to react so that the metal of deposition and the silicon materials in the grid region, source region and drain region
Reaction is more abundant, and the thickness value of the metal silicide ultimately generated is bigger and resistance value is smaller, so that reducing institute
It is relatively good to state the effect of gate resistance and contact resistance, further, reduces the effect of the power consumption of the semiconductor devices comprising MOS structure
Fruit is also relatively good.
It is preferred that when carrying out first time quick thermal annealing process to the substrate, in the reaction chamber that the substrate is located at
Gas be inert gas.
In embodiments of the present invention, due to the substrate carry out first time quick thermal annealing process when, inert gas
The metal with deposition does not react, and therefore, will not consume the metal, avoids waste the gold to a certain extent
Belong to, and avoid reducing the metal reacted with the silicon materials in the grid region, source region and drain region to a certain extent so that the gold
Belong to more abundant with the extent of reaction of the silicon materials in grid region, source region and drain region.
It is preferred that the value of first temperature is less than the temperature that the material of the metal and the insulation layer reacts
Value.
In embodiments of the present invention, can be interconnected to avoid grid region, source region and drain region.
It is preferred that the metal is titanium.
In embodiments of the present invention, there is provided a kind of embodiment of metal, so that those skilled in the art can be with
It is easily carried out technical scheme.It should be noted that the specific metal in the embodiment of the present invention is served only for
Explain the present invention, and be not intended to limit the invention, other metals that can be used for realizing technical solution of the present invention are also in this hair
Within bright protection domain.
Second aspect, the second provided in an embodiment of the present invention method that metal silicide is made in MOS structure, bag
Include：
Step A, in the case where depositing temperature is the first temperature conditionss, in the substrate formed with grid region, source region, drain region and insulation layer
One layer of metal of upper deposition, a length of first duration during deposition；Make the metal on the grid region, source region and the drain region respectively with
The silicon materials in the grid region, source region and drain region react, and generate metal silicide；Wherein, the value of first temperature is not
Less than abundant reaction temperature threshold value, the fully reaction temperature threshold value reacts for the material of the metal and the insulation layer
Temperature value and fluctuating temperature value difference, the value range of the fluctuating temperature value is [50 DEG C, 100 DEG C]；When described first
Long value range is [20s, 40s]；
Step B, cleaning treatment is carried out to the substrate；
Step C, to carrying out quick thermal annealing process by the cleaned substrate, the grid region, source region are changed
With the phase of metal silicide formed on drain region.
Depositing temperature when in embodiments of the present invention, compared with prior art, in step, by deposited metal improves
It is not less than the first temperature of abundant reaction temperature threshold value for value, and deposition duration is extended for the first duration；It can cause
When performing the step of deposited metal, deposit to metal on grid region, source region and drain region respectively with the grid region, source region and drain region
Fully reaction generation metal silicide occurs for silicon materials；That is, when performing the step of deposited metal, the metal of deposition can divide
Fully reaction does not occur with the silicon materials in the grid region, source region and drain region, metallic silicon is formed on the grid region, source region and drain region
Compound；
Due to when performing the step of deposited metal, the metal of deposition respectively with the grid region, source region and drain region
Fully reaction occurs for silicon materials, forms metal silicide on the grid region, source region and drain region so that the metallic silicon ultimately generated
The thickness value of compound is bigger and resistance value is smaller, so that the effect for reducing the gate resistance and contact resistance compares
Good, further, the effect for reducing the power consumption of the semiconductor devices comprising MOS structure is also relatively good；
And due to when performing the step of deposited metal, the metal of deposition respectively with the grid region, source region and leakage
Fully reaction occurs for the silicon materials in area, metal silicide is formed on the grid region, source region and drain region, so as to omit to institute
The step of substrate carries out first time quick thermal annealing process is stated, reduces the cost that metal silicide is made in MOS structure, with
And reduce the complexity that metal silicide is made in MOS structure.
It is preferred that when depositing one layer of metal, the value of deposition power and the value of first duration are negatively correlated.
In embodiments of the present invention, the thickness of the metal of deposition can be controlled, is occurred so as to fulfill control and the metal
The amount of the silicon materials in the grid region of reaction, source region and drain region, and then ensure the electrical property of MOS structure.
It is preferred that the value of first temperature is less than the temperature that the material of the metal and the insulation layer reacts
Value.
In embodiments of the present invention, can be interconnected to avoid grid region, source region and drain region.
It is preferred that the metal is titanium.
In embodiments of the present invention, there is provided a kind of embodiment of metal, so that those skilled in the art can be with
It is easily carried out technical scheme.It should be noted that the specific metal in the embodiment of the present invention is served only for
Explain the present invention, and be not intended to limit the invention, other metals that can be used for realizing technical solution of the present invention are also in this hair
Within bright protection domain.
The third aspect, the embodiment of the present invention provide a kind of production method of MOS structure, including：
Source region and drain region are formed in the substrate, and form grid region and insulation layer over the substrate；
Using the method that metal silicide is made in MOS structure, in the grid region of the substrate, source region and drain region
The upper metal silicide for forming transformation phase；
The oxide layer for covering the metal silicide and insulation layer is formed, patterned process is carried out to the oxide layer, with
And metal layer is formed in the oxide layer after patterned process, to form gate electrode, source electrode and drain electrode respectively.
In embodiments of the present invention, the first described method that metal silicide is made in MOS structure is being used,
When the metal silicide of transformation phase is formed on the grid region of the substrate, source region and drain region so that finally formed metal silication
The thickness value of thing is bigger and resistance value is smaller, so that the effect for reducing the gate resistance and contact resistance is relatively good,
Further, the effect for reducing the power consumption of the semiconductor devices comprising MOS structure is also relatively good；And
Using described second in MOS structure make metal silicide method, in the grid region of the substrate, source
When the metal silicide of transformation phase is formed in area and drain region, not only so that the thickness value of finally formed metal silicide compares
Big and resistance value is smaller, reduces that the effect of the gate resistance and contact resistance is relatively good, reduces the semiconductor for including MOS structure
The effect of the power consumption of device is also relatively good；And allow to omit and first time quick thermal annealing process is carried out to the substrate
Step, reduces the cost of manufacture of MOS structure, and reduces the making complexity of MOS structure.
Fourth aspect, the embodiment of the present invention provide a kind of MOS structure, wherein：The MOS structure is by the MOS structure
Production method is made.
In embodiments of the present invention, the gate resistance of MOS structure and contact resistance are smaller, partly leading comprising the MOS structure
The power consumption of body device is also smaller；In addition, the cost of manufacture of the MOS structure is smaller and makes complexity than relatively low.
Compared with prior art, in the first method that metal silicide is made in MOS structure of the embodiment of the present invention
In, depositing temperature during by deposited metal rise to value occur not less than the silicon materials of metal and grid region, source region and drain region it is anti-
First temperature of the temperature value answered；Can, in deposited metal, to deposit to metal on grid region, source region and drain region respectively with
The silicon materials in the grid region, source region and drain region, which react, generates metal silicide；So that by being carried out to the substrate
The silicon materials in first time quick thermal annealing process, the metal of deposition and the grid region, source region and drain region continue to react so that
The metal of deposition and the reaction of the silicon materials in the grid region, source region and drain region are more abundant, the metal silicide ultimately generated
Thickness value is bigger and resistance value is smaller, so that the effect for reducing the gate resistance and contact resistance is relatively good, into one
Step ground, the effect for reducing the power consumption of the semiconductor devices comprising MOS structure are also relatively good.
Compared with prior art, the method for making metal silicide in MOS structure at second of the embodiment of the present invention
In, depositing temperature during by deposited metal rises to the first temperature that value is not less than abundant reaction temperature threshold value, and will deposition
Duration is extended for the first duration；It can, when performing the step of deposited metal, to deposit to the gold on grid region, source region and drain region
Belong to and fully reaction generation metal silicide occurs with the silicon materials in the grid region, source region and drain region respectively；So that ultimately generate
The thickness value of metal silicide is bigger and resistance value is smaller, so that reducing the gate resistance and the effect of contact resistance
Relatively good, further, the effect for reducing the power consumption of the semiconductor devices comprising MOS structure is also relatively good；And eliminate pair
The substrate carries out the step of first time quick thermal annealing process, reduces the cost that metal silicide is made in MOS structure,
And reduce the complexity that metal silicide is made in MOS structure.
Brief description of the drawings
Fig. 1 is the method flow schematic diagram that the first in the embodiment of the present invention makes metal silicide in MOS structure；
Fig. 2 is second of method flow schematic diagram that metal silicide is made in MOS structure in the embodiment of the present invention；
Fig. 3 A~Fig. 3 E are to make MOS structure during metal silicide in the embodiment of the present invention in MOS structure
Diagrammatic cross-section；
Fig. 4 is the production method flow diagram of MOS structure in the embodiment of the present invention.
Embodiment
In embodiments of the present invention, the method for making metal silicide in MOS structure for the first, by deposited metal
When depositing temperature rise to the of value not less than the temperature value that the silicon materials in metal and grid region, source region and drain region react
One temperature；Can, in deposited metal, to deposit to metal on grid region, source region and drain region respectively with the grid region, source region
React with the silicon materials in drain region and generate metal silicide；So that moved back by carrying out fast speed heat for the first time to the substrate
The silicon materials in fire processing, the metal of deposition and the grid region, source region and drain region continue to react so that the metal of deposition and institute
State the metal silicide that the reaction of the silicon materials in grid region, source region and drain region is more abundant, ultimately generates thickness value it is bigger and
Resistance value is smaller, so that the effect for reducing the gate resistance and contact resistance is relatively good, further, reduction includes
The effect of the power consumption of the semiconductor devices of MOS structure is also relatively good；
The method for making metal silicide in MOS structure for second, depositing temperature during by deposited metal improve
It is not less than the first temperature of abundant reaction temperature threshold value for value, and deposition duration is extended for the first duration；It can cause
When performing the step of deposited metal, deposit to metal on grid region, source region and drain region respectively with the grid region, source region and drain region
Fully reaction generation metal silicide occurs for silicon materials；So that the thickness value of the metal silicide ultimately generated is bigger and resistance
It is worth smaller, so that the effect for reducing the gate resistance and contact resistance is relatively good, further, reduces and tied comprising MOS
The effect of the power consumption of the semiconductor devices of structure is also relatively good；And eliminate and the substrate is carried out at first time rapid thermal annealing
The step of reason, reduce the cost that metal silicide is made in MOS structure, and reduces and metal is made in MOS structure
The complexity of silicide.
The embodiment of the present invention is described in further detail with reference to Figure of description.
It should be noted that in embodiments of the present invention, there is provided two kinds of sides that metal silicide is made in MOS structure
Method, will be introduced respectively below.
As shown in Figure 1, the first of the embodiment of the present invention makes the method for metal silicide including following in MOS structure
Step：
Step 101, depositing temperature be the first temperature conditionss under, in the lining formed with grid region, source region, drain region and insulation layer
One layer of metal is deposited on bottom；Make the metal on the grid region, source region and the drain region respectively with the grid region, source region and leakage
The silicon materials in area, which react, generates metal silicide；The value of wherein described first temperature is not less than the metal and the grid
The temperature value that the silicon materials in area, source region and drain region react；
Step 102, carry out first time quick thermal annealing process to the substrate；
Step 103, carry out cleaning treatment to the substrate after first time quick thermal annealing process；
Step 104, carry out second of quick thermal annealing process to passing through the cleaned substrate, changes the grid
The phase of the metal silicide formed on area, source region and drain region.
In implementation, compared with prior art, in a step 101, depositing temperature during by deposited metal rises to value not
First temperature of the temperature value to react less than the silicon materials of metal and grid region, source region and drain region；It can cause in deposition gold
During category, the metal that deposits on grid region, source region and drain region reacts life with the silicon materials in the grid region, source region and drain region respectively
Into metal silicide；That is, when performing the step of deposited metal, the metal of deposition will respectively with the grid region, source region
React with the silicon materials in drain region, metal silicide is formed on the grid region, source region and drain region；
So that by carrying out first time quick thermal annealing process to the substrate, the metal of deposition and the grid region,
The silicon materials in source region and drain region continue to react so that the metal of deposition and the silicon materials in the grid region, source region and drain region
Reaction is more abundant, and the thickness value of the metal silicide ultimately generated is bigger and resistance value is smaller, so that reducing MOS
The effect of gate resistance and contact resistance in structure is relatively good, further, reduces the work(of the semiconductor devices comprising MOS structure
The effect of consumption is also relatively good.
It is preferred that in embodiments of the present invention, the metal of deposition can be any metal in the prior art, such as, Ti
（Titanium）、Co（Cobalt）Or Ni（Nickel）.
It is preferred that in a step 101, temperature value that the silicon materials in the metal and the grid region react is equal to described
The temperature value that metal and the silicon materials of source region and drain region react；
The material in the grid region is polysilicon, and the material in the source region and drain region is monocrystalline silicon；The metal and polysilicon
The temperature value to react is equal to the temperature value that the metal reacts with monocrystalline silicon.
In implementation, the value of the first temperature occurs not less than the metal and the silicon materials in the grid region, source region and drain region
The temperature value of reaction, it is ensured that under the first temperature conditionss, the metal and the silicon materials in the grid region, source region and drain region are equal
React generation metal silicide.
It is preferred that in a step 101, the value of the first temperature is less than the metal and the material of the insulation layer occurs instead
The temperature value answered；
The material of the insulation layer is silica；The value of first temperature is less than the metal and is sent out with silica
The temperature value of raw reaction.
In implementation, the value of the first temperature is less than the temperature value that the material of the metal and the insulation layer reacts,
It can be interconnected to avoid grid region, source region and drain region.
In specific implementation, in a step 101, depositing temperature is the temperature of the reaction chamber of depositing device.
In specific implementation, in a step 101, one layer is deposited on the substrate formed with grid region, source region, drain region and insulation layer
During metal, the other specification in addition to depositing temperature, such as, vacuum, deposition power in the reaction chamber of depositing device and
The embodiment for depositing duration is similar with embodiment of the prior art.
In specific implementation, in a step 102, the embodiment that first time quick thermal annealing process is carried out to the substrate can
With similar with embodiment of the prior art.
It is preferred that in a step 102, when carrying out first time quick thermal annealing process to the substrate, the substrate position
In reaction chamber in（That is, in the reaction chamber of rapid thermal annealers）Gas be inert gas, such as, argon gas.
In implementation, to the substrate carry out first time quick thermal annealing process when, inert gas not with described in deposition
Metal reacts, and therefore, will not consume the metal, avoids waste the metal to a certain extent, and certain
Avoid reducing the metal reacted with the silicon materials in the grid region, source region and drain region in degree so that the metal and grid region, source region
It is more abundant with the extent of reaction of the silicon materials in drain region.
In specific implementation, in step 103, the substrate after first time quick thermal annealing process is cleaned
The embodiment of processing is similar with embodiment of the prior art；
Wherein, if in a step 102, to the substrate carry out first time quick thermal annealing process when, the substrate position
In reaction chamber in gas be inert gas；Then in step 103, the metal for being not engaged in reaction is only washed；
If in a step 102, when carrying out first time quick thermal annealing process to the substrate, the substrate is located at anti-
The gas for answering intracavitary is nitrogen；Then in step 103, the metal of reaction is not engaged in except washing, it is also necessary to wash nitrogen
Gas and the metal nitride of metal reaction generation.
In specific implementation, at step 104, to carrying out second of rapid thermal annealing by the cleaned substrate
The embodiment of processing is similar with embodiment of the prior art.
It should be noted that in embodiments of the present invention, in a step 101, the metal silicide of generation is 49 phase metals
Silicide；In a step 102, to the substrate carry out first time quick thermal annealing process so that the metal of deposition respectively with grid
The silicon materials in area, source region and drain region continue the to react metal silicide of generation is 49 phase metal silicides；In step 104
In, the 49 phase metal silicides formed on the grid region, source region and drain region are changed into 54 phase metal silicides.
As shown in Fig. 2, second of the embodiment of the present invention method that metal silicide is made in MOS structure is including following
Step：
Step 201, depositing temperature be the first temperature conditionss under, in the lining formed with grid region, source region, drain region and insulation layer
One layer of metal is deposited on bottom, a length of first duration during deposition；Make the metal difference on the grid region, source region and drain region
React with the silicon materials in the grid region, source region and drain region, generate metal silicide；Wherein, the value of first temperature
Not less than abundant reaction temperature threshold value, the fully reaction temperature threshold value occurs anti-for the material of the metal and the insulation layer
The temperature value and the difference of fluctuating temperature value answered, the value range of the fluctuating temperature value is [50 DEG C, 100 DEG C]；Described first
The value range of duration is [20s, 40s]；
Step 202, carry out cleaning treatment to the substrate；
Step 203, carry out quick thermal annealing process to passing through the cleaned substrate, changes the grid region, source
The phase of the metal silicide formed in area and drain region.
In implementation, compared with prior art, in step 201, depositing temperature during by deposited metal rises to value not
The first duration is extended for less than the first temperature of abundant reaction temperature threshold value, and by deposition duration；It can performing deposition
During the step of metal, deposit to the silicon materials of metal on grid region, source region and drain region respectively with the grid region, source region and drain region and send out
Raw fully reaction generation metal silicide；That is, when performing the step of deposited metal, the metal of deposition can respectively with
Fully reaction occurs for the silicon materials in the grid region, source region and drain region, and metal silication is formed on the grid region, source region and drain region
Thing；
Due to when performing the step of deposited metal, the metal of deposition respectively with the grid region, source region and drain region
Fully reaction occurs for silicon materials, forms metal silicide on the grid region, source region and drain region so that the metallic silicon ultimately generated
The thickness value of compound is bigger and resistance value is smaller, so that the effect for reducing the gate resistance and contact resistance compares
Good, further, the effect for reducing the power consumption of the semiconductor devices comprising MOS structure is also relatively good；
And due to when performing the step of deposited metal, the metal of deposition respectively with the grid region, source region and leakage
Fully reaction occurs for the silicon materials in area, metal silicide is formed on the grid region, source region and drain region, so as to omit to institute
The step of substrate carries out first time quick thermal annealing process is stated, reduces the cost that metal silicide is made in MOS structure, with
And reduce the complexity that metal silicide is made in MOS structure.
It is preferred that in embodiments of the present invention, the metal of deposition can be any metal in the prior art, such as, Ti
（Titanium）、Co（Cobalt）Or Ni（Nickel）.
It is preferred that in step 201, the value of the first temperature is not less than abundant reaction temperature threshold value, the fully reaction
The temperature value and the difference of fluctuating temperature value that temperature threshold reacts for the material of the metal and the insulation layer, the ripple
The value range of dynamic temperature angle value is [50 DEG C, 100 DEG C]；I.e. the lower limit of the value range of the first temperature is the fully reaction temperature
Spend threshold value；
The material of the insulation layer is silica, and the fully reaction temperature threshold value is sent out for the metal and silica
The temperature value of raw reaction and the difference of fluctuating temperature value.Wherein, the lower limit of the value range of the first temperature in step 201 is big
The lower limit of the value range of the first temperature in step 101.
It is preferred that in step 201, the value of first temperature is less than the material hair of the metal and the insulation layer
The temperature value of raw reaction；I.e. the upper limit value of the value range of the first temperature occurs anti-for the material of the metal and the insulation layer
The temperature value answered；
The material of the insulation layer is silica, and the value of first temperature is less than the metal and is sent out with silica
The temperature value of raw reaction.
In implementation, the value of the first temperature is less than the temperature value that the material of the metal and the insulation layer reacts,
It can be interconnected to avoid grid region, source region and drain region.
It is preferred that in step 201, the value range of the upper limit value of the value range of the first temperature and first temperature
Lower limit difference between 50 DEG C -100 DEG C.
In implementation, the value of the first temperature is not less than the fully reaction temperature threshold value, and when a length of first during deposition
It is long, it is ensured that fully reaction occurs for the metal and the silicon materials in the grid region, source region and drain region, and generation thickness value is bigger
And the metal silicide that resistance value is smaller.
It is preferred that in step 201, when depositing one layer of metal, the value of deposition power and first duration
Value it is negatively correlated.
In implementation, in the value of deposition power and the negatively correlated value of first duration, the gold of deposition can be controlled
The thickness of category will not be too thick, the amount of the silicon materials in the grid region, source region and the drain region that react so as to fulfill control with the metal
Will not be too many, and then ensure the electrical property of MOS structure.
In specific implementation, in step 201, depositing temperature is the temperature of the reaction chamber of depositing device, a length of argon during deposition
The duration of gas ion bombardment metal targets, deposition power bombard the energy of metal targets for argon gas ion.
In specific implementation, in step 201, one layer is deposited on the substrate formed with grid region, source region, drain region and insulation layer
During metal, the embodiment of the vacuum in the reaction chamber of depositing device is similar with embodiment of the prior art.
It is vacuum state in the reaction chamber of depositing device, it is ensured that the metal of deposition is not in step 201 in implementation
React with the material in addition to the silicon materials in the grid region, source region and drain region, avoid to a certain extent reduce with it is described
The metal of the silicon materials reaction in grid region, source region and drain region so that the reaction of the metal and the silicon materials in grid region, source region and drain region
Degree is more abundant.
In specific implementation, in step 202, to the substrate carry out cleaning treatment embodiment with it is of the prior art
Embodiment is similar；
In step 202, the metal for being not engaged in reaction is only washed.
In specific implementation, in step 203, to carrying out quick thermal annealing process by the cleaned substrate
Embodiment is similar with embodiment of the prior art.
It should be noted that in embodiments of the present invention, in step 201, the metal silicide of generation is 49 phase metals
Silicide；In step 203, the 49 phase metal silicides formed on the grid region, source region and drain region are changed into 54 phase metals
Silicide.
For scheme that is detailed, clearly demonstrating the embodiment of the present invention, below using the metal of deposition as Ti, to of the invention real
The first method that metal silicide is made in MOS structure for applying example describes in detail.
Embodiment one
As shown in Figure 3A, MOS structure includes substrate 1, the source region 2 in substrate 1 and drain region 3 and on substrate 1
Grid region 4 and insulation layer 5；Wherein the material in source region 2 and drain region 3 is monocrystalline silicon, and the material in grid region 4 is polysilicon, insulation layer 5
Material is silica；TiIt is 200 DEG C with the temperature value that monocrystalline silicon and polysilicon react, TiReact with silica
Temperature value be 750 DEG C, the value range of depositing temperature is [200 DEG C, 750 DEG C）.
Step A1, it is 200 DEG C~500 DEG C in depositing temperature, the vacuum of the reaction chamber of depositing device is 3mt（Millitorr）,
Under conditions of deposition power is 2.5kw, one layer of T is deposited on the substrate formed with grid region, source region, drain region and insulation layeri, deposition
Shi Changwei 10s-15s；So that the T on the grid region, source region and drain regioniRespectively with the silicon in the grid region, source region and drain region
Material, which reacts, generates 49 phase Ti-SiCompound；
Wherein, after execution of step A1, as shown in Figure 3B, the part T on grid region 4i6 with the silicon materials in grid region 4
React 49 phase T of generationi-SiCompound 7, the part T in source region 2i6 react generation 49 with the silicon materials of source region 2
Phase Ti-SiCompound 7, and the part T on drain region 3i6 react 49 phase T of generation with the silicon materials in drain region 3i-SiChemical combination
Thing 7.
Wherein, in step A1, deposition when a length of 10s-15s and deposition power be 2.5kw when, the T of depositioniThickness
Angle value is in the range of 200A~1000A.Step A2, it is 650 DEG C~750 DEG C in rapid thermal annealing temperature, and rapid thermal annealing is set
The gas of standby reaction chamber be nitrogen under conditions of, to the substrate carry out first time quick thermal annealing process, rapid thermal annealing
Shi Changwei 20s-40s；So that the T on the grid region, source region and drain regioniContinue the silicon with the grid region, source region and drain region
Material, which reacts, generates 49 phase Ti-SiCompound；Nitrogen and a small amount of TiReact, generate Ti- N compounds；
Wherein, after execution of step A2, as shown in Figure 3 C, part TiContinue the life that reacts with the silicon materials in grid region 4
Into 49 phase Ti-SiCompound 7, part TiContinue the 49 phase T of generation that react with the silicon materials of source region 2i-SiCompound 7, and portion
Divide TiContinue the 49 phase T of generation that react with the silicon materials in drain region 3i-SiCompound 7；The part T contacted with nitrogeniSent out with nitrogen
Raw reaction, generates Ti- N compounds 8.
Step A3, using the mixed liquor or sulfuric acid of ammonium hydroxide and hydrogen peroxide and the mixed liquor of hydrogen peroxide, by Ti- N compounds
With the T that reaction is had neither part nor lot on insulation layeriWash；
Wherein, after execution of step A3, as shown in Figure 3D, formed with 49 phase T on source region 2, drain region 3 and grid region 4i-SiChange
Compound 7；Without the 49 phase T on insulation layer 5i-SiCompound 7.
Step A4, it is 800 DEG C~900 DEG C in rapid thermal annealing temperature, and the gas of the reaction chamber of rapid thermal annealers
Under conditions of nitrogen, second of quick thermal annealing process is carried out to the substrate, a length of 20s-40s during rapid thermal annealing；Turn
Become on the grid region, source region and drain region the 49 phase T formedi-SiThe phase of compound, by the 49 phase Ti-SiCompound is changed into
54 phase Ti-SiCompound.
Wherein, after execution of step A4, as shown in FIGURE 3 E, 54 phase T are formd on source region 2, drain region 3 and grid region 4i-SiChange
Compound 9.
Wherein, the 54 phase Ti-SiThe resistance of compound probably only 49 phase Ti-Si/ 3rd of compound.
Wherein, to deposit TiThickness value for 400A tested when, made using of the prior art in MOS structure
The 54 phase T that the method for metal silicide is formedi-SiThe thickness value of compound is about 580A, and square resistance is about 9.2ohm（Europe
Nurse）；The 54 phase T formed using the method for making metal silicide in the embodiment of the present invention one in MOS structurei-SiCompound
Thickness value is about 900A, and square resistance is about 5.7ohm.
As shown in figure 4, the production method of the MOS structure of the embodiment of the present invention comprises the following steps：
Step 401, form source region and drain region in the substrate, and forms grid region and insulation layer over the substrate；
Step 402, the method using the making metal silicide in MOS structure, in the grid region of the substrate, source
The metal silicide of transformation phase is formed in area and drain region；
Step 403, form the oxide layer for covering the metal silicide and insulation layer, and the oxide layer is patterned
Processing, and metal layer is formed in the oxide layer after patterned process, to form gate electrode, source electrode and electric leakage respectively
Pole.
In implementation, the first described method that metal silicide is made in MOS structure is being used, in the substrate
When the metal silicide of transformation phase is formed on grid region, source region and drain region so that the thickness value of finally formed metal silicide
Bigger and resistance value is smaller, so that the effect for reducing the gate resistance and contact resistance is relatively good, further, drop
The effect of the power consumption of the low semiconductor devices comprising MOS structure is also relatively good；And
Using described second in MOS structure make metal silicide method, in the grid region of the substrate, source
When the metal silicide of transformation phase is formed in area and drain region, not only so that the thickness value of finally formed metal silicide compares
Big and resistance value is smaller, reduces that the effect of the gate resistance and contact resistance is relatively good, reduces the semiconductor for including MOS structure
The effect of the power consumption of device is also relatively good；And allow to omit and first time quick thermal annealing process is carried out to the substrate
Step, reduces the cost of manufacture of MOS structure, and reduces the making complexity of MOS structure.
In specific implementation, in step 401, source region and drain region are formed in the substrate, and form grid over the substrate
The embodiment of area and insulation layer and forms grid over the substrate with forming source region and drain region in the substrate in the prior art
Area is similar with the embodiment of insulation layer, and details are not described herein.
It is preferred that in step 402, using the method that metal silicide is made in MOS structure, in the lining
The embodiment that the metal silicide of transformation phase is formed on the grid region at bottom, source region and drain region may refer to the embodiment of the present invention
The embodiment of the method part of metal silicide is made in MOS structure.
In specific implementation, in step 403, gate electrode, the embodiment and the prior art of source electrode and drain electrode are formed
Middle formation gate electrode, the embodiment of source electrode and drain electrode are similar, and details are not described herein.
In specific implementation, when making MOS structure, formed gate electrode, the processing step after source electrode and drain electrode with
Processing step in the prior art after formation gate electrode, source electrode and drain electrode is similar, such as, form protective layer.
It is preferred that an embodiment of the present invention provides a kind of MOS structure, the MOS structure is by the making MOS structure
Method be made.
In implementation, the gate resistance and contact resistance of MOS structure are smaller, the semiconductor devices comprising the MOS structure
Power consumption is also smaller；In addition, the cost of manufacture of the MOS structure is smaller and makes complexity than relatively low.
Although preferred embodiments of the present invention have been described, but those skilled in the art once know basic creation
Property concept, then can make these embodiments other change and modification.So appended claims be intended to be construed to include it is excellent
Select embodiment and fall into all change and modification of the scope of the invention.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
God and scope.In this way, if these modifications and changes of the present invention belongs to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising including these modification and variations.
Claims (6)
- A kind of 1. method that metal silicide is made in MOS structure, it is characterised in that including：Step A, in the case where depositing temperature is the first temperature conditionss, sink on the substrate formed with grid region, source region, drain region and insulation layer One layer of metal of product；Make the metal on the grid region, source region and the drain region silicon with the grid region, source region and drain region respectively Material, which reacts, generates metal silicide；The value of wherein described first temperature is not less than the metal and the grid region, source The temperature value that the silicon materials in area and drain region react；Step B, first time quick thermal annealing process is carried out to the substrate；Step C, cleaning treatment is carried out to the substrate after first time quick thermal annealing process；Step D, to carrying out second of quick thermal annealing process by the cleaned substrate, the grid region, source are changed The phase of the metal silicide formed in area and drain region.
- 2. the method as described in claim 1, it is characterised in that first time quick thermal annealing process is being carried out to the substrate When, the gas in reaction chamber that the substrate is located at is inert gas.
- 3. the method as described in claim 1, it is characterised in that the value of first temperature be less than the metal with it is described absolutely The temperature value that the material in edge area reacts.
- 4. the method as described in claims 1 to 3 is any, it is characterised in that the metal is titanium.
- A kind of 5. production method of MOS structure, it is characterised in that including：Source region and drain region are formed in the substrate, and form grid region and insulation layer over the substrate；Using the method that metal silicide is made in MOS structure as described in Claims 1 to 4 is any, in the substrate The metal silicide of transformation phase is formed on grid region, source region and drain region；The oxide layer for covering the metal silicide and insulation layer is formed, patterned process, Yi Ji are carried out to the oxide layer Metal layer is formed in oxide layer after patterned process, to form gate electrode, source electrode and drain electrode respectively.
- 6. a kind of MOS structure, it is characterised in that the MOS structure is made as the method described in claim 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410010653.8A CN104779271B (en) | 2014-01-09 | 2014-01-09 | MOS structure and preparation method thereof and the method for making metal silicide |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410010653.8A CN104779271B (en) | 2014-01-09 | 2014-01-09 | MOS structure and preparation method thereof and the method for making metal silicide |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104779271A CN104779271A (en) | 2015-07-15 |
| CN104779271B true CN104779271B (en) | 2018-05-01 |
Family
ID=53620641
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410010653.8A Active CN104779271B (en) | 2014-01-09 | 2014-01-09 | MOS structure and preparation method thereof and the method for making metal silicide |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104779271B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107305847A (en) * | 2016-04-18 | 2017-10-31 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0651076B1 (en) * | 1993-10-29 | 1999-08-11 | International Business Machines Corporation | Method for lowering the phase transformation temperature of a metal silicide |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020151170A1 (en) * | 1996-06-04 | 2002-10-17 | Karen Maex | Method of forming polycrystalline CoSi2 salicide and products obtained thereof |
| KR100562310B1 (en) * | 2003-04-08 | 2006-03-22 | 동부아남반도체 주식회사 | Method for manufacturing silicide and semiconductor with the silicide |
-
2014
- 2014-01-09 CN CN201410010653.8A patent/CN104779271B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0651076B1 (en) * | 1993-10-29 | 1999-08-11 | International Business Machines Corporation | Method for lowering the phase transformation temperature of a metal silicide |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104779271A (en) | 2015-07-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI623023B (en) | Methods and apparatuses for manufacturing an interconnect structure | |
| CN102544098B (en) | MOS (Metal-Oxide-Semiconductor) transistor and forming method thereof | |
| TW201434085A (en) | Flocking cleaning process method for polysilicon wafer | |
| CN103578960B (en) | A kind of method preparing Ohmic contact in surface on back side of SiC substrate | |
| CN106683994A (en) | Manufacturing method of P-type silicon carbide ohmic contact | |
| CN104779271B (en) | MOS structure and preparation method thereof and the method for making metal silicide | |
| TWI389255B (en) | Method for fabricating integrated circuit structures | |
| CN103000579A (en) | Semiconductor device and preparation method thereof | |
| CN101447454A (en) | Method for adjusting grid work function of fully-silicified metal grid | |
| CN102856179A (en) | Method for forming semiconductor device | |
| CN102569089B (en) | Semiconductor device forming method | |
| WO2013146327A1 (en) | Manufacturing method for silicon carbide semiconductor element | |
| CN105244267B (en) | A kind of Ohmic contact method of silicon carbide PiN device | |
| CN102969276A (en) | Semiconductor device and manufacturing method thereof | |
| CN105448981A (en) | VDMOS device, drain electrode structure thereof, and manufacturing method | |
| CN103839807A (en) | Trench DMOS transistor manufacturing method and trench DMOS transistor | |
| CN101140871B (en) | Preparation method of metallic silicide in semiconductor device | |
| CN110942984B (en) | Preparation method of cobalt silicide film | |
| CN107968048A (en) | A kind of method for reducing semiconductor devices back metal contacts resistance | |
| TWI492285B (en) | Forming method of metal semiconductor compound | |
| CN104392915B (en) | Method for epitaxial growth of NiGe material by using NiTi alloy | |
| CN100466199C (en) | Method for cleaning residual metal | |
| CN104409362A (en) | Manufacturing method and device for thin film transistor and array substrate | |
| CN109935518A (en) | The forming method of semiconductor devices and its metal gates | |
| CN110473775A (en) | Improve the method for film removing |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| EXSB | Decision made by sipo to initiate substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220720 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District Cheng Fu Road 298, founder building, 5 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |