CN104778973B - A kind of external flash data memory interface application process based on CPLD - Google Patents
A kind of external flash data memory interface application process based on CPLD Download PDFInfo
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Abstract
The present invention discloses a kind of external flash data memory interface and its application process based on CPLD, more particularly to a kind of external flash data memory interface based on CPLD, including CPLD units and flash storage units, SIP interface, CPLD units and flash storage units are set in CPLD units, and communication is realized by SIP interface.Flash storage units include address storage area and data storage area, and address storage area is the sectors 0x7FF, and data storage area is the sector other than the sectors 0x7FF.The application process of the invention further relates to a kind of external flash data memory interface based on CPLD.The present invention not only correctly realizes data storage function, but also enormously simplifies program structure, saves resources of chip, effectively raises executing efficiency and reliability.
Description
Technical field
The invention belongs to digital integrated electronic circuit applied technical fields, and in particular to a kind of external flash numbers based on CPLD
According to memory interface application process.
Background technology
In digital display circuit, the access for external memory mostly uses processor and is operated.CPLD technologies are close
Year is increasingly mature and is used widely, and more and more substitutes ASIC (integrated circuit of special-purpose) and be used as Digital Logic
Control and data acquisition.CPLD devices have the advantage that internal delay time is short, execution speed is fast, efficient, institutional framework is flexible,
Whole programmed logic can use the form of hardware circuit to realize.
EPM1270 type CPLD chips are a kind of devices based on CMOS EEPROM, can by jtag interface online programming,
There are 1270 logic gates and 980 equivalent macroelements in piece, the logic time delay of pin to pin is 6.2ns, counter works frequency
Rate can reach 304MHz.FLASH storage chips are W25Q64BV, which is 64Mbit, is divided into 128 memory blocks, every piece
16 sectors, per sector page 16, every page of 256 bytes.It is sector that the chip minimum, which wipes unit, and most 256 can be written simultaneously
Byte supports standard Serial Peripheral interface SPI.
Invention content
The present invention provides a kind of external flash data memory interface and its application process based on CPLD, in CPLD chips
Cage structure SIP interface, without carrying out processor operation, CPLD chips are directly communicated with FLASH chip.
The technical solution adopted in the present invention is：A kind of external flash data memory interface based on CPLD, including CPLD
Unit and flash storage units set SIP interface in the CPLD units, and the CPLD units and flash storage units pass through
SIP interface realizes communication；
Flash storage units：Realization is filled with rear automatic cycle covering early time data；
SIP interface：Realize control Flash storage unit read-write operations.
Further, the flash storage units include address storage area and data storage area, and described address memory block is
The sectors 0x7FF, the data storage area are the sector other than the sectors 0x7FF.
A kind of external flash data memory interface application process based on CPLD, includes the following steps,
S0, original state：Initialization, judges whether there is write-protect, if nothing, S1 is jumped to after delay；
S1, judge busy states：If busy is low, S2 is jumped to according to program executive condition；
S2, target sector address is read：Sector address data in the addresses reading 7FF000/7FF001/7FF002, sector
Location adds 1, after jump to S3；
S3, erasing target sector：Send erasing instruction, after jump to S1；
S4, update sector address data：Address is updated simultaneously to store in 7FF000/7FF001/7FF002, after redirect
To S1；
S5, it waits for and latching：If data store enable signal (latch_set) and arrive, WP 1 jumps to S6；
S6, set write enabled：Write enabled WEL and set 1, after jump to S7；
S7, sector data is write：According to newer address date, sector instruction is write in transmission, and the data of 16 bytes are stored in
Sector jumps to S1 after the completion；
S8, register are reset：Status register reset, after jump to S1.
The present invention has the advantage that compared with prior art and effect：According to FLASH chip timing requirements, in CPLD chips
Upper construction SPI interface, to control FLASH chip reading and writing data.By the state that storage division of operations each time is different function, lead to
The running position that the logical relation between each state judges storing process is crossed, excessive repetitive operation is avoided.The present invention is not only correct
Realize data storage function, and enormously simplify program structure, save resources of chip, effectively raise program and hold
Line efficiency and reliability.
Description of the drawings
Fig. 1 is a kind of external flash data storage interface function module diagram based on CPLD of the present invention；
Fig. 2 is a kind of method flow diagram of the external flash data memory interface application process based on CPLD of the present invention.
Specific implementation mode
The following describes the present invention in detail with reference to the accompanying drawings and specific embodiments.
A kind of external flash data memory interface based on CPLD, structure is as shown in Figure 1, include 1 He of CPLD units
Flash storage units 2 set SIP interface 3 in the CPLD units 1, and CPLD units 1 and flash storage units 2 pass through SIP interface
3 realize communication.
Flash storage units 2：Realize the function of being filled with rear automatic cycle covering early time data.
SIP interface 3：Realize the function of 2 read-write operation of control Flash storage units.
The flash storage units 2 include address storage area and data storage area, and described address memory block is fanned for 0x7FF
Area, the sector first address of storage last time data storage.The data storage area is the sector other than the sectors 0x7FF, for storing
The process data of product operation.
Its working principle is that after the power is turned on, the data (i.e. the first address of last stored sector) of address storage area are first read, and
Judged.If reading the feature that data do not meet sector first address, then it is assumed that be to power on for the first time, address is stored sector at this time
Content update be 0 sector first address, such as read data fit sector first address feature, then more by the content of address storage area
The first address of new next sector for reading data.After the content for updating address storage area, further according to updated sector head
Address carries out data storage.After certain sector is filled with, after the content that address storage area must be updated, it is further continued for storing.
A kind of application process of the external flash data memory interface based on CPLD, method flow diagram as shown in Fig. 2,
Implement according to the following steps：
Step S0, original state：Initialization, judges whether there is write-protect, if nothing, step S1 is jumped to after delay.
Step S1, judge busy states：Instruction is sent in the failing edge of flash_clk, is read in the rising edge of flash_clk
Status register data is taken, if busy is low, step S2 is jumped to according to program executive condition.
Step S2, target sector address is read：Reading instruction is sent in the failing edge of flash_clk, in the rising of flash_clk
Along the sector address data read in 7FF000/7FF001/7FF002 addresses, sevtor address adds 1, after jump to step
S3。
Step S3, target sector is wiped：Send erasing instruction, after go to step S1.
Step S4, sector address data is updated：It updates address and stores in 7FF000/7FF001/7FF002, after
Go to step S1.
Step S5, it waits for and latching：If data store enable signal (latch_set) and arrive, WP 1, go to step S6.
Step S6, set is write enabled：Write enabled WEL and set 1, after go to step S7.
Step S7, sector data is write：According to newer address date, sector instruction is write in transmission, by the data of 16 bytes
It is stored in sector, go to step S1 after the completion.
Step S8, register is reset：Status register is reset, after go to step S1.
Above-described embodiment, only presently preferred embodiments of the present invention not are used for limiting the practical range of the present invention, thus it is all with
The equivalent variations that content described in the claims in the present invention is done should all be included within scope of the invention as claimed.
Claims (1)
1. a kind of external flash data memory interface application process based on CPLD, which is characterized in that include the following steps：
S0, original state：Initialization, judges whether there is write-protect, if nothing, S1 is jumped to after delay；
S1, judge busy states：If busy is low, S2 is jumped to according to program executive condition；
S2, target sector address is read：The sector address data in the addresses 7FF000/7FF001/7FF002 is read, sevtor address adds
1, after jump to S3；
S3, erasing target sector：Send erasing instruction, after jump to S1；
S4, update sector address data：Address is updated simultaneously to store in 7FF000/7FF001/7FF002, after jump to
S1；
S5, it waits for and latching：If data store enable signal（latch_set）It arrives, WP 1 jumps to S6；
S6, set write enabled：Write enabled WEL and set 1, after jump to S7；
S7, sector data is write：According to newer address date, sector instruction is write in transmission, and the data of 16 bytes are stored in sector,
S1 is jumped to after the completion；
S8, register are reset：Status register reset, after jump to S1.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1591377A (en) * | 2003-06-10 | 2005-03-09 | 阿尔特拉公司 | Apparatus and methods for communicating with programmable logic devices |
| US7088132B1 (en) * | 2004-03-25 | 2006-08-08 | Lattice Semiconductor Corporation | Configuring FPGAs and the like using one or more serial memory devices |
| CN1963814A (en) * | 2006-11-29 | 2007-05-16 | 珠海市泰德企业有限公司 | Managing method of data of memorizer |
| CN102169462A (en) * | 2011-04-27 | 2011-08-31 | 中国科学院光电技术研究所 | NAND Flash-based data recording method and recording controller |
-
2015
- 2015-04-20 CN CN201510187558.XA patent/CN104778973B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1591377A (en) * | 2003-06-10 | 2005-03-09 | 阿尔特拉公司 | Apparatus and methods for communicating with programmable logic devices |
| US7088132B1 (en) * | 2004-03-25 | 2006-08-08 | Lattice Semiconductor Corporation | Configuring FPGAs and the like using one or more serial memory devices |
| CN1963814A (en) * | 2006-11-29 | 2007-05-16 | 珠海市泰德企业有限公司 | Managing method of data of memorizer |
| CN102169462A (en) * | 2011-04-27 | 2011-08-31 | 中国科学院光电技术研究所 | NAND Flash-based data recording method and recording controller |
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