CN104778770A - Access-control host - Google Patents
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- CN104778770A CN104778770A CN201510167143.6A CN201510167143A CN104778770A CN 104778770 A CN104778770 A CN 104778770A CN 201510167143 A CN201510167143 A CN 201510167143A CN 104778770 A CN104778770 A CN 104778770A
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Abstract
The invention relates to the technical field of access control and particularly relates to an access-control host. The access-control host comprises an RS485 receiving and transmitting circuit, a voltage feedbacking and adjusting circuit, a signal inputting and processing circuit, an embedded type controller, a signal outputting and processing circuit and a storage circuit, wherein the RS485 receiving and transmitting circuit is used for communication with equipment; the voltage feedbacking and adjusting circuit is used for adjusting an input voltage and feedbacking an output voltage; the signal inputting and processing circuit is used for acquiring signal sources; the embedded type controller is used for processing signals transmitted by the signal inputting and processing circuit and communication data transmitted by the equipment; the signal outputting and processing circuit is used for receiving signals processed by the embedded type controller and processing the signals and transmitting the processed signals to the equipment; and the storage circuit is used for storing user data and system files. The access-control host has the advantages that the signals can be acquired without polarity limitation of the signal sources, both direct-current signals and alternative-current signals can be acquired, a multi-input acquisition interface is provided and the range of the voltage-value acquisition is wide.
Description
Technical field
The present invention relates to gate inhibition's technical field, particularly relate to a kind of gate inhibition's main frame.
Background technology
Gate control system is the modernization smart exit-entrance management control system integrating the multiple technologies such as computer technology, Micro-control Technology, smart card techniques, electromechanical integration technology, gate control system is (two-door by four, simple gate) two-way interconnection type controller, communication converter, read sensor, electric lock, button of going out, Men Ci, entrance guard management software and various cable accessory composition.Adopt noncontact Intelligent Card as identification.
Gate inhibition's main frame is ingredient important in gate control system.By RS485 bus, 99 combination in any can be formed a net control at most, utilize bus network can manage 99 × 4 doors.Each main frame can work independently, the impact that uncontrolled host computer (computing machine) shuts down, and when connecting host computer, data all upload to computer by management software, from storing All Activity record and data during off line.
The switch mode of all right collecting device of gate inhibition's main frame, and by gathered omicronff signal transmission to watch-dog.Current gate inhibition's main frame on the market also exists and gathers switching voltage value narrow range, and output terminal is few, and collection signal limits by the polarity of signal source.
This problem needs solution badly.
Summary of the invention
In view of above-mentioned the deficiencies in the prior art, the object of the present invention is to provide a kind of gate inhibition's main frame, it can not limit by the polarity of signal source by collection signal, can gather direct current signal, also can gather AC signal, and multi input acquisition interface is provided and gather range of voltage values wide.
In order to realize above-mentioned technical purpose, the technical solution used in the present invention is as follows:
A kind of gate inhibition's main frame, comprise for carrying out with equipment the RS485 transmission circuit that communicates, for regulating the Voltage Feedback regulating circuit of input voltage and fed-back output voltage, for the signal input processing circuit in collection signal source, for the treatment of the signal transmitted from signal input processing circuit, the embedded controller of communication data that transmits from equipment, for receiving the signal after processing from described embedded controller and carrying out described signal to process and send to the signal output processing circuit of equipment, for the memory circuit of store user data and system file; Described RS485 transmission circuit is connected with embedded controller, described Voltage Feedback regulating circuit is connected with embedded controller, signal input processing circuit, signal output processing circuit respectively, and described embedded controller is connected with signal input processing circuit, signal output processing circuit respectively.
Further, described RS485 transmission circuit specifically comprises RS485 transceiver, the first resistance, the second resistance, the 3rd resistance, the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance, the 8th resistance, the first transient supression diode, the second transient supression diode, the 3rd transient supression diode, the first triode, the second triode, the first light emitting diode, the second light emitting diode, the first fuse box, the second fuse and the first voltage;
Described RS485 transceiver comprises the first pin, the second pin, the 3rd pin, the 4th pin, the 5th pin, the 6th pin, the 7th pin and the 8th pin;
Described first pin is connected to the first voltage, one end of described second pin respectively with the first resistance, one end of second resistance, one end of first transient supression diode, one end of second transient supression diode, one end of first fuse connects, and one end of described first resistance is connected with one end of the second resistance, one end of described first transient supression diode is connected with one end of the second transient supression diode, the other end of described first resistance is connected to the first voltage, the other end of the first transient supression diode is connected to ground, the other end of the first fuse connects external power source,
The other end of described 3rd pin respectively with the second resistance, one end of the 3rd resistance, the other end of the second transient supression diode, one end of the 3rd transient supression diode, one end of the second fuse are connected, the other end of described second resistance is connected with one end of the 3rd resistance, the other end of the second transient supression diode is connected with one end of the 3rd transient supression diode, the other end of described 3rd resistance and the other end of the 3rd transient supression diode ground connection respectively, the other end of the second fuse connects external power source;
Described 4th pin, the 5th pin, the 6th pin, the 7th pin are connected with described embedded controller respectively; The emitter of described first triode is connected to the first voltage, and base stage is connected to the 5th pin by the 5th resistance, and collector is connected to the positive pole of the first light emitting diode by the 6th resistance, and the negative pole of the first light emitting diode is connected to ground; 6th pin is connected to ground by the 4th resistance; The emitter of described second triode is connected to the first voltage, and base stage is connected to the 7th pin by the 7th resistance, and collector is connected to the positive pole of the second light emitting diode by the 8th resistance, and the negative pole of the second light emitting diode is connected to ground; 8th pin is directly connected to ground.
Further, described gate inhibition's main frame is provided with two groups of RS485 transmission circuits.
Further, described RS485 transceiver employing model is the RS485 transceiver of SP3485 model.
Further, described Voltage Feedback regulating circuit comprises voltage regulator, the 4th diode, the 5th diode, the 6th diode, the first polar capacitor, the second polar capacitor, the 3rd electric capacity, the 4th electric capacity, the 5th polar capacitor, the first inductance, the 9th resistance, the tenth resistance, the 11 resistance, the second voltage and tertiary voltage; Described voltage regulator comprises the 9th pin, the tenth pin and the 11 pin;
Described Voltage Feedback regulating circuit is connected with a socket, the positive pole of described socket the respectively with four diode, the positive pole of the 5th diode are connected, negative pole the respectively with nine pin of described 4th diode, the positive pole of the second polar capacitor are connected, the negative pole of described second polar capacitor is connected to ground, the negative pole of the 5th diode connects the positive pole of the second voltage, the first polar capacitor respectively, the negative pole of described first polar capacitor is connected to ground, and positive pole is connected with the second voltage;
One end of described tenth pin the respectively with nine resistance, the negative pole of the 6th diode, the first inductance, one end of the 4th electric capacity, the positive pole of the 5th polar capacitor are connected; The other end of described 9th resistance is connected to ground by the 3rd electric capacity; The positive pole of described 6th diode is connected to ground; The other end of the 4th electric capacity is connected to ground, and the negative pole of described 5th polar capacitor is connected to ground, and positive pole is connected with tertiary voltage;
Described one end of 11 pin the respectively with ten resistance, one end of the 11 resistance are connected, and the other end of the tenth resistance is connected to ground, and the other end of the 11 resistance is connected with tertiary voltage.
Further, described socket is phoenix socket, and described voltage regulator adopts model to be TD1509PR.
Further, described signal input processing circuit comprises socket, 3rd light emitting diode, 4th light emitting diode, 5th light emitting diode, 12 resistance, 13 resistance, 14 resistance, 15 resistance, 16 resistance, 17 resistance, 18 resistance, 19 resistance, 20 resistance, 21 resistance, 22 resistance, 23 resistance, first crosspointer wire jumper, second crosspointer wire jumper, 3rd crosspointer wire jumper, first photoelectrical coupler, second photoelectrical coupler, 3rd photoelectrical coupler, 6th electric capacity, 7th electric capacity, 8th electric capacity and the first voltage, described socket comprises the 12 pin, the 13 pin, the 14 pin and the 15 pin, described first photoelectrical coupler comprises first input end, the second input end, the first output terminal and the second output terminal, described second photoelectrical coupler comprises the 3rd input end, four-input terminal, the 3rd output terminal and the 4th output terminal, and described 3rd photoelectrical coupler comprises the 5th input end, the 6th input end, the 5th output terminal and the 6th output terminal,
Described 12 pin is connected with the 3rd light emitting diode positive pole, the negative pole of described 3rd light emitting diode is connected with one end of the 12 resistance, the other end of described 12 resistance is connected with one end of the 15 resistance, the other end of described 15 resistance is connected with the first input end of the first photoelectrical coupler, described 15 pin is connected with the second input end of the first photoelectrical coupler, wherein, described first crosspointer wire jumper and the 12 resistor coupled in parallel; First output terminal of described first photoelectrical coupler is connected with one end of the 18 resistance, one end of the 19 resistance respectively, the other end of described 18 resistance is connected to the first voltage, the other end of the 19 resistance is connected to embedded controller, is also connected to ground by the 6th electric capacity;
Described 13 pin is connected with the 4th light emitting diode positive pole, the negative pole of described 4th light emitting diode is connected with one end of the 13 resistance, the other end of described 13 resistance is connected with one end of the 16 resistance, the other end of described 16 resistance is connected with the 3rd input end of the second photoelectrical coupler, described 15 pin is connected with the four-input terminal of the second photoelectrical coupler, wherein, described second crosspointer wire jumper and the 13 resistor coupled in parallel; 3rd output terminal of described second photoelectrical coupler is connected with one end of the 20 resistance, one end of the 21 resistance respectively, the other end of described 20 resistance is connected to the first voltage, the other end of the 21 resistance is connected to embedded controller, is also connected to ground by the 7th electric capacity;
Described 14 pin is connected with the 5th light emitting diode positive pole, the negative pole of described 5th light emitting diode is connected with one end of the 14 resistance, the other end of described 14 resistance is connected with one end of the 17 resistance, the other end of described 17 resistance is connected with the 5th input end of the 3rd photoelectrical coupler, described 15 pin is connected with the 6th input end of the 3rd photoelectrical coupler, wherein, described 3rd crosspointer wire jumper and the 14 resistor coupled in parallel; 5th output terminal of described 3rd photoelectrical coupler is connected with one end of the 22 resistance, one end of the 23 resistance respectively, the other end of described 22 resistance is connected to the first voltage, the other end of the 23 resistance is connected to embedded controller, is also connected to ground by the 8th electric capacity.
Further, described gate inhibition's main frame is provided with three groups of signal input processing circuits.
Further, described signal output processing circuit comprises relay, the 7th diode, the 3rd triode and the 24 resistance;
Described signal output processing circuit is connected with embedded controller, more specifically: the base stage of described 3rd triode is connected with embedded controller, emitter is held by the 24 resistance with being connected to, the positive pole of collector the respectively with seven diode, one end of relay are connected, and negative pole respectively with the second voltage of described 7th diode, the other end of relay are connected.
Further, described gate inhibition's main frame is provided with six groups of signal output processing circuits.
Beneficial effect of the present invention:
By arranging RS485 transmission circuit, collection signal can be transferred to watch-dog by the present invention, and meanwhile, watch-dog controls work of the present invention by RS485 transmission circuit;
By arranging Voltage Feedback regulating circuit, for the whole device of the present invention provides stable working power, and can fed-back output voltage, make whole device reliably working;
Signal input processing circuit adopts Phototube Coupling, collection signal of the present invention is not limited by signal source polarity, can gather direct supply, also can gather AC power;
Input voltage range double range designs, and can detect 8 ~ 40V voltage signal, also can measure the voltage signal of 180 ~ 500V.
Accompanying drawing explanation
Fig. 1 is circuit frame schematic diagram of the present invention.
Fig. 2 and Fig. 3 is RS485 transmission circuit figure of the present invention.
Fig. 4 and Fig. 5 is Voltage Feedback regulating circuit figure of the present invention.
Fig. 6 is signal input processing circuit figure of the present invention.
Fig. 7 is signal output processing circuit figure of the present invention.
Embodiment
The invention provides a kind of gate inhibition's main frame, for making object of the present invention, technical scheme and effect clearly, clearly, developing simultaneously referring to accompanying drawing, the present invention is described in more detail for embodiment.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
As shown in Figure 1, gate inhibition's main frame of the present invention comprises for carrying out with equipment the RS485 transmission circuit that communicates, for regulating the Voltage Feedback regulating circuit of input voltage and fed-back output voltage, for the signal input processing circuit in collection signal source, for the treatment of the signal transmitted from signal input processing circuit, from the embedded controller of the communication data that equipment transmits, for receiving the signal after processing from described embedded controller and carrying out described signal to process and send to the signal output processing circuit of equipment, for the memory circuit of store user data and system file, described RS485 transmission circuit is connected with embedded controller, described Voltage Feedback regulating circuit is connected with embedded controller 100, signal input processing circuit, signal output processing circuit respectively, and described embedded controller is connected with signal input processing circuit, signal output processing circuit respectively.Embedded controller of the present invention adopts model to be STM32F103C8T6's, the embedded controller of this model has three groups of signal transmission interfaces and receiving interface, i.e. signal first transmission interface, signal second transmission interface, signal the 3rd transmission interface, signal first receiving interface, signal second receiving interface and signal the 3rd receiving interface.
As shown in Figure 2, described RS485 transmission circuit specifically comprises RS485 transceiver 101, first resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6, the 7th resistance R7, the 8th resistance R8, the first transient supression diode D1, the second transient supression diode D2, the 3rd transient supression diode D3, the first triode Q1, the second triode Q2, the first light emitting diode K1, the second light emitting diode K2, the first fuse box F1, the second fuse F2 and the first voltage 110.As preferred value, the resistance value of the first resistance R1 of the present invention to the 5th resistance R5 is 10000 ohm, and the 6th resistance R6 is 330 ohm, and the 7th resistance R7 is 10000 ohm, and the 8th resistance R8 is 330 ohm.
Described RS485 transceiver 101 comprises the first pin 1, second pin 2, the 3rd pin 3, the 4th pin 4, the 5th pin 5, the 6th pin 6, the 7th pin 7 and the 8th pin 8.
Described first pin 1 is connected to the first voltage 110, described first voltage is+3.3V, one end of described second pin 2 respectively with the first resistance R1, one end of second resistance R2, one end of first transient supression diode D1, one end of second transient supression diode D2, one end of first fuse F1 connects, and one end of described first resistance R1 is connected with one end of the second resistance R2, one end of described first transient supression diode D1 is connected with one end of the second transient supression diode D2, the other end of described first resistance R1 is connected to the first voltage 110, the other end of the first transient supression diode D1 is connected to ground, the other end of the first fuse F1 connects external power source,
The other end of described 3rd pin 3 respectively with the second resistance R2, one end of the 3rd resistance R3, the other end of the second transient supression diode D2, one end of the 3rd transient supression diode D3, one end of the second fuse F2 are connected, the other end of described second resistance R2 is connected with one end of the 3rd resistance R3, the other end of the second transient supression diode D2 is connected with one end of the 3rd transient supression diode D3, the other end of described 3rd resistance R3 and the other end of the 3rd transient supression diode D3 ground connection respectively, the other end of the second fuse F2 connects external power source;
Described 4th pin 4, the 5th pin 5, the 6th pin 6, the 7th pin 7 are connected with described embedded controller 100 respectively; The emitter of described first triode Q1 is connected to the first voltage, and base stage is connected to the 5th pin by the 5th resistance R5, and collector is connected to the positive pole of the first light emitting diode K1 by the 6th resistance R6, and the negative pole of the first light emitting diode K1 is connected to ground; 6th pin 6 is connected to ground by the 4th resistance R4; The emitter of described second triode Q2 is connected to+3.3V, and base stage is connected to the 7th pin 7 by the 7th resistance R7, and collector is connected to the positive pole of the second light emitting diode K2 by the 8th resistance R8, and the negative pole of the second light emitting diode K2 is connected to ground; 8th pin 8 is directly connected to ground.Describe RS485 transmission circuit in order to simple, clear, in RS485 transmission circuit of the present invention, the first voltage 110 is+3.3V, and the power supply of the first voltage provided by following Voltage Feedback regulating circuit.And circuit as shown in Figure 3 is also set in the first voltage part, the first voltage 110 connects ground by electric capacity C100, and the preferred value of C100 is 104P, i.e. 0.1 μ P.
What deserves to be explained is, gate inhibition's main frame of the present invention is provided with two groups of RS485 transmission circuits, wherein, the circuit design often organizing RS485 transmission circuit is the same with framework, in order to simply clearly demonstrate, invention has been described wherein one group of RS485 transmission circuit and also announcing wherein one group of RS485 transmission circuit design drawing.One group of RS485 transmission circuit is connected with signal first receiving interface with signal first transmission interface of embedded controller, and another group RS485 transmission circuit is connected with signal second receiving interface with signal second transmission interface of embedded controller.RS485 transceiver 101 of the present invention adopts model to be the RS485 transceiver of SP3485 model.
As shown in Figure 4, Voltage Feedback regulating circuit comprises voltage regulator 101, the 4th diode D4, the 5th diode D5, the 6th diode D6, the first polar capacitor C1, the second polar capacitor C2, the 3rd electric capacity C3, the 4th electric capacity C4, the 5th polar capacitor C5, the 9th resistance R9, the tenth resistance R10, the 11 resistance R11, the first inductance L 1, second voltage 111 and tertiary voltage 112; Described voltage regulator 102 comprises the 9th pin 9, the tenth pin the 10 and the 11 pin 11; Described voltage regulator adopts model to be TD1509PR.
Described Voltage Feedback regulating circuit is connected with a socket 103, and wherein, described socket is 4 pin phoenix sockets.The described positive pole of socket 103 the respectively with four diode D4, the positive pole of the 5th diode D5 are connected, the positive pole of negative pole the respectively with nine pin 9, the second polar capacitor C2 of described 4th diode D4 is connected, the negative pole of described second polar capacitor C2 is connected to ground, the negative pole of the 5th diode D5 connects the positive pole of the second voltage+12V and the first polar capacitor C1 respectively, and the negative pole of described first polar capacitor C1 is connected to ground;
One end of described tenth pin 10 the respectively with nine resistance R9, the negative pole of the 6th diode D6, the first inductance L 1, one end of the 4th electric capacity C4, the positive pole of the 5th polar capacitor C5 are connected; The other end of described 9th resistance R9 is connected to ground by the 3rd electric capacity C3; The positive pole of described 6th diode D6 is connected to ground; The other end of the 4th electric capacity C4 is connected to ground, and the negative pole of described 5th polar capacitor C5 is connected to ground.Described one end of 11 pin 11 the respectively with ten resistance R10, one end of the 11 resistance R11 are connected, and the other end of the tenth resistance R10 is connected to ground, and the other end of the 11 resistance R11 is connected with tertiary voltage 112.In order to simple, clear, Voltage Feedback regulating circuit is described, in Voltage Feedback regulating circuit of the present invention, all second voltage is+12V, tertiary voltage is+3.3V, and circuit as shown in Figure 5 is also set in tertiary voltage part, one end of tertiary voltage is held by resistance R100, light emitting diode D100 successively with being connected to.
As preferred value, the resistance value of R100 is 330 ohm, first polar capacitor C1 and the second polar capacitor C2 is 100 μ f/50V, 3rd electric capacity C3 is 330P, and the 4th electric capacity C4 is 104P, and the 5th electric capacity C5 is 330 μ f/10V, 9th resistance R9 is 10R, tenth resistance R10 is 1KF, and the 11 resistance R11 is 1.67KF, and the first inductance L 1 is 220 μ H.
As shown in figure 6, signal input processing circuit comprises socket 104, 3rd light emitting diode K3, 4th light emitting diode K4, 5th light emitting diode K5, 12 resistance R12, 13 resistance R13, 14 resistance R14, 15 resistance R15, 16 resistance R16, 17 resistance R17, 18 resistance R18, 19 resistance R19, 20 resistance R20, 21 R21 resistance, 22 R22 resistance, 23 R23 resistance, first crosspointer wire jumper S1, second crosspointer wire jumper S2, 3rd crosspointer wire jumper S3, first photoelectrical coupler G1, second photoelectrical coupler G2, 3rd photoelectrical coupler G3, 6th electric capacity C6, 7th electric capacity C7, 8th electric capacity C8 and the first voltage 110, described socket 104 comprises the 12 pin the 12, the 13 pin the 13, the 14 pin the 14 and the 15 pin 15, described first photoelectrical coupler G1 comprises first input end A1, the second input end A2, the first output terminal B1 and the second output terminal B2, described second photoelectrical coupler G2 comprises the 3rd input end A3, four-input terminal A4, the 3rd output terminal B3 and the 4th output terminal B4, and described 3rd photoelectrical coupler G3 comprises the 5th input end A5, the 6th input end A6, the 5th output terminal B5 and the 6th output terminal B6.
Described 12 pin 12 is connected with the 3rd light emitting diode K3 positive pole, the negative pole of described 3rd light emitting diode K3 is connected with one end of the 12 resistance R12, the other end of described 12 resistance R12 is connected with one end of the 15 resistance R15, the other end of described 15 resistance R15 is connected with the first input end A1 of the first photoelectrical coupler G1, described 15 pin 15 is connected with the second input end A2 of the first photoelectrical coupler G1, wherein, described first crosspointer wire jumper S1 and the 12 resistance R12 is in parallel; The first output terminal B1 of described first photoelectrical coupler G1 is connected with one end of the 18 resistance R18, one end of the 19 resistance R19 respectively, the other end of described 18 resistance R18 is connected to the first voltage, the other end of the 19 resistance R19 is connected to embedded controller 100, is also connected to ground by the 6th electric capacity C6;
Described 13 pin 13 is connected with the 4th light emitting diode K4 positive pole, the negative pole of described 4th light emitting diode K4 is connected with one end of the 13 resistance R13, the other end of described 13 resistance R13 is connected with one end of the 16 resistance R16, the other end of described 16 resistance R16 is connected with the 3rd input end A3 of the second photoelectrical coupler G2, described 15 pin 15 is connected with the four-input terminal A4 of the second photoelectrical coupler G2, wherein, described second crosspointer wire jumper S2 and the 13 resistance R13 is in parallel; The 3rd output terminal B3 of described second photoelectrical coupler G2 is connected with one end of the 20 resistance R20, one end of the 21 resistance R21 respectively, the other end of described 20 resistance R20 is connected to the first voltage 110, the other end of the 21 resistance R21 is connected to embedded controller 100, is also connected to ground by the 7th electric capacity C7;
Described 14 pin 14 is connected with the 5th light emitting diode K5 positive pole, the negative pole of described 5th light emitting diode K5 is connected with one end of the 14 resistance R14, the other end of described 14 resistance R14 is connected with one end of the 17 resistance R17, the other end of described 17 resistance R17 is connected with the 5th input end A5 of the 3rd photoelectrical coupler G3, described 15 pin 15 is connected with the 6th input end A6 of the 3rd photoelectrical coupler G3, wherein, described 3rd crosspointer wire jumper S3 and the 14 resistance R14 is in parallel; The 5th output terminal B5 of described 3rd photoelectrical coupler G3 is connected with one end of the 22 resistance R22, one end of the 23 resistance R23 respectively, the other end of described 22 resistance R22 is connected to the first voltage 110, the other end of the 23 resistance R23 is connected to embedded controller 100, is also connected to ground by the 8th electric capacity C8.
What deserves to be explained is, gate inhibition's main frame of the present invention is provided with three groups of signal input processing circuits, wherein, often organize the circuit design of signal input processing circuit, components and parts use the same with framework, in order to simply clearly demonstrate, invention has been described wherein one group of signal input processing circuit announce one of them signal input processing circuit design drawing.And the present invention, by described three groups of signal input processing circuits, is respectively ten tunnels, each group shares a public terminal.
As shown in Figure 7, signal output processing circuit comprises relay 105, the 7th diode D7, the 3rd triode Q3, the 24 resistance R24 and the second voltage 111.Wherein, described relay 105 adopts JQ-SH-112D model;
Described signal output processing circuit is connected with embedded controller 100, more specifically: the base stage of described 3rd triode Q3 is connected with embedded controller 100, emitter is held by the 24 resistance R24 with being connected to, the positive pole of collector the respectively with seven diode D7, one end of relay 105 are connected, and negative pole respectively with the second voltage 111 of described 7th diode D7, the other end of relay 105 are connected.The output terminal OUT of relay 105 connects watch-dog 106.
What deserves to be explained is, gate inhibition's main frame of the present invention is provided with six groups of signal output processing circuits, wherein, often organize the circuit design of signal output processing circuit, components and parts use the same with framework, in order to simply clearly demonstrate, invention has been described wherein one group of signal output processing circuit and also announcing wherein one group of signal output processing circuit design drawing.Therefore the present invention's six groups of channel signal output ports.
Should be understood that, application of the present invention is not limited to above-mentioned citing, for those of ordinary skills, can be improved according to the above description or convert, and all these improve and convert the protection domain that all should belong to claims of the present invention.
Claims (10)
1. gate inhibition's main frame, it is characterized in that: comprise for carrying out with equipment the RS485 transmission circuit that communicates, for regulating the Voltage Feedback regulating circuit of input voltage and fed-back output voltage, for the signal input processing circuit in collection signal source, for the treatment of the signal transmitted from signal input processing circuit, from the embedded controller of the communication data that equipment transmits, for receiving the signal after processing from described embedded controller and carrying out described signal to process and send to the signal output processing circuit of equipment, for the memory circuit of store user data and system file, described RS485 transmission circuit is connected with embedded controller, described Voltage Feedback regulating circuit is connected with embedded controller, signal input processing circuit, signal output processing circuit respectively, and described embedded controller is connected with signal input processing circuit, signal output processing circuit respectively.
2. a kind of gate inhibition's main frame according to claim 1, is characterized in that: described RS485 transmission circuit specifically comprises RS485 transceiver, the first resistance, the second resistance, the 3rd resistance, the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance, the 8th resistance, the first transient supression diode, the second transient supression diode, the 3rd transient supression diode, the first triode, the second triode, the first light emitting diode, the second light emitting diode, the first fuse box, the second fuse and the first voltage;
Described RS485 transceiver comprises the first pin, the second pin, the 3rd pin, the 4th pin, the 5th pin, the 6th pin, the 7th pin and the 8th pin;
Described first pin is connected to the first voltage, one end of described second pin respectively with the first resistance, one end of second resistance, one end of first transient supression diode, one end of second transient supression diode, one end of first fuse connects, and one end of described first resistance is connected with one end of the second resistance, one end of described first transient supression diode is connected with one end of the second transient supression diode, the other end of described first resistance is connected to the first voltage, the other end of the first transient supression diode is connected to ground, the other end of the first fuse connects external power source,
The other end of described 3rd pin respectively with the second resistance, one end of the 3rd resistance, the other end of the second transient supression diode, one end of the 3rd transient supression diode, one end of the second fuse are connected, the other end of described second resistance is connected with one end of the 3rd resistance, the other end of the second transient supression diode is connected with one end of the 3rd transient supression diode, the other end of described 3rd resistance and the other end of the 3rd transient supression diode ground connection respectively, the other end of the second fuse connects external power source;
Described 4th pin, the 5th pin, the 6th pin, the 7th pin are connected with described embedded controller respectively; The emitter of described first triode is connected to the first voltage, and base stage is connected to the 5th pin by the 5th resistance, and collector is connected to the positive pole of the first light emitting diode by the 6th resistance, and the negative pole of the first light emitting diode is connected to ground; 6th pin is connected to ground by the 4th resistance; The emitter of described second triode is connected to the first voltage, and base stage is connected to the 7th pin by the 7th resistance, and collector is connected to the positive pole of the second light emitting diode by the 8th resistance, and the negative pole of the second light emitting diode is connected to ground; 8th pin is directly connected to ground.
3. a kind of gate inhibition's main frame according to claim 1 and 2, is characterized in that: described gate inhibition's main frame is provided with two groups of RS485 transmission circuits.
4. a kind of gate inhibition's main frame according to claim 2, is characterized in that: described RS485 transceiver employing model is the RS485 transceiver of SP3485 model.
5. a kind of gate inhibition's main frame according to claim 1, is characterized in that: described Voltage Feedback regulating circuit comprises voltage regulator, the 4th diode, the 5th diode, the 6th diode, the first polar capacitor, the second polar capacitor, the 3rd electric capacity, the 4th electric capacity, the 5th polar capacitor, the first inductance, the 9th resistance, the tenth resistance, the 11 resistance, the second voltage and tertiary voltage; Described voltage regulator comprises the 9th pin, the tenth pin and the 11 pin;
Described Voltage Feedback regulating circuit is connected with a socket, the positive pole of described socket the respectively with four diode, the positive pole of the 5th diode are connected, negative pole the respectively with nine pin of described 4th diode, the positive pole of the second polar capacitor are connected, the negative pole of described second polar capacitor is connected to ground, the negative pole of the 5th diode connects the positive pole of the second voltage, the first polar capacitor respectively, the negative pole of described first polar capacitor is connected to ground, and positive pole is connected with the second voltage;
One end of described tenth pin the respectively with nine resistance, the negative pole of the 6th diode, the first inductance, one end of the 4th electric capacity, the positive pole of the 5th polar capacitor are connected; The other end of described 9th resistance is connected to ground by the 3rd electric capacity; The positive pole of described 6th diode is connected to ground; The other end of the 4th electric capacity is connected to ground, and the negative pole of described 5th polar capacitor is connected to ground, and positive pole is connected with tertiary voltage;
Described one end of 11 pin the respectively with ten resistance, one end of the 11 resistance are connected, and the other end of the tenth resistance is connected to ground, and the other end of the 11 resistance is connected with tertiary voltage.
6. a kind of gate inhibition's main frame according to claim 3, is characterized in that: described socket is phoenix socket, and described voltage regulator adopts model to be TD1509PR.
7. a kind of gate inhibition's main frame according to claim 1, it is characterized in that: described signal input processing circuit comprises socket, 3rd light emitting diode, 4th light emitting diode, 5th light emitting diode, 12 resistance, 13 resistance, 14 resistance, 15 resistance, 16 resistance, 17 resistance, 18 resistance, 19 resistance, 20 resistance, 21 resistance, 22 resistance, 23 resistance, first crosspointer wire jumper, second crosspointer wire jumper, 3rd crosspointer wire jumper, first photoelectrical coupler, second photoelectrical coupler, 3rd photoelectrical coupler, 6th electric capacity, 7th electric capacity and the 8th electric capacity, described socket comprises the 12 pin, the 13 pin, the 14 pin and the 15 pin, described first photoelectrical coupler comprises first input end, the second input end, the first output terminal and the second output terminal, described second photoelectrical coupler comprises the 3rd input end, four-input terminal, the 3rd output terminal and the 4th output terminal, and described 3rd photoelectrical coupler comprises the 5th input end, the 6th input end, the 5th output terminal and the 6th output terminal,
Described 12 pin is connected with the 3rd light emitting diode positive pole, the negative pole of described 3rd light emitting diode is connected with one end of the 12 resistance, the other end of described 12 resistance is connected with one end of the 15 resistance, the other end of described 15 resistance is connected with the first input end of the first photoelectrical coupler, described 15 pin is connected with the second input end of the first photoelectrical coupler, wherein, described first crosspointer wire jumper and the 12 resistor coupled in parallel; First output terminal of described first photoelectrical coupler is connected with one end of the 18 resistance, one end of the 19 resistance respectively, the other end of described 18 resistance is connected to the first voltage, the other end of the 19 resistance is connected to embedded controller, is also connected to ground by the 6th electric capacity;
Described 13 pin is connected with the 4th light emitting diode positive pole, the negative pole of described 4th light emitting diode is connected with one end of the 13 resistance, the other end of described 13 resistance is connected with one end of the 16 resistance, the other end of described 16 resistance is connected with the 3rd input end of the second photoelectrical coupler, described 15 pin is connected with the four-input terminal of the second photoelectrical coupler, wherein, described second crosspointer wire jumper and the 13 resistor coupled in parallel; 3rd output terminal of described second photoelectrical coupler is connected with one end of the 20 resistance, one end of the 21 resistance respectively, the other end of described 20 resistance is connected to the first voltage, the other end of the 21 resistance is connected to embedded controller, is also connected to ground by the 7th electric capacity;
Described 14 pin is connected with the 5th light emitting diode positive pole, the negative pole of described 5th light emitting diode is connected with one end of the 14 resistance, the other end of described 14 resistance is connected with one end of the 17 resistance, the other end of described 17 resistance is connected with the 5th input end of the 3rd photoelectrical coupler, described 15 pin is connected with the 6th input end of the 3rd photoelectrical coupler, wherein, described 3rd crosspointer wire jumper and the 14 resistor coupled in parallel; 5th output terminal of described 3rd photoelectrical coupler is connected with one end of the 22 resistance, one end of the 23 resistance respectively, the other end of described 22 resistance is connected to the first voltage, the other end of the 23 resistance is connected to embedded controller, is also connected to ground by the 8th electric capacity.
8. a kind of gate inhibition's main frame according to claim 1 or 7, is characterized in that: described gate inhibition's main frame is provided with three groups of signal input processing circuits.
9. a kind of gate inhibition's main frame according to claim 1, is characterized in that: described signal output processing circuit comprises relay, the 7th diode, the 3rd triode, the 24 resistance and the second voltage;
Described signal output processing circuit is connected with embedded controller, more specifically: the base stage of described 3rd triode is connected with embedded controller, emitter is held by the 24 resistance with being connected to, the positive pole of collector the respectively with seven diode, one end of relay are connected, and negative pole respectively with the second voltage of described 7th diode, the other end of relay are connected.
10. a kind of gate inhibition's main frame according to claim 1 or 9, is characterized in that: described gate inhibition's main frame is provided with six groups of signal output processing circuits.
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| CN201510167143.6A CN104778770A (en) | 2015-04-10 | 2015-04-10 | Access-control host |
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| CN1753407A (en) * | 2005-10-20 | 2006-03-29 | 上海电器科学研究所（集团）有限公司 | Communication adapter |
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