CN104766887A - Electronic circuits including MOSFET and dual-gate JFET - Google Patents

Electronic circuits including MOSFET and dual-gate JFET Download PDF

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Publication number
CN104766887A
CN104766887A CN201510002272.XA CN201510002272A CN104766887A CN 104766887 A CN104766887 A CN 104766887A CN 201510002272 A CN201510002272 A CN 201510002272A CN 104766887 A CN104766887 A CN 104766887A
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grid
trap
drain electrode
jfet
source electrode
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CN201510002272.XA
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CN104766887B (en
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D·A·玛斯利亚
A·G·布拉卡尔
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Somos Semiconductor Co
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Acco Semiconductor Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H01L29/7832—Field effect transistors with field effect produced by an insulated gate with multiple gate structure the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

Abstract

Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.

Description

Comprise the electronic circuit of MOSFET and bigrid JFET
the cross reference of related application
The application is the U.S. Patent application No.13/803 submitted on March 13rd, 2013, the continuation-in-part application of 792, U.S. Patent application No.13/803, 792 is the U.S. Patent application No.13/433 submitted on April 10th, 2012, 611 (is now the U.S. Patent No. 8 of bulletin on March 19th, 2013, 400, 222) continuation-in-part application, U.S. Patent application No.13/433, 611 is the U.S. Patent application No.13/107 submitted on May 13rd, 2011, 411 (is now the U.S. Patent No. 8 of bulletin on May 15th, 2012, 179, 197) continuation application case, U.S. Patent application No.13/107, 411 is the U.S. Patent application No.12/686 submitted on January 13rd, 2010, 573 (is now the U.S. Patent No. 7 of bulletin on June 28th, 2011, 969, 243) divisional application, above-mentioned all name of patent application are " Electronic Circuits including a MOSFET and a Dual-Gate JFET ", U.S. Patent application No.12/686, the U.S. Provisional Patent Application No.61/171 that 573 names requiring on April 22nd, 2009 to submit to are called " Electronic Circuits including a MOSFET and a Dual-Gate JFET andhaving a High Breakdown Voltage ", the rights and interests of 689, each above-mentioned patent application is incorporated to herein by reference at this.The U.S. Provisional Patent Application No.61/923 that the name that the application also requires on January 3rd, 2014 to submit to is called " Electronic Circuitsincluding a MOSFET and a Dual-Gate JFET ", the rights and interests of 578, this application is also incorporated to herein by reference.The application is also called the U.S. Patent application No.12/070 of " High Breakdown Voltage Double-gateSemiconductor Device " with the name submitted on February 13rd, 2008,019 (is now the U.S. Patent No. 7 of bulletin on January 4th, 2011,863,645) relevant, be also incorporated to by reference herein at this.
Technical field
Present invention relates in general to semiconductor device, and relate more specifically to the semiconductor device being configured for power application.
Background technology
Complementary metal oxide semiconductors (CMOS) (CMOS) device being designed for radio frequency (RF) power application has traditionally required trading off between the RF performance improved and higher puncture voltage.Such as, the RF performance of cmos device can be improved by reducing grid physical dimension (such as, by using short channel length).But less grid physical dimension reduces the puncture voltage of cmos device.Because the puncture voltage reduced is limited in the obtainable voltage swing in output of the cmos device in amplifier configuration, so this cmos device use in power application is less.
Process in the method for break-down voltage problem a kind of, cmos device can be designed to the larger current drives with lower voltage swing.But larger current drives may need the width of the transistor made in cmos device comparatively large, therefore presents unexpected capacity load to drive circuit.
The method of another kind of process break-down voltage problem uses Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor.Ldmos transistor has the drift region between active area and drain electrode.Drift region is lightly doped and experiences maximum voltage swing.Because the doping content in drift region requires restriction by puncture voltage, so the higher puncture voltage of LDMOS device sacrifice and bring the higher all-in resistance (being called on-state resistance) of the drain current flowed between drain electrode and source terminal.
The method of another kind of process break-down voltage problem uses has device that is thicker and the more substrate of high resistivity.These devices can provide more high-tension performance, but also introduce higher conducting state loss.These devices comprise reduction surface field (RESURF) device, and wherein the depletion region of substrate diode and the depletion region of transverse diode interact to reduce surface field.In these devices, puncture voltage is added due to the horizontal broadening of depletion region.
Therefore, exist and provide the RF performance of improvement and the needs of more high-power high-voltage semiconductor device compared to traditional semiconductor device.
Summary of the invention
The invention provides the various electronic circuits of the power amplifier being used as amplification input signal.Exemplary circuit comprises MOSFET and JFET, and the two all comprises source electrode and drain electrode, and wherein the source electrode of JFET is directly coupled to the drain electrode of MOSFET.MOSFET also comprises grid, and JFET also comprises both top grid and bottom grid simultaneously.In certain embodiments, the grid of MOSFET and JFET has different width.In various embodiments, the source electrode of both MOSFET and JFET and drain electrode, and the top grid of JFET and bottom grid are limited in substrate, the grid of MOSFET is disposed on substrate simultaneously.In some instances, substrate comprises the Silicon-On-Insulator wafer of the silicon layer had on insulator layer, and in these embodiments, the feature be limited in substrate is limited in silicon layer.
In various embodiments, the top grid of JFET is coupled to the grid of MOSFET.In some embodiments in these embodiments, the bottom grid of JFET is also coupled to the grid of MOSFET, and in some embodiments in these embodiments, the top grid of JFET and bottom grid are all coupled to DC bias source.
In the various embodiments of exemplary circuit, the top grid of JFET is coupled to the bottom grid of JFET, and two grids are all independent of the grid of MOSFET.In some embodiments in these embodiments, the top grid of JFET and bottom grid are all coupled to DC bias source, and in some other embodiment in these embodiments, the top grid of JFET and bottom grid be all coupled to (ground).In other embodiments again in these embodiments, the bottom grid that the top grid of JFET is coupled to a DC bias source and/or JFET is coupled to the 2nd DC bias source or ground.
The present invention also relates to various device.Example device comprises the transceiver being coupled to power amplifier mentioned above.In various embodiments, transceiver is configured to produce the signal that the signal of frequency that has in the scope of about 700MHz to about 2.5GHz or generation have the frequency in the scope of about 150MHz to about 6GHz.In certain embodiments, transceiver is disposed on the substrate identical with MOSFET with JFET.Various embodiment comprises the output matching circuit of the drain electrode of being coupled to JFET further.
Further, the present invention is also provided for the method that signal amplifies.Exemplary method comprises grid with the first signal controlling MOSFET, with the top grid of secondary signal control JFET and the bottom grid with the 3rd signal controlling JFET, wherein JFET is in and configures with the cascade of MOSFET (cascode).In various embodiments, secondary signal depends on the first signal and in some embodiments in these embodiments, the 3rd signal depends on secondary signal.Similarly, in various embodiments, in secondary signal some embodiments independent of the first signal and in these embodiments, the 3rd signal depends on secondary signal.
Invention further provides the method making electronic circuit.Exemplary method comprises the Silicon-On-Insulator wafer providing and have the silicon layer on insulator layer embedded in wafer, such as by ion implantation, the MOSFET comprising source electrode and drain electrode is limited in the silicon of wafer, by comprise source electrode, drain electrode, top grid and bottom grid JFET be limited in the silicon of wafer, and such as on silicon, formed the grid of MOSFET by photoetching.In various embodiments, the method comprises the metal level formed with the drain electrode of the source electrode of JFET and MOSFET all telecommunication further, thus the source electrode of JFET is directly coupled to the drain electrode of MOSFET.
Another exemplary circuit of the present invention comprises the MOS device formed substantially in the substrate.This substrate comprises the first trap be limited in substrate, and wherein the feature of trap is such as by top surface that leveling substrate is formed.Be limited in trap be bottom grid, be limited to the first raceway groove between bottom grid and top surface, the first drain electrode, the second drain electrode between the first drain electrode and source electrode, the first grid between the first drain electrode and the second drain electrode and the gap between source electrode and the second drain electrode.MOS device comprise further be arranged in the first trap top surface above and with the dielectric layer of gap alignment and the second grid that is arranged in above dielectric layer.In example MOS device, first grid controls the first raceway groove, and second grid controls the second raceway groove be also arranged in the first trap.First raceway groove and the second raceway groove are differently adulterated, and make when a raceway groove is doped to N-shaped, another raceway groove is doped to p-type.
The various embodiments of example MOS device also comprise restriction two sidewalls in the first trap, are connected to bottom grid to make two sidewalls.Second trap is by being limited in the first trap by the volume enclosed between two sidewalls and between bottom grid and top grid.In one configuration, a sidewall in two sidewalls is disposed between first grid and second grid, is in the MOSFET in triple-well with the side making the first source electrode, second grid and the second drain electrode be included in a sidewall.In these embodiments, the first trap also comprises, be defined in wherein be arranged in second source electrode between sidewall and first grid.In these embodiments, the second source electrode, first grid and the first drain electrode all in the second trap, and form bigrid JFET with bottom grid together with the first raceway groove.In these embodiments, a sidewall is disposed between the second source electrode and the second drain electrode, and therefore MOSFET and JFET is electrically coupled to the second source electrode from the second drain electrode by the conductive path (being such as arranged in the metal trace substrate) be limited to above top surface.In these embodiments, one or two sidewalls can have the doping identical with bottom grid.At least one sidewall is exposed on top surface place, is applied to bottom grid to allow voltage.
In another configuration, two sidewalls are arranged such that the first source electrode, the first drain electrode and the second drain electrode, first grid and the first raceway groove are all disposed in the second trap.These embodiments do not comprise the second source electrode, do not comprise triple-well yet.On the contrary, the first raceway groove is offeed telex and is led and control by first grid between the second drain electrode and the first drain electrode, and the second raceway groove be arranged in the second trap is offeed telex and led and control by second grid between the first source electrode and the second drain electrode.In these embodiments, the second raceway groove is disposed between bottom grid and second grid.Note, first raceway groove and the second raceway groove are doped to make when a raceway groove is doped to N-shaped, another raceway groove is doped to p-type, therefore, in these embodiments, the opposite side of the second trap is doped to side and is N-shaped and opposite side is p-type, and the boundary interface place that they extend between the second drain electrode and bottom grid meets.
Accompanying drawing explanation
In order to simple and clear and element in pictorial image, and the element in figure is not proportionally drawn.The size of some elements may be exaggerated to help improve the understanding of various embodiment of the present invention relative to other elements.
Fig. 1 illustrates the illustrated section of double-gate semiconductor devices in N+ district comprising mos gate pole, junction gate and two vicinities according to an embodiment of the invention.
Fig. 2 illustrates the illustrated section comprising the double-gate semiconductor devices in the Liang Ge N+ district that mos gate pole, junction gate and use conductive layer are coupled according to an embodiment of the invention.
Fig. 3 illustrates the illustrated section of double-gate semiconductor devices comprising mos gate pole, junction gate and be arranged in the single N+ district between mos gate pole and junction gate according to an embodiment of the invention.
Fig. 4 illustrates the double-gate semiconductor devices illustrated section in Fig. 3 in this second mode of operation according to an embodiment of the invention.
Fig. 5 illustrates the exemplary circuit figure of the double-gate semiconductor devices in Fig. 1 to Fig. 3 according to an embodiment of the invention and Fig. 6.
Fig. 6 illustrates the illustrated section comprising the double-gate semiconductor devices of mos gate pole and junction gate according to an embodiment of the invention.
Fig. 7 provides the circuit diagram comprising the example electronic circuit of MOSFET and bigrid JFET according to an embodiment of the invention.
Fig. 8 A, 8B and 8C are the cross sections of the example electronic circuit according to three embodiments of the present invention, and each example electronic circuit comprises MOSFET and bigrid JFET, and wherein MOSFET and JFET is different.
Fig. 9 to Figure 15 provides the circuit diagram comprising several example electronic circuit of MOSFET and bigrid JFET according to various embodiments of the present invention.
Figure 16 provides the flow chart carrying out the exemplary method of amplifying signal for being used in MOSFET in cascode configuration in FIG and bigrid JFET and represents.
Figure 17 is the cross sectional view of MOS device according to one example embodiment.
Figure 18 is the cross sectional view of the MOS device according to another example embodiment of the present invention.
Embodiment
The disclosure relates to double-gate semiconductor devices, it is characterized in that the high-breakdown-voltage of the large drift (excursion) allowing output voltage, makes these semiconductor device be useful for the power application of such as power amplification.Disclosed double-gate semiconductor devices comprises metal-oxide semiconductor (MOS) (MOS) grid and junction gate in this article, and wherein junction gate biased can be the function of the grid voltage of mos gate pole.The puncture voltage of this double-gate semiconductor devices is the summation of the puncture voltage of mos gate pole and junction gate.Because independent junction gate has this high puncture voltage of taking over the land for use, so the puncture voltage of double-gate semiconductor devices is higher than the puncture voltage of independent mos gate pole.
Compared with traditional complementary metal oxide semiconductors (CMOS) (CMOS) device, except except the operability of more high power levels, double-gate semiconductor devices provides the RF performance of improvement.Semiconductor fabrication techniques known in the art can be used, substantially on substrate and/or middle making double-gate semiconductor devices, and the standard manufacture craft for CMOS and logical device of the tiny amendment had in technological process can be used.
Mos gate extremely can comprise metal-oxide-semiconductor structure.When voltage is applied to mos gate pole, this structural modification CHARGE DISTRIBUTION in the semiconductor structure, therefore controls the conductive features of semiconductor structure.Therefore mos gate extremely can play grid as electric control or switch.The grid of the type can find in metal oxide semiconductor field effect tube (MOSFET).Junction gate comprises the region of the raceway groove of the semi-conducting material with the doping feature contrary with all the other regions of raceway groove, makes when voltage is applied to junction gate, and the CHARGE DISTRIBUTION in raceway groove is modified and controls the conductive features of raceway groove thus.Therefore junction gate can serve as grid or the switch of electric control.The grid of the type can find in technotron (JFET).The effective resistance of junction gate is by the resistance of the voltage-controlled raceway groove of junction gate.
Double-gate semiconductor devices disclosed herein can be made as one or more injection region be included between mos gate pole and junction gate.Compared with the embodiment of one or more injection region be included between mos gate pole and junction gate, the embodiment without the injection region between mos gate pole and junction gate can provide higher space density configuration for double-gate semiconductor devices.The principle of the operation of these various embodiments is similar, except the depletion region between mos gate pole raceway groove and drift region is modified.
Fig. 1 illustrates the illustrated section of double-gate semiconductor devices in N+ district (i.e. injection region) comprising mos gate pole, junction gate and two vicinities.Double-gate semiconductor devices 100 can use semiconductor fabrication techniques known in the art to be formed by the district of doped silicon, polysilicon, metal and insulating barrier and/or floor.To be appreciated that as used herein term " oxide skin(coating) " is the term of this area, and refer to any suitable insulating barrier of the barrier layer be used as in MOS device, no matter whether it comprises oxygen.This term occurs it being because this layer is formed by silicon dioxide traditionally, but in recent years, become and also can have been made by the other materials of such as low k dielectric material and so on, some of them do not comprise oxygen.
The N-trap 120 that double-gate semiconductor devices 100 comprises P-substrate 110, formed in P-substrate 110, N+ source electrode 130, grid 140, oxide skin(coating) 150, N+ district 160, N+ district 162, P+ grid 170 and N+ drain electrode 180.As used herein, the strong doping (such as, N+ indicates N-type to adulterate by force) of the indicated conduction type of "+" symbol instruction, the weak doping (such as, P-indicates P type weak doping) of the indicated conduction type of "-" symbol instruction.
Such as V g1with control voltage V g2and so on the signal of telecommunication can be coupled to grid 140 and P+ grid 170 respectively.Also can use semiconductor fabrication techniques known in the art, use and be arranged in extra polysilicon layer (not shown) in N+ source electrode 130, N+ district 160, N+ district 162 and N+ drain electrode 180 on each surface or coupling electrical signals is drained 180 to N+ source electrode 130, N+ district 160, N+ district 162 and N+ by metal level (not shown).
Double-gate semiconductor devices 100 comprises the N-type MOS field-effect transistor (also referred to as N-channel MOS FET) formed by P-substrate 110, N+ source electrode 130 and N+ district 160, grid 140 and oxide skin(coating) 150.Double-gate semiconductor devices 100 also comprises the N channel junction field-effect transistors (also referred to as N-type JFET) formed by P-substrate 110, N-trap 120, N+ district 162, P+ grid 170 and N+ drain electrode 180.In this embodiment, N+ district 160 and N+ district 162 are contiguous and N+ district 162 is disposed in N-trap 120 substantially.
Alternatively, the element of double-gate semiconductor devices 100 can be configured to make double-gate semiconductor devices 100 comprise P type mos gate pole, and described P type mos gate pole comprises P channel junction grid.In such an embodiment, according to manufacturing technology known in the art, some in the district of doped silicon and/or floor can have different doping.
Double-gate semiconductor devices 100 can be considered to operate in two kinds of patterns.Illustrated first mode in Fig. 1, by V g1> threshold voltage V thwith | V g2-V pI| ≈ 0 (that is, V g2-V pIabsolute value be about 0) instruction.V g1the voltage at grid 140 place, V g2the voltage at P+ grid 170 place, V ththe threshold voltage for grid 140, and V pIthe voltage at place of N+ district 162.In a first mode, V is greater than thvoltage V g1being applied to grid 140, is " conducting " to make mos gate pole.Control voltage V g2be applied to P+ grid 170, utilize at control voltage V to make junction gate g2with the voltage V in N+ district 162 pIbetween low potential difference be biased.Therefore P+ grid 170 presents low resistance to current flowing, R on.In a first mode, semiconductor device 100 conduction current between N+ source electrode 130 and N+ drain electrode 180.In a second mode, semiconductor device 100 non-conducting electric current.
Return Fig. 1, in a second mode, negative control voltage V g2be applied to P+ grid 170 and depletion region under P+ grid 170 extends in the raceway groove (not shown) in N-trap 120.When being applied to the control voltage V of P+ grid 170 g2make | V g2-V pI| be greater than pinch-off voltage V offtime, the raceway groove under P+ grid 170 is completely depleted and does not have current flowing between N+ district 162 and N+ drain electrode 180.Similarly, in a second mode, between N+ source electrode 130 and N+ drain electrode 180, current flowing is not had.
As control voltage V g2be applied to P+ grid 170 to make | V g2-V pI| time ≈ 0 (corresponding to first mode), raceway groove is the flowing between the 180 and electric current of majority carrier can drain in N+ district 162 and N+ of opening.Therefore, P+ grid 170 (junction gate) can show as variable resistance equivalently, wherein as | V g2-V pI| >V offtime, there is high effective resistance R off, effective resistance R offallow little or there is no electric current flowing between N+ source electrode 130 and N+ drain electrode 180, and working as | V g2-V pI| during ≈ 0, there is the low effective resistance R allowing maximum current flowing on.
Double-gate semiconductor devices 100 can comprise and has two grid device, the wherein control voltage V at P+ grid 170 (junction gate) place g2can be the voltage V at grid 140 (mos gate pole) place g1function.Mos gate pole and junction gate can use and be all in " conducting " or " shutoff " state by simultaneously dynamically biased with reference to the control circuit device described by figure 5.
High effective resistance R in the second mode of operation offallow P+ grid 170 to bear high voltage and the voltage potential between grid 140 and N+ district 160 be restricted to and be less than mos gate pole puncture voltage.Because the puncture voltage of double-gate semiconductor devices 100 is summations of the puncture voltage of mos gate pole and P+ grid 170, so this of P+ grid 170 is taken over the land for use, high puncture voltage provides the high puncture voltage of double-gate semiconductor devices 100.
Control voltage V g2control circuit device can be used to adjust and depend on pinch-off voltage V off.Control circuit device can comprise and being configured to the RF signal coupling from grid 140 to the capacitor (not shown) of P+ grid 170.In order to limit the distance between grid 140 and P+ grid 170, the metal level that capacitor can be used in multiple-level stack parallel between grid 140 and P+ grid 170 realizes.
Fig. 2 illustrates the illustrated section of the double-gate semiconductor devices comprising the Liang Ge N+ district that mos gate pole, junction gate and use conductive layer are coupled.Double-gate semiconductor devices 200 can use semiconductor fabrication techniques known in the art to be formed by the district of doped silicon, polysilicon, metal and insulating barrier and/or floor.
The N-trap 120 that double-gate semiconductor devices 200 comprises P-substrate 110, formed in P-substrate 110, N+ source electrode 130, grid 140, oxide skin(coating) 150, N+ district 260, N+ district 262, conductive layer 265, P+ grid 170 and N+ drain electrode 180.Conductive layer 265 can be polysilicon layer, metal level or another conductive layer as known in the art.As illustrated in Figure 2 like that, N+ district 260 and N+ district 262 by the differentiation of P-substrate 110 from, and N+ district 262 is disposed in N-trap 120 substantially.
As discussed herein, about double-gate semiconductor devices 200, the signal of telecommunication (such as V g1with control voltage V g2) grid 140 and P+ grid 170 can be coupled to respectively.Also can use semiconductor fabrication techniques as known in the art, use and be arranged in extra polysilicon layer (not shown) in N+ source electrode 130, N+ district 260, N+ district 262 and N+ drain electrode 180 on each surface or coupling electrical signals is drained 180 to N+ source electrode 130, N+ district 260, N+ district 262 and N+ by metal level (not shown).
Double-gate semiconductor devices 200 comprises the N-type MOSFET formed by P-substrate 110, N-trap 120, N+ source electrode 130 and N+ district 260, grid 140 and oxide skin(coating) 150.Double-gate semiconductor devices 200 also comprises the N raceway groove JFET formed by P-substrate 110, N-trap 120, N+ district 262, P+ grid 170 and N+ drain electrode 180.In this embodiment, N+ district 260 and N+ district 262 are coupled by use conductive layer 265.
Alternatively, the element of double-gate semiconductor devices 200 can be configured to double-gate semiconductor devices 200 is comprised: the P type mos gate pole comprising P channel junction grid or the N-type mos gate pole comprising P channel junction grid or comprise the P type mos gate pole of N channel junction grid.In this embodiment, according to semiconductor fabrication techniques known in the art, some in the district of doped silicon and/or floor can have different doping.
Double-gate semiconductor devices 200 can be considered to as operated like kind of the Pattern Class of two described by Fig. 1 herein.First mode is by V g1> threshold voltage V thwith | V g2-V pI| ≈ 0 indicates, wherein V pIthe voltage at place of N+ district 262.In a first mode, V is greater than thvoltage V g1being applied to grid 140 to make mos gate pole is " conducting ".Control voltage V g2be applied to P+ grid 170 to utilize at control voltage V to make junction gate g2with the voltage V in N+ district 262 pIbetween there is low potential difference be biased.Therefore P+ grid 170 presents low resistance R for current flowing on.In a first mode, semiconductor device 200 conduction current between N+ source electrode 130 and N+ drain electrode 180.In a second mode, semiconductor device 200 non-conducting electric current.
As control voltage V g2be applied to P+ grid 170 to make | V g2-V pI| time ≈ 0 (corresponding to first mode), raceway groove is the flowing between the 180 and electric current of majority carrier can drain in N+ district 262 and N+ of opening.Therefore, P+ grid 170 (junction gate) can show as variable resistance equivalently, when | V g2-V pI| >V offtime, there is the high effective resistance R allowing seldom or do not have electric current flowing between N+ source electrode 130 and N+ drain electrode 180 off, and work as | V g2-V pI| there is during ≈ 0 the low effective resistance R allowing maximum current flowing on.
Double-gate semiconductor devices 200 can comprise and has two grid device, the wherein control voltage V at P+ grid 170 (junction gate) place g2it can be the function of the voltage at grid 140 place.Mos gate pole and junction gate can use and be in " conducting " state or " shutoff " state with reference to the control circuit device described by figure 5 by simultaneously dynamically biased.Control circuit device can comprise be configured to as described with reference to fig. 1 by the RF signal coupling from grid 140 to the capacitor (not shown) of P+ grid 170.
In this second mode of operation, high effective resistance R offp+ grid 170 is allowed to bear high voltage and the voltage potential between grid 140 and N+ district 260 be restricted to the puncture voltage being less than mos gate pole.Because the puncture voltage of double-gate semiconductor devices 200 is summations of the puncture voltage of mos gate pole and P+ grid 170, so this of P+ grid 170 is taken over the land for use, high voltage provides the high-breakdown-voltage of double-gate semiconductor devices 200.
Fig. 3 illustrates the illustrated section of the double-gate semiconductor devices comprising mos gate pole and junction gate and be arranged in the single N+ district between mos gate pole and junction gate.Double-gate semiconductor devices 300 can use semiconductor fabrication techniques known in the art to be formed by the district of doped silicon, polysilicon, metal and insulating barrier and/or floor.The N-trap 120 that double-gate semiconductor devices 300 comprises P-substrate 110, formed in P-substrate 110, N+ source electrode 130, grid 140, oxide skin(coating) 150, N+ district 360, P+ grid 170 and N+ drain electrode 180.As illustrated in Figure 3 like that, N+ district 360 is disposed in N-trap 120 substantially.
Described by referring to figs. 1 to Fig. 2, the signal of telecommunication (such as V g1with control voltage V g2) grid 140 and P+ grid 170 can be respectively coupled to.Also can use semiconductor fabrication techniques known in the art, use and be arranged in extra polysilicon layer (not shown) in N+ source electrode 130, N+ district 360 and N+ drain electrode 180 on each surface or coupling electrical signals is drained 180 to N+ source electrode 130, N+ district 360 and N+ by metal level (not shown).
Double-gate semiconductor devices 300 comprises the N-type mos gate pole formed by P-substrate 110, grid 140 and oxide skin(coating) 150.Double-gate semiconductor devices 300 also comprises the N raceway groove JFET formed by P-substrate 110, N-trap 120, N+ district 360, P+ grid 170 and N+ drain electrode 180.In this embodiment, N+ district 360 is the source electrode of N raceway groove JFET and adjoins N-type mos gate pole, and N-type mos gate pole comprises grid 140 and oxide skin(coating) 150.
Double-gate semiconductor devices 300 can be considered to as operated like kind of the Pattern Class of two described by Fig. 1 to Fig. 2 herein.First mode is by V g1> threshold voltage V thwith | V g2-V pI| ≈ 0 indicates, wherein V pIthe voltage at place of N+ district 360.In a first mode, V is greater than thvoltage V g1being applied to grid 140, is " conducting " to make mos gate pole.Control voltage V g2be applied to P+ grid 170, utilize at control voltage V to make junction gate g2with the voltage V in N+ district 360 pIbetween low potential difference be biased.Therefore P+ grid 170 presents low resistance R for current flowing on.In a first mode, semiconductor device 200 conduction current between N+ source electrode 130 and N+ drain electrode 180.In a second mode, semiconductor device 200 non-conducting electric current.
As control voltage V g2be applied to P+ grid 170 to make | V g2-V pI| time ≈ 0 (corresponding to first mode), raceway groove is the flowing between the 180 and electric current of majority carrier can drain in N+ district 360 and N+ of opening.Therefore, P+ grid 170 (junction gate) can show as variable resistance equivalently, when | V g2-V pI| >V offtime, there is the high effective resistance R allowing seldom or do not have electric current flowing between N+ source electrode 130 and N+ drain electrode 180 off, and work as | V g2-V pI| allow the low effective resistance R of maximum current flowing during ≈ 0 on.
Described by referring to figs. 1 to Fig. 2, double-gate semiconductor devices 300 can be considered to have two grid device, wherein the control voltage V at P+ grid 170 (junction gate) place g2can be the voltage V at grid 140 place g1function.Mos gate pole and junction gate can use and be in " conducting " state or " shutoff " state with reference to the control circuit device described by figure 5 by simultaneously dynamically biased.Control circuit device can comprise be configured to as described with reference to fig. 1 by the RF signal coupling from grid 140 to the capacitor (not shown) of P+ grid 170.
In this second mode of operation, high effective resistance R offp+ grid 170 is allowed to bear high voltage and the voltage potential between grid 140 and N+ district 360 be restricted to the puncture voltage being less than mos gate pole.Because the puncture voltage of double-gate semiconductor devices 300 is summations of the puncture voltage of mos gate pole and P+ grid 170, so this of P+ grid 170 is taken over the land for use, high voltage provides the high-breakdown-voltage of double-gate semiconductor devices 300.
Fig. 4 illustrates the illustrated section of the double-gate semiconductor devices 300 of Fig. 3 in this second mode of operation.The description of this paper of double-gate semiconductor devices 300 in this second mode of operation is applied to similarly respectively referring to figs. 1 to the second operator scheme of the double-gate semiconductor devices 100 and 200 described by Fig. 2.
In this second mode of operation, the voltage V of grid 140 is applied to g1lower than threshold voltage V th, thus mos gate pole is " shutoff ".Control voltage V g2be applied to P+ grid 170, pass through to make junction gate to use V g2with the voltage V in N+ district 360 pIbetween high potential difference be biased in pinch-off voltage V offnear.Therefore P+ grid 170 presents high effective resistance R for the current flowing of drift region (all drift regions 420 as illustrated in figure 4) off.High effective resistance R offby under P+ grid 170 and around extend depletion region (all depletion regions 410 as illustrated in Figure 4) produce.
High effective resistance R in this second mode of operation offp+ grid 170 is allowed to bear high voltage and the voltage swing at grid 140 place is restricted to the puncture voltage being less than mos gate pole.Second operator scheme protects grid 140 from the voltage higher than puncture voltage effectively.Because the puncture voltage of double-gate semiconductor devices 300 is summations of the puncture voltage of mos gate pole and P+ grid 170, so this of P+ grid is taken over the land for use, high puncture voltage provides the high-breakdown-voltage of double-gate semiconductor devices 300.
Fig. 5 illustrates the exemplary circuit figure of the double-gate semiconductor devices of Fig. 1 to Fig. 2.Circuit 500 comprises N raceway groove JFET 510, N-channel MOS FET 530 and control circuit device 530.Control circuit device 530 can be the voltage V of N-channel MOS FET 520 g1the control voltage V of function g2be provided to the grid of N raceway groove JFET 510.Control circuit device 530 work with simultaneously dynamically biased both N-channel MOS FET 520 and N raceway groove JFET510 be in " conducting " state or " shutoff " state.Control circuit device 530 can be can by the capacitor of the RF signal coupling of the grid from N-channel MOS FET to the grid of N raceway groove JFET.
Control circuit device 530 provides control voltage V g2with biased N raceway groove JFET 510, to make (the V when N-channel MOS FET is " shutoff " g1<V th), R offeffective resistance is maximum.Usually, control voltage V g2the contiguous pinch-off voltage V of biased N raceway groove JFET 510 off.(the V when N-channel MOS FET 520 is " conductings " g1>V th), then control circuit 530 provides control voltage V g2with biased N raceway groove JFET 510, to make R oneffective resistance is minimum and electric current is maximum.R onto R offeffective resistance change allow on a large scale the voltage of drain electrode place of N raceway groove JFET 510 drift greatly and for the corresponding high power performance referring to figs. 1 to the double-gate semiconductor devices described by Fig. 2.Also can be expressed as the circuit diagram being similar to circuit 500 referring to figs. 1 to the double-gate semiconductor devices described by Fig. 2, wherein N channel junction grid 510 can by P channel junction grid (not shown) substitute and N-channel MOS grid 520 can be substituted by P channel MOS grid (not shown).
Fig. 6 illustrates the cross section of double-gate semiconductor devices according to an embodiment of the invention.In this embodiment, double-gate semiconductor devices 600 can to make than the space density configuration higher referring to figs. 1 to the embodiment described by Fig. 4.As illustrated in Figure 6 like that, double-gate semiconductor devices 600 does not comprise N+ district, such as referring to figs. 1 to the N+ district 160 described by Fig. 4, N+ district 162, N+ district 260, N+ district 262 and N+ district 360.Therefore, do not use the common injection in the N+ district between mos gate pole and junction gate to make double-gate semiconductor devices 600.The principle of the operation of double-gate semiconductor devices 600 is similar to the principle of the operation (comprising the description with reference to the second operator scheme described by figure 4) referring to figs. 1 to the double-gate semiconductor devices 100,200 and 300 described by Fig. 3.
Double-gate semiconductor devices 600 can use semiconductor fabrication techniques known in the art to be formed by the district of doped silicon, polysilicon, metal and insulating barrier and/or floor.N-trap 120, N+ source electrode 130, grid 140, oxide skin(coating) 150, P+ grid 170 and the N+ drain electrode 180 that double-gate semiconductor devices 600 comprises P-substrate 110, formed in P-substrate 110.
Such as V g1with control voltage V g2the signal of telecommunication can be coupled to grid 140 and P+ grid 170 respectively.Semiconductor fabrication techniques known in the art can be used, use and be arranged in extra polysilicon layer (not shown) in N+ source electrode 130 and N+ drain electrode 180 on each surface or coupling electrical signals is drained 180 to N+ source electrode 130 and N+ by metal level (not shown).
Double-gate semiconductor devices 600 can be considered to be similar to referring to figs. 1 to the operation mode of two described by Fig. 4.In a first mode, electric current conduction between N+ source electrode 130 and N+ drain electrode 180.In a second mode, electric current non-conducting.In a first mode, threshold voltage V is greater than ththe voltage V of (not shown) g1be applied to grid 140.Control voltage V g2be applied to P+ grid 170, thus low effective resistance R presented to current flowing on.
In this second mode of operation, the voltage V of grid 140 is applied to g1lower than threshold voltage V th, and control voltage V g2be applied to P+ grid 170, therefore high effective resistance R presented to current flowing off.High effective resistance R offproduced by depletion region, depletion region is similar to reference to the depletion region 410 described by figure 4, under P+ grid 170 and around extend.
Fig. 7 provides the circuit diagram of the example electronic circuit 700 of the input signal for amplifying such as RF signal.Electronic circuit 700 comprises with the MOSFET 705 of cascode configuration in FIG and bigrid JFET 710.In circuit 700, JFET 710 is used as variable resistance.
MOSFET 705 and bigrid JFET 710 is different transistors.As used herein, except the injection region that transistors share is common, two transistors are restricted to different.As an example, N+ district 260 and 262 (Fig. 2) is drain electrode and the source electrode of different transistors respectively.As another example, N+ district 160 and 162 (Fig. 1) is drain electrode and the source electrode of different transistors respectively, because their two shared N+ injection regions.
MOSFET 705 comprises drain electrode and source electrode, and source electrode is coupled to power supply, such as V in operation dD.MOSFET 705 controls by grid, and grid receives input signal, such as RF input signal from the signal source of such as transceiver 715 in operation.Input matching circuit 720 between the grid that the various embodiments of circuit 700 are included in transceiver 715 and MOSFET 705 is to mate the impedance on its every side.A kind of example match circuit 720 comprises capacitor and inductor, wherein capacitor be coupling in and the grid of transceiver 715 and MOSFET 705 between node between, and inductor is arranged between node and the grid of MOSFET 705 into a line.In various embodiments, the grid length of MOSFET 705, the length that the grid namely between source electrode and drain electrode injects, is less than 1 micron.Notice that grid width is the size of the grid in the plane of the substrate measured perpendicular to grid length.In various embodiments, MOSFET 705 can be NMOSFET or PMOSFET.
In certain embodiments, signal source, such as transceiver 715, be disposed on the substrate identical with bigrid JFET 710 with MOSFET705.In a further embodiment, signal source produces the signal of the frequency had in the scope of about 700MHz to about 2.5GHz.In a further embodiment, signal source produces the signal of the frequency had in the scope of about 150MHz to about 6GHz.
Bigrid JFET 710 comprises the source electrode and drain electrode that are electrically connected by the raceway groove controlled by two grids (being arranged in the top grid 725 above and below raceway groove and bottom grid 730).In various embodiments, bigrid JFET 710 can be NJFET or PJFET.In various embodiments, bigrid JFET 710 comprises sub-micron grid length.The drain electrode of bigrid JFET710 is coupled to antenna 735 or is configured for another device of Signal transmissions.In certain embodiments, antenna 735 is coupled to the drain electrode of bigrid JFET 710 by the output matching circuit 740 formed by passive network, and output matching circuit 740 is also provided to matched impedance.
The source electrode of bigrid JFET 710 is coupled to the drain electrode of MOSFET 705.In certain embodiments, the source electrode of bigrid JFET 710 is directly coupled to the drain electrode of MOSFET 705.As used herein, " direct-coupling " means do not have active parts in the electrical connection between the transistor be coupled.In certain embodiments, the source electrode of bigrid JFET 710 is coupled to the drain electrode of MOSFET 705 by the trace of through hole and such as conductive layer 265 (Fig. 2).In certain embodiments, the point between the drain electrode of bigrid JFET 710 and MOSFET 705 comprises common node (CN) point.As shown in Figure 7, in some instances, electronic circuit 700 also can comprise, the optional common node circuit 750 be coupled between common node point and ground.
As explained above, JFET 710 controls by top grid 725 and bottom grid 730.In various embodiments, top grid 725 and bottom grid 730 are complementary (such as jointly controlled) or independently, and can be biased, be applied to the input signal of the grid of MOSFET 705 or input signal by ground, DC and add that DC is biased to be controlled.Control referenced Fig. 9 to Figure 15 discussion of various exemplary methods of top grid 725 and bottom grid 730.In the example that Fig. 7 provides, top grid 725 and bottom grid 730 are similar to the output co-controlling of the optional JFET grid circuit 745 of control circuit 530 (Fig. 5).
JFET grid circuit 745 is used for improving the performance of embodiments of the invention being used as power amplifier.The biased of bottom grid 730 determines that the voltage of top grid 725 is with pinch off JEFT710, and wherein the pinch-off voltage of JFET 710 is limits values of the drain electrode for MOSFET 705.It is the value allowing the pinch-off voltage of JFET 710 protection MOSFET 705 to be in reliable district for the desired value that bottom grid 730 is biased.In certain embodiments, the top grid 725 of JFET 710 is maintained at 0V.But very large grid to source electrode and grid to capacitance of drain by the very large voltage couples of drain electrode and source electrode on grid voltage, reduce the R of JFET 710 offand R onthe efficiency of change.The function of JFET grid circuit 745 is these signals by applying on contrary signal cancellation top grid 725.
In some instances, as shown in Figure 7, electronic circuit 700 also can comprise the optional common node circuit 750 be coupling between common node point and ground.Common node circuit 750 is also used for improving the performance of embodiments of the invention being used as power amplifier.The grid of common node circuit 750 compensating MOS FET 705 is to the grid of capacitance of drain and JFET 710 to the effect of source capacitance.In certain embodiments, common node circuit 750 can single inductance or be configured to and series inductor-capacitor (LC) network of the electric capacity illustrated by MOSFET 705 and JFET 710 at characteristic frequency resonance.
Fig. 8 A provides the cross section of the example electronic circuit 800 comprising MOSFET 805 and bigrid JFET 810, and wherein MOSFET 805 and JFET 810 forms different transistors.As in the previous embodiment, MOSFET 805 and bigrid JFET 810 can use semiconductor fabrication techniques known in the art to be formed by the district of doped silicon, polysilicon, various metal and various insulating barrier or floor.In this example, the source electrode 815 of bigrid JFET 810 is directly coupled to the drain electrode 820 of MOSFET 805 by metal level 825 and through hole 830.As different transistors, MOSFET 805 and bigrid JFET 810 can diverse location place on the same substrate and being of different sizes, and such as different width realizes.
JFET 810 additionally comprises drain electrode 835, top grid 840 and bottom grid 845.Top grid 840 and bottom grid 845 are disposed in and are coupled to above and below the N raceway groove 850 of drain electrode 820 by the source electrode 815 of JFET 810.Bottom grid 845 defines by providing two the P traps 855 being electrically connected to bottom grid 845.JFET 810 be disposed in comprise two N traps 860 and N separator 865 N well region in.In these embodiments, P trap 855 is also used for N raceway groove 850 and N trap 860 to isolate.
As shown in Figure 8 A, the grid 870 of MOSFET 805 is by signal V g1control.Similarly, the top grid 840 of JFET 810 and bottom grid 845 are respectively by signal V g2and V g3control.As explained above, signal V g2can to depend on or independent of signal V g1.Additionally, signal V g3can to depend on or independent of signal V g2.
Fig. 8 B provides the cross section of another example electronic circuit 875 comprising MOSFET 805 and bigrid JFET 810, and wherein MOSFET 805 and JFET 810 forms different transistors.In circuit 875, eachly in MOSFET 805 and bigrid JFET 810 to be disposed in independent N well region.Here, wherein arrange that the N well region of MOSFET 805 is defined by two N traps 880 and N separator 885.These embodiments are advantageously by the substrate isolation of MOSFET805 and JFET 810.
Fig. 8 C provides the cross section of another example electronic circuit 875 comprising MOSFET 805 and bigrid JFET 810, and wherein MOSFET 805 and JFET 810 forms different transistors.Electronic circuit 890 in Fig. 8 C and the electronic circuit 875 different N of the being separator 865 in Fig. 8 B are continuous print across whole substrate.Here, wherein arrange that the N well region of MOSFET is defined by two N traps 880 and the N separator 865 identical with the trap defining JFET 810.
Such as, from the substrate of N separator 865 with embedding, the embodiment of the illustrated electronic circuit of Fig. 8 C can be produced.Substrate can by a surface-borne oxide skin(coating) at wafer, by the second bonding chip to this surface, then from the back side of the second wafer towards oxide skin(coating) carry out polishing until realize above N separator 865 expect material thickness realize; This substrate is commonly called silicon-on-insulator (SOI) wafer.Then the various features being limited to MOSFET 805 in substrate and JFET 810 are proceeded to more shallow feature to be formed from darker feature by ion implantation technique.The feature (as metal wire 825 and grid 870) that substrate is formed, such as, can be formed by photoetching method.Such as, can by forming N separator 865 and N separator 885 alternatively by ion implantation, then formed remaining feature be limited in substrate by ion implantation, then then on substrate, form those features to produce the embodiment of the electronic circuit illustrated in Fig. 8 A and Fig. 8 B by photoetching.
Fig. 9 provides the circuit diagram of the example electronic circuit 900 comprising electronic circuit 700 and comprise the DC bias source 910 being coupled to top grid 725 and bottom grid 730 further.In operation, DC bias voltage is added to input signal to control top grid 725 and bottom grid 730.In various embodiments, DC bias voltage can be positive or negative.Negative-gate voltage can be applied to reduce common-node voltage on top grid 725 and bottom grid 730, guarantee that the drain electrode of MOSFET 805 remains on its reliable district by this way.On the contrary, positive gate voltage can be applied to use the complete drift of reliable drain voltage to improve performance on top grid 725 and bottom grid 730.In the embodiment of such as electronic circuit 900, and in some hereafter described embodiments, MOS and JFET grid circuit 745 and common node circuit 750 are all optional.
Figure 10 provides for comprising electronic circuit 700 and comprising the circuit diagram of example electronic circuit 1000 of the DC bias source 1010 being coupled to top grid 725 and the 2nd DC bias source 1020 being coupled to bottom grid 730 further.In operation, independent DC bias voltage is added to input signal to control each grid in top grid 725 and bottom grid 730 independently.In various embodiments, each DC bias voltage can be positive or negative.Capacitor 1030 is added between top grid 725 and bottom grid 730 and is applied to each grid to allow different DC to be biased, and applies RF that is identical with the grid being applied to MOSFET 705, that be coupled to each grid in top grid 725 and bottom grid 730 simultaneously.
Figure 11 provides the circuit diagram for example electronic circuit 1100, and electronic circuit 1100 comprises electronic circuit 700 but do not have MOS and JFET grid circuit 745 and wherein top grid 725 and bottom grid 730 are all coupled to ground.
Figure 12 provides the circuit diagram for example electronic circuit 1200, and electronic circuit 1200 comprises electronic circuit 700 but do not have MOS and JFET grid circuit 745 and wherein top grid 725 and bottom grid 730 are all coupled to DC bias source 910.In various embodiments, DC bias voltage can be positive or negative.
Figure 13 provides the circuit diagram for example electronic circuit 1300, and electronic circuit 1300 comprises electronic circuit 700 but do not have MOS and JFET grid circuit 745.Additionally, contrary with Fig. 7, a DC bias source 1010 is coupled to top grid 725, and the 2nd DC bias source 1020 is coupled to bottom grid 730, instead of top grid 725 and bottom grid 730 interdepend.In various embodiments, each DC bias voltage can be positive or negative.In those embodiments illustrated in Figure 11 to Figure 13, the control of top grid 725 and bottom grid 730 is independent of input signal.
Figure 14 provides the circuit diagram for example electronic circuit 1400, and electronic circuit 1400 comprises electronic circuit 1300 and comprises MOS and JFET grid circuit 745 further.Figure 15 provides the circuit diagram for example electronic circuit 1500, circuit 1500 comprises amendment to make bottom grid 730 independent of the electronic circuit 700 of top grid 725, and comprise the DC bias source 910 being coupled to top grid 725 further, bottom grid 730 is coupled to ground simultaneously.In Figure 14 and Figure 15 those embodiments illustrated, the control of top grid 725 depends on the control of input signal bottom grid 730 simultaneously independent of input signal.The advantage only RF signal being applied to the top grid 725 of JFET 710 is the electric capacity that electric capacity between top grid 725 and source electrode or drain terminal is less than between bottom grid 730 and source electrode or drain terminal, and top grid 725 is more effective to control channel current flow than bottom grid 730.
The flow chart that Figure 16 provides for utilizing the MOSFET 705 being in cascode configuration in FIG with bigrid JFET 710 to carry out the exemplary method 1600 of amplifying signal represents.The method comprises the step 1610 of the grid with the first signal (input signal that namely will be exaggerated) control MOSFET, the step 1630 with the step 1620 of the top grid of secondary signal control JFET and the bottom grid with the 3rd signal controlling JFET.By it is to be appreciated that the step illustrated in Figure 16 is intended to be performed simultaneously.
In various embodiments, secondary signal is independent of the first signal, and in some embodiments of these embodiments, such as, in the place that the grid of MOSFET and the top grid of JFET are capacitively coupled, two signals are identical.In some embodiments in these embodiments, the 3rd signal also depends on the first signal and secondary signal, as shown in Figure 7 all, and in other embodiments, the 3rd signal independent of the first signal and secondary signal, such as in figures 14 and 15.
In various embodiments, secondary signal is independent of the first signal, as shown in Figure 11 to Figure 13 all.In some embodiments in these embodiments, the 3rd signal depends on secondary signal, and in other embodiments, the 3rd signal is independent of secondary signal.
In various embodiments, the first signal comprises the biased summation of input signal and DC.Also in various embodiments, in secondary signal and the 3rd signal, any or all can be that fixing DC is biased (or positive or negative) or ground.
Figure 17 provides the cross sectional view of another example MOS device 1700 again of the present invention.MOS device 1700 comprises substrate 1705, and substrate 1705 comprises the first trap 1710 be limited in substrate 1705.First trap 1710 is characterised in that top surface 1715, and have wherein limit first source electrode 1720, first drain 1725 and second drain electrode 1730, bottom grid 1735, first top grid 1740.Top surface 1715 overlaps with the top surface of substrate 1705, and such as can be formed by planarization process.First trap 1710 also comprises the isolation structure of being isolated with the remainder of substrate 1705 by the first trap 1710.Isolation structure comprises the separator being parallel to top surface 1715 and arranging, and also comprises two sidewalls, and each sidewall is connected to the opposed end of separator, and each sidewall extends to top surface 1715.Depend on context, the whole volume that term as used herein " trap " can refer to isolation structure or enclose thus, wherein structure and the volume that encloses due to different doping be differentiable in structure.
First source electrode 1720 and the second drain electrode 1730 are separated by gap 1745.MOS device 1700 also comprise be arranged in the first trap 1710 top surface 1715 above and the dielectric layer 1750 aimed at gap 1745, and to be arranged in above dielectric layer 1750 and the second top grid 1755 aimed at gap 1745 similarly.Such as, the second top grid 1755 can comprise electric conducting material, such as polysilicon or metal.First trap 1710 comprises the first raceway groove 1760 be limited between bottom grid 1735 and top surface 1715 further.
In the embodiment of Figure 17, bottom grid 1735 is defined by two sidewalls 1770.Each sidewall 1770 is connected to the opposed end of bottom grid 1735, and at least one sidewall 1770 extends to top surface 1715.Sidewall 1770 limits the second trap be arranged in the first trap 1710 together with bottom grid 1735.First drain electrode the 1725, first top grid 1740, first raceway groove 1760 and the second source electrode 1765 are disposed in the second trap, are disposed between the first drain electrode 1725 and the second source electrode 1765 to make the first top grid 1740.Bottom grid 1735 is electrically connected to top surface 1715 by sidewall 1770, and wherein at least one electrical contact (not shown) can allow bias voltage to be applied to bottom grid 1735.In this embodiment, the first top grid 1740, second source electrode 1765 and bottom grid 1735 and the first raceway groove 1765 jointly form the JFET in these embodiments.
In various embodiments, substrate 1705 can be the silicon with the first doping (such as P-), the isolation structure of the first trap 1710 can have the second doping, such as N-, bottom grid 1735 can have the 3rd doping, such as P+, first source electrode 1720, first drain electrode 1725, second drain electrode 1730 and the second source electrode 1765 can have the 4th doping, such as N+, and top grid 1740 can have the 5th doping of such as P+, the 5th doping can be identical doping of adulterating with the 3rd of bottom grid 1735 the alternatively.Remaining material in the second trap can have (comprising the first raceway groove 1760) the 6th doping of such as N-, and the 6th doping can be identical doping of adulterating with second of the first trap 1710 alternatively.Remaining material in the first trap 1710 but outside the second trap comprises the first source electrode 1720, second drain electrode 1730 and gap 1745.Except the first source electrode 1720 and the second drain electrode 1730, this material can be regarded as being arranged in the first trap 1710 and to have the triple-well of the 7th doping of such as P-.7th doping can be identical doping of adulterating with first of substrate 1705 alternatively.In gap 1745 and around this material form have the 7th doping the second raceway groove 1775.First source electrode 1720, second drain electrode the 1730, second top grid 1755 and the second raceway groove 1775 form MOSFET jointly.Material in the second trap and triple-well is doped to make when being doped to N-shaped for one, and another is doped to p-type.In these embodiments, triple-well lacks the limiting structure being similar to the isolation structure of the first trap 1710 and the bottom grid 1735 of the second trap and sidewall 1770, but can be restricted to the part not in the second trap of the volume that the first trap 1710 encloses.
In the embodiment of Figure 17, a sidewall 1770 is disposed between the second drain electrode 1730 and the second source electrode 1765.Material in second trap is by the second source electrode 1765 and this sidewall 1770 electric insulation, and the material simultaneously in triple-well is by the second drain electrode 1730 and this sidewall 1770 electric insulation.1730 and second all to insulate both source electrode 1765 because this sidewall 1770 and second drains, electric current can not flow through wherein.On the contrary, the second drain electrode 1730 is directly coupled to the second source electrode 1765 to provide current path therebetween by metal level 1780 and through hole 1785.
The electrical contact (not shown) be arranged on top surface 1715 provides and is electrically connected to grid 1735,1740, source electrode 1720,1765, drain electrode 1725,1730, and the first trap 1710 alternatively.Second grid 1755 is electrically contacted and is electrically connected similarly.Grid 1735,1740,1755 can be controlled as described by embodiment above.First trap 1710 can be biased by electrical contact alternatively.
Figure 18 provides the cross sectional view of another example MOS device 1800 again of the present invention.MOS device 1800 comprises substrate 1805, and substrate 1805 comprises the first trap 1810 be limited in substrate 1505.First trap 1810 is characterised in that top surface 1815, and has the first source electrode 1820, first drain electrode 1825 and the second drain electrode 1830, bottom grid 1835 and the first top grid 1840 wherein limited.Top surface 1815 overlaps with the top surface of substrate 1805, and such as can be formed by planarization process.First trap 1810 also comprises the isolation structure of being isolated with the remainder of substrate 1805 by the first trap 1810.Isolation structure comprises the separator being parallel to top surface 1815 and arranging, and also comprises two sidewalls, and each sidewall is connected to the opposed end of separator, and each sidewall extends to top surface 1815.
First source electrode 1820 and the second drain electrode 1830 are separated by gap 1845.MOS device 1800 also comprise be arranged in the first trap 1810 top surface 1815 above and the dielectric layer 1850 aimed at gap 1845, and to be arranged in above dielectric layer 1850 and the second top grid 1855 aimed at gap 1845 similarly.Such as, the second top grid 1855 can comprise electric conducting material, such as polysilicon or metal.First trap 1810 comprises the first raceway groove 1860 be limited between bottom grid 1835 and top surface 1815 further.
In the embodiment of Figure 18, bottom grid 1835 is defined by two sidewalls 1870.Each sidewall 1870 is connected to the opposed end of bottom grid 1835, and at least one sidewall 1870 extends to top surface 1815.Sidewall 1870 limits the second trap be arranged in the first trap 1810 together with bottom grid 1835.First source electrode 1820, second drain electrode 1830, first top grid 1840, first drain electrode 1825 and the first raceway groove 1860 are all disposed in the second trap, wherein the first top grid 1840 and the second drain electrode 1830 are disposed between the first source electrode 1820 and the first drain electrode 1825, and the first top grid 1840 is disposed between the first drain electrode 1825 and the second drain electrode 1830.Bottom grid 1835 is electrically connected to top surface 1815 by sidewall 1870, and wherein at least one electrical contact (not shown) can allow bias voltage to be applied to bottom grid 1735.
In various embodiments, substrate 1805 can be the silicon with the first doping (such as P-), the isolation structure of the first trap 1810 can have the second doping, such as N-, bottom grid 1835 can have the 3rd doping, such as P+, first source electrode 1820, first drain electrode 1825 and the second drain electrode 1830 can have the 4th doping, such as N+, and top grid 1840 can have the 5th doping of such as P+, the 5th doping can be identical doping of adulterating with the 3rd of bottom grid 1835 the alternatively.
Remaining material in the second trap is divided into Liang Ge district, there is the first district 1875 of the 6th doping and there is the second district 1880 of the 7th doping, wherein the 6th doping and the 7th doping are contrary types, and mean when a doping is N-shaped doping, another doping is p-type.6th doping alternatively can with first adulterate identical and/or the 7th adulterate can with second adulterate identical.The border between the first district 1875 and the second district 1880 in the second trap extends between bottom grid 1835 and the second district 1835, all contacts with both districts 1875,1880 to make the second drain electrode 1830.First raceway groove 1860 to be disposed in the second district 1880 and can to offe telex between two drain electrodes 1820,1830 and leads.Second raceway groove 1885 to be disposed in the first district 1875 and can to offe telex between the first source electrode 1820 and the second drain electrode 1830 and leads.
The electrical contact (not shown) be arranged on top surface 1815 provides and is electrically connected to grid 1835,1840, source electrode 1820, and drain electrode 1825,1830.Second grid 1855 is electrically connected similarly.Grid 1835,1840,1855 can be controlled as described by embodiment above.
Embodiment discussed in this article is example of the present invention.As these embodiments described by reference accompanying drawing, various amendment or the reorganization of described method or particular element can become apparent those skilled in the art.All dependences instruction of the present invention, and advanced such amendment, the reorganization of this area by its these instruction or changed, be considered within the scope and spirit of the invention.Therefore, these describe and accompanying drawing should not be considered in limiting sense, are that the present invention is not limited to absolutely only illustrated embodiment as can be appreciated.

Claims (6)

1. a MOS device, comprising:
Substrate, comprises the first trap be limited in described substrate, and the feature of described trap is top surface and has to be limited in described trap:
Bottom grid,
Be limited to the first raceway groove between described bottom grid and described top surface,
First source electrode,
First drain electrode,
The second drain electrode between described first drain electrode and described first source electrode,
First grid between described first drain electrode and described second drain electrode,
Gap between described first source electrode and described second drain electrode, and
Be arranged in the second raceway groove in described first trap, described first raceway groove and described second raceway groove comprise different doping;
Dielectric layer, above the described top surface being arranged in described first trap and with described gap alignment; And
Second grid, to be arranged in above described dielectric layer and with described gap alignment.
2. MOS device according to claim 1, comprises further:
The first side wall, being limited in described first trap and being arranged between described first grid and described second grid, described the first side wall is connected to described bottom grid, and
Second sidewall, is exposed to described top surface place and is also connected to described bottom grid, and described bottom grid and two sidewalls limit the second trap in described first trap.
3. MOS device according to claim 2, comprises the triple-well be arranged in described first trap further,
Wherein said triple-well comprises the part be not in described second trap enclosing volume of described first trap,
The side that wherein said first source electrode, described second grid and described second drain electrode are included in described the first side wall is in the MOSFET in described triple-well,
Wherein said first trap also comprises the second source electrode be limited to wherein, described second source electrode is arranged between described the first side wall and described first grid, and wherein said second source electrode, described first grid are all positioned at described second trap with described first drain electrode and form bigrid JFET with described bottom grid together with described first raceway groove.
4. a MOS device, comprising:
Substrate, comprises the first trap be limited in described substrate, and the feature of described trap is top surface and has to be limited in described trap:
Bottom grid,
Be limited to the first raceway groove between described bottom grid and described top surface,
First source electrode,
First drain electrode,
The second drain electrode between described first drain electrode and described first source electrode,
First grid between described first drain electrode and described second drain electrode,
Gap between described first source electrode and described second drain electrode, and
The first side wall and the second sidewall, all to be limited in described first trap and to be all connected to described bottom grid, described bottom grid and two sidewalls limit the second trap in described first trap, and wherein said first source electrode, described first drain electrode and described second drain electrode and described first grid are all disposed in described second trap;
Dielectric layer, above the described top surface being arranged in described first trap and with described gap alignment; And
Second grid, to be arranged in above described dielectric layer and with described gap alignment.
5. MOS device according to claim 4, comprises the second raceway groove further, and two raceway grooves are all arranged in described second trap, and described first raceway groove and described second raceway groove comprise different doping.
6. MOS device according to claim 5, wherein said first raceway groove is offeed telex and is led and control by described first grid between described second drain electrode and described first drain electrode, and described second raceway groove is offeed telex and led and control by described second grid between described first source electrode and described second drain electrode.
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