CN104766825B - A kind of method and flash devices of increase flash device gate capacitance - Google Patents
A kind of method and flash devices of increase flash device gate capacitance Download PDFInfo
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- CN104766825B CN104766825B CN201410009073.7A CN201410009073A CN104766825B CN 104766825 B CN104766825 B CN 104766825B CN 201410009073 A CN201410009073 A CN 201410009073A CN 104766825 B CN104766825 B CN 104766825B
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000007667 floating Methods 0.000 claims abstract description 40
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 33
- 229920005591 polysilicon Polymers 0.000 claims abstract description 32
- 238000005520 cutting process Methods 0.000 claims abstract description 8
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims description 19
- 150000002500 ions Chemical class 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 17
- 238000005516 engineering process Methods 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 11
- 229910000577 Silicon-germanium Inorganic materials 0.000 abstract description 10
- 230000000694 effects Effects 0.000 abstract description 5
- 230000004913 activation Effects 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 239000000377 silicon dioxide Substances 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention provides a kind of method and flash structures of increase flash device gate capacitance, by carrying out after local Ge ion implantings and etching to the polysilicon layer for preparing floating boom, it is final to prepare a two level floating boom with step cutting pattern, on the premise of device critical dimensions are not influenceed, the contact area of dielectric layer and floating boom and control gate can be effectively increased, improves control gate capacitance；The two level FGS floating gate structure formed simultaneously is also improved to have between dielectric layer and floating boom and control gate and preferably contacted, and then lifts device performance；Further, the floating boom that the present invention is formed is collectively formed by polysilicon layer and germanium-silicon layer, therefore has preferably activation characteristic and lower gate resistance in sige formed with Si SiGe hetero-junctions, doping in floating boom；Junction capacity caused by Si SiGe hetero-junctions can further contribute to the electric capacity of whole device simultaneously, have good effect for the lifting of flash device performances.
Description
Technical field
The present invention relates to semiconductor memory preparation field, and in particular to a kind of method of increase flash device gate capacitance
And flash devices.
Background technology
Now with the continuous development of semiconductor fabrication, the especially design aspect in memory cell, in order to carry
High competitiveness, it is necessary to improve the performance of device, to realize the read/write of faster efficiency, to meet people to high-performance device as far as possible
The continuous pursuit of part.
Fig. 1-3 is the flow chart that in the prior art prepared by flash devices：Comprise the following steps that：
One substrate 1 is provided first, side sequentially forms tunnel oxide 2, floating gate material layer 3 and mask layer 4 over the substrate,
As shown in Figure 1；Then etching forms shallow trench, is ground after oxide layer is filled to groove, forms fleet plough groove isolation structure 5,
As shown in Figure 2；Remaining mask layer 4 ' is removed, after preparing a dielectric layer 6 on floating gate material layer 3a surface, then at the dielectric layer 6
Disposed thereon one controls gate material layer 7, as illustrated in FIG. 3；Carry out follow-up unit component area forming step and source and drain injection work
Skill, subsequent technology uses prior art institute conventional techniques, therefore will not be described here.
In order to obtain higher performance and more large storage capacity, the area of device cell is the smaller the better.This allows for floating boom
Critical size is restricted, and the reduction of floating boom size itself can cause the reduction of the contact area between floating boom and control gate,
Namely coupled capacitor reduces, and effectively high coupling ratios mean that memory has relatively low operating voltage and power consumption, therefore, how
In the case of ensureing that device critical dimensions are constant, the coupled capacitor for being effectively increased flash is endeavoured always for those skilled in the art
The direction of research.
The content of the invention
The invention provides a kind of method of increase flash device gate capacitance, to be formed by prepared by floating boom with step
The two level floating boom of figure, can effectively increase flash coupled capacitor, and then can be effectively increased control gate capacitance, improve device
Energy.
The technical solution adopted by the present invention is：
A kind of method of increase flash device gate capacitance, wherein, comprise the following steps：
One substrate is provided, oxide layer, the first polysilicon layer and mask layer are sequentially depositing in the upper surface of the substrate；
It is sequentially etched in the mask layer, the first polysilicon layer and oxide layer to the substrate and forms shallow trench, deposition one
It is upper to the remaining mask layer to polish the packed layer full of the shallow trench and the upper surface of remaining mask layer is covered for packed layer
Surface, form fleet plough groove isolation structure；
After removing the remaining mask layer, a side wall is prepared in the side wall of fleet plough groove isolation structure exposure, and with
The side wall is that mask carries out ion implantation technology, to form an ion doped layer in remaining first polysilicon layer；
After removing the side wall, etching removes part remaining first polysilicon layer, to be formed with step cutting pattern
Floating boom；
Prepare a dielectric layer to be covered on the surface that the floating boom exposes completely, then at the dielectric layer disposed thereon
Two polysilicon layers are preparing control gate.
Above-mentioned method, wherein, the material of the mask layer is Si3N4。
Above-mentioned method, wherein, the oxide layer and the material of the packed layer are silica.
Above-mentioned method, wherein, after removing the remaining mask layer, deposit one layer of side wall film and the side wall film is entered
Row selective etch, to form the side wall.
Above-mentioned method, wherein, the material of the side wall film is SiN.
Above-mentioned method, wherein, the ion implantation technology is carried out using Ge ions.
Above-mentioned method, wherein, the dielectric layer is ono dielectric layer.
Above-mentioned method, wherein, the ono dielectric layer is prepared using thermal oxidation technology.
Above-mentioned method, wherein, the material of the ion doped layer is germanium silicon.
A kind of flash devices, wherein, the flash devices include a substrate, formed with stacking gate knot on the substrate
Structure, and the stacking gate structure includes floating boom, dielectric layer and control gate with step cutting pattern, the dielectric layer covers the floating boom
Upper surface, the control gate covers the upper surface of the dielectric layer；
Wherein, the floating boom includes a polysilicon layer and part covers the germanium-silicon layer of the polysilicon layer upper surface.
Above-mentioned device, wherein, there are a tunnel oxide, and the tunnel oxide between the stacking gate and the substrate
Material be silica.
Above-mentioned device, wherein, the dielectric layer is the ono dielectric layer prepared using thermal oxidation technology.
Above-mentioned device, wherein, the material of the control gate is polysilicon.
Due to present invention employs above technical scheme, passing through the polysilicon layer progress local ion injection to preparing floating boom
Afterwards and etch, finally preparing one has the two level floating boom of step cutting pattern, on the premise of device critical dimensions are not influenceed, can have
The contact area of effect increase dielectric layer and floating boom and control gate, this is beneficial to improve control gate capacitance；The two level floating boom formed simultaneously
Structure, which can also make to have between dielectric layer and floating boom and control gate, preferably to be contacted, and then lifts device performance.
Brief description of the drawings
By reading the detailed description made with reference to the following drawings to non-limiting example, the present invention and its feature, outside
Shape and advantage will become more apparent upon.The identical mark instruction identical part in whole accompanying drawings.Not deliberately proportionally
Draw accompanying drawing, it is preferred that emphasis is the purport of the present invention is shown.
Fig. 1-3 is the flow chart that in the prior art prepared by flash；
Fig. 4-10 is a kind of flow chart of the method for increase flash device gate capacitance provided by the invention；
Figure 11 is the partial structurtes sectional view of flash structures provided by the invention.
Embodiment
The embodiment of the present invention is further described below in conjunction with the accompanying drawings：
Shown in reference picture 4-10, the invention provides a kind of method of increase flash device gate capacitance, including following step
Suddenly：
Step S1：One substrate 1 is provided, is then sequentially prepared tunnel oxide 2, the first polysilicon in the upper surface of substrate 1
Layer 3 and mask layer 4, it is preferred that the material of tunnel oxide 2 is silica, and the material of mask layer 4 is Si3N4.Structure as shown in Figure 4.
Step S2：Etch to form shallow trench using Patternized technique, then prepare a packed layer and be filled shallow trench,
The remaining upper surface of mask layer 4 ' is polished to using chemical mechanical milling tech to stop, formation fleet plough groove isolation structure 5 (STI,
Shallow Trench Isolation).Preferably, the packed layer material is silica.Structure as shown in Figure 5.
Step S3：Remaining mask layer 4 ' is removed, as shown in Figure 6.
Step S4：Side wall 8 is formed in the side wall that fleet plough groove isolation structure 5 exposes, is concretely comprised the following steps：
Prepare one layer of side wall film first device upper surface is completely covered, it is preferred that depositing operation can be used to form one
Layer SiN layer is as side wall film；Then side wall film is performed etching using selective etch technique, finally isolated in shallow trench
The side wall that structure 5 exposes forms side wall 8, and causes the side wall 8 to be covered in the first polysilicon layer 3a top.In the reality of the present invention
Apply in example, by adjusting the reaction condition of etching, to adjust the width of the side wall 8 finally given.As shown in Figure 7.
Step S5：Ion implanting is carried out, an ion doped layer 3b is formed in the first polysilicon layer 3a.In the reality of the present invention
To apply in example, it is preferred to use Ge ions are injected, and the Ge ions of injection react with the first polysilicon layer 3a, and then first
The ion doped layer 3b that a material is SiGe is formed in polysilicon layer 3a.As shown in Figure 8.
Step S6：Side wall 8 is removed, and carries out etching technics and the first polysilicon layer 3a is performed etching, it is preferred that using etc.
Ion etch process performs etching.Due to foring the ion doped layer 3b of a SiGe in step S5, using plasma etching
When, the gas of etching is slower to the etch rate of SiGe, and very fast for the etch rate of polysilicon, through after a while
After etching, the polysilicon layer of ion doped layer 3b both sides is removed, and by material for SiGe ion doped layer 3b then lose compared with
It is small, it is newly formed structure shown in Fig. 9.As illustrated, after ion implanting and etching, form floating with step cutting pattern
Grid, it is by the remaining polysilicon layer 3c of bottom and common group of the ion doped layer 3b on remaining polysilicon layer 3c
Into,.
Step S7：Prepare a dielectric layer 6 to be covered on the surface of the exposure of floating boom completely, it is preferred that using thermal oxide
Technique forms an ono dielectric layer and covers the surface of two level floating boom；Then, then at dielectric layer 6 disposed thereon, one layer of second polycrystalline
Silicon layer 7 continues the forming step of follow-up flash cellular zones to prepare control gate.Because subsequent step is using existing
The usual technological means of technology, therefore will not be described here.
Due to using technique made above, finally preparing one has the two level floating boom of step cutting pattern, is not influenceing device
On the premise of critical size, the contact area of dielectric layer can be effectively increased, this is advantageous to improve control gate capacitance；Formed simultaneously
Two level FGS floating gate structure is also improved to have between dielectric layer and floating boom and control gate and preferably contacted, and then lifts device
Energy.
Further, because the floating boom formed in the present embodiment is by the polysilicon of bottom and the silicon on polysilicon
What germanium was collectively constituted, therefore both interfaces have preferably activation characteristic in sige formed with Si-SiGe hetero-junctions, doping
Lower gate resistance；Junction capacity caused by Si-SiGe hetero-junctions can further contribute to whole flash devices simultaneously
Electric capacity, there is good effect for the lifting of flash device performances.
Meanwhile present invention also offers a kind of flash device architectures, as shown in figure 11, including a base substrate 1 ', serving as a contrast
There is a pile stacked gate structure the top of bottom 1 ', there is a tunnel oxide 2 ' between stacking gate structure and substrate 1 '.The stacking gate from lower and
On include floating boom, dielectric layer 6 and control gate 7 successively；Wherein, floating boom is the two level floating boom with step cutting pattern, the floating boom be by
The polysilicon layer 3c of bottom and the germanium-silicon layer 3b on polysilicon layer 3c are collectively formed；Dielectric layer is using thermal oxide work
Skill prepares the ONO thin layers to be formed, and control gate material is polysilicon；
And shallow channel isolation area is provided with the substrate of stacking gate structure both sides, it is filled with silica medium,
Further, source class and drain electrode are additionally provided with the substrate of stacking gate structure both sides, because the figure is two dimension view, therefore in figure
Do not indicated.
Because the floating boom of the flash devices of offer of the invention is a two level floating boom with step shape, it is possible to increase with Jie
The contact area of matter layer, this is advantageous to increase control gate capacitance, so as to increase voltage coupling efficiency and coupled voltages, and reduces device
Part energy consumption, while existing device area will not also be impacted, while device area can be also further reduced using the technology,
To bring faster read/write efficiency.
Further, because the floating boom formed in the present embodiment is by the polysilicon of bottom and the silicon on polysilicon
Germanium is collectively constituted, therefore both interfaces are formed with Si-SiGe hetero-junctions, doping have in sige preferably activation characteristic and
Lower gate resistance；Junction capacity caused by Si-SiGe hetero-junctions can further contribute to the electricity of whole flash devices simultaneously
Hold, there is good effect for the lifting of flash device performances.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, wherein the equipment and structure be not described in detail to the greatest extent are construed as giving reality with the common mode in this area
Apply；Any those skilled in the art, without departing from the scope of the technical proposal of the invention, all using the disclosure above
Methods and technical content many possible changes and modifications are made to technical solution of the present invention, or be revised as equivalent variations etc.
Embodiment is imitated, this has no effect on the substantive content of the present invention.Therefore, every content without departing from technical solution of the present invention, foundation
The technical spirit of the present invention still falls within the present invention to any simple modifications, equivalents, and modifications made for any of the above embodiments
In the range of technical scheme protection.
Claims (9)
- A kind of 1. method of increase flash device gate capacitance, it is characterised in that comprise the following steps：One substrate is provided, oxide layer, the first polysilicon layer and mask layer are sequentially depositing in the upper surface of the substrate；It is sequentially etched the part oxide layer, the first polysilicon layer and mask layer to the substrate and forms shallow trench, deposition one is filled out Layer is filled full of the shallow trench and covers the upper surface of remaining mask layer, polishes the packed layer to the upper table of the remaining mask layer Face, form fleet plough groove isolation structure；After removing the remaining mask layer, a side wall is prepared in the side wall of fleet plough groove isolation structure exposure, and with described Side wall is that mask carries out ion implantation technology, to form an ion doped layer in remaining first polysilicon layer；After removing the side wall, and etch and remove the polysilicon layer of some residual first, form the floating boom with step cutting pattern；Prepare a dielectric layer to be covered on the surface that the floating boom exposes completely, then at the dielectric layer disposed thereon more than second Crystal silicon layer is preparing control gate.
- 2. the method as described in claim 1, it is characterised in that the material of the mask layer is Si3N4。
- 3. the method as described in claim 1, it is characterised in that the material of the oxide layer and the packed layer is oxidation Silicon.
- 4. the method as described in claim 1, it is characterised in that after removing the remaining mask layer, it is thin first to deposit one layer of side wall Film is covered in device upper surface, then carries out selective etch to the side wall film, forms the side wall.
- 5. the method as described in claim 1, it is characterised in that the material of the side wall film is SiN.
- 6. the method as described in claim 1, it is characterised in that the ion implantation technology is carried out using Ge ions.
- 7. the method as described in claim 1, it is characterised in that the dielectric layer is ono dielectric layer.
- 8. method as claimed in claim 7, it is characterised in that the ono dielectric layer is prepared using thermal oxidation technology.
- 9. the method as described in claim 1, it is characterised in that the material of the ion doped layer is germanium silicon.
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