CN104766822B - A kind of manufacturing method of semiconductor devices - Google Patents
A kind of manufacturing method of semiconductor devices Download PDFInfo
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- CN104766822B CN104766822B CN201410005283.9A CN201410005283A CN104766822B CN 104766822 B CN104766822 B CN 104766822B CN 201410005283 A CN201410005283 A CN 201410005283A CN 104766822 B CN104766822 B CN 104766822B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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Abstract
The present invention provides a kind of manufacturing method of semiconductor devices, including：Semiconductor substrate with first area and second area is provided; it is formed with high k dielectric layer, the protective layer of high k dielectric layer and the dummy gate structure of sacrificial gate dielectric layer including stacking gradually from bottom to top on a semiconductor substrate; wherein, first area is NMOS area, and second area is PMOS areas；Or first area is PMOS areas, second area is NMOS area；Three steps is divided to implement the sacrificial gate dielectric layer that etching removal is located in the dummy gate structure on second area, formation groove；Metal gate structure is formed in the trench.According to the present invention, three steps is divided to implement etching, removal is located at after the sacrificial gate dielectric layer on second area, the side wall profile being in contact with the sacrificial gate dielectric layer on first area of the groove formed is vertical, does not interfere with the follow-up filling for implementing workfunction layers in the trench.
Description
Technical field
The present invention relates to semiconductor fabrication process, during in particular to a kind of implementation post tensioned unbonded prestressed concrete (gate-last) technique
The method for removing the sacrificial gate dielectric layer in dummy gate structure.
Background technology
With the continuous reduction of feature sizes of semiconductor devices, traditional nitrogen oxygen is replaced with high k dielectric layer/metal-gate structures
SiClx or silicon oxide dielectric layer/polysilicon grating structure be considered as solving traditional grid structure problem encountered it is main even
It is unique method, traditional grid structure problem encountered mainly includes grid leak electricity, polysilicon depletion and by thin oxide gate
Boron penetration caused by silicon dielectric layer.
For having the transistor arrangement compared with high technology node, the high k- metal gate process is usually post tensioned unbonded prestressed concrete
(gate-last) technique, typical implementation process include：First, dummy gate structure, the puppet are formed on a semiconductor substrate
Gate structure is made of boundary layer, high k dielectric layer, coating and sacrificial gate dielectric layer from bottom to top；Then, in the pseudo- grid
The both sides of pole structure form gate pitch wall construction, the sacrificial gate dielectric layer in the dummy gate structure are removed later, described
A groove is left between gate pitch wall construction；Then, workfunction layers are sequentially depositing in the groove
（workfunction metal layer）, barrier layer（barrier layer）And soakage layer（wetting layer）；Finally
The filling of metal gate material is carried out, to form metal gate structure on the coating.
For as shown in Figure 1A formed the semiconductor device structure of dummy gate structure for, need to be by shallow trench isolation
It is respectively formed and is included with different work functions metal layer on NMOS area and PMOS areas in the substrate 100 that structure 101 separates
Metal gate structure, therefore, generally use remove the sacrificial gate in the dummy gate structure formed in NMOS area and PMOS areas respectively
The technique of electrode layer 103 is described comprising the metal gate structure with different work functions metal layer to be formed.It is located in removal
After sacrificial gate dielectric layer 103 in PMOS areas, the groove 104 of formation with the sacrificial gate dielectric layer 103 on NMOS area
The side wall profile being in contact is not vertical, and usually bowl-shape in as shown in Figure 1B, this bowl-like profile will influence subsequently to exist
The implementation of workfunction layers is filled in groove 104, and then influences the performance of device.
It is, therefore, desirable to provide a kind of method, to solve the above problems.
Invention content
In view of the deficiencies of the prior art, the present invention provides a kind of manufacturing method of semiconductor devices, including：There is provided has the
One region and the Semiconductor substrate of second area, are formed with the height including stacking gradually from bottom to top on the semiconductor substrate
The dummy gate structure of k dielectric layer, the protective layer of the high k dielectric layer and sacrificial gate dielectric layer；Three steps is divided to implement etching removal position
Sacrificial gate dielectric layer in the dummy gate structure on the second area forms groove；Metal gate is formed in the trench
Pole structure.
Further, described point of three steps are implemented to etch and be included：Implement the first etching, be located on the second area with removal
The major part of sacrificial gate dielectric layer in dummy gate structure；Implement the second etching, to remove the residual of the sacrificial gate dielectric layer
Part；Implement third etching, to remove etch residue nitride layer caused by first etching and the described second etching.
Further, described first be etched under high pressure with HBr and O2Dry etching for basic etching gas.
Further, the technological parameter of first etching is：The flow 50-500sccm, O of pressure 40-80mTorr, HBr2
Flow 2-10sccm, source power 100-2000W, bias voltage 50-300V.
Further, described second be etched under low pressure with HBr and O2Dry etching for basic etching gas.
Further, the technological parameter of second etching is：The flow 50-500sccm, O of pressure 2-10mTorr, HBr2
Flow 2-10sccm, source power 100-2000W, bias voltage 50-300V, the pulse frequency 20-150Hz of bias voltage,
During the pulse ripple, imported to etching operation room the plasma of the etching gas process be in open, shutdown
In repetitive cycling state, wherein, the 10%-90% of the time for accounting for the etching process total time of the opening.
Further, the third is etched to Siconi etchings, and the Siconi etchings are with NH3And NF3Based on etch gas
Body.
Further, the metal gate structure includes the workfunction layers stacked from bottom to top and metal gates material
The bed of material.
Further, it further includes between the workfunction layers and the metal gate material layer and stacks from bottom to top
Barrier layer and soakage layer.
Further, the first area is NMOS area, and the second area is PMOS areas；Or the first area is
PMOS areas, the second area are NMOS area.
According to the present invention, point three steps implement etching, and removal is located at after the sacrificial gate dielectric layer on the second area, shape
Into the groove the side wall profile being in contact with the sacrificial gate dielectric layer on the first area be it is vertical, will not
Influence the follow-up filling for implementing workfunction layers in the trench.
Description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Figure 1A is the schematic cross sectional view for forming the device after dummy gate structure on substrate using the prior art；
Figure 1B is the sacrificial gate in the dummy gate structure in the PMOS areas removed using prior art as shown in Figure 1A
The side wall profile being in contact with the sacrificial gate dielectric layer in the dummy gate structure on NMOS area of the groove formed after electrode layer is in
Bowl-shape schematic cross sectional view；
The device that the step of Fig. 2A-Fig. 2 D is implement according to the method for exemplary embodiment of the present successively obtains respectively
Schematic cross sectional view；
Fig. 3 A- Fig. 3 D be correspond respectively to Fig. 2A-Fig. 2 D the device obtained along the trend in PMOS areas schematically cut open
Face figure；
Fig. 4 is flow chart the step of implementation successively according to the method for exemplary embodiment of the present.
Specific embodiment
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to illustrate proposition of the present invention
Implement post tensioned unbonded prestressed concrete technique when removal dummy gate structure in sacrificial gate dielectric layer method.Obviously, execution of the invention is not
It is defined in the specific details that the technical staff of semiconductor applications is familiar with.Presently preferred embodiments of the present invention is described in detail as follows, so
And other than these detailed descriptions, the present invention can also have other embodiment.
It should be understood that it when the term " comprising " and/or " including " is used in this specification, indicates described in presence
Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of other one or more features, entirety,
Step, operation, element, component and/or combination thereof.
[exemplary embodiment]
With reference to Fig. 2A-Fig. 2 D and Fig. 3 A- Fig. 3 D, it is real successively that method according to an exemplary embodiment of the present invention is shown
What the step of applying obtained respectively moves towards and corresponding walking along PMOS areas along the sacrificial gate dielectric layer in element layout
To the schematic cross sectional view of obtained device.
First, as shown in Fig. 2A and Fig. 3 A, Semiconductor substrate 200 is provided, the constituent material of Semiconductor substrate 200 can be adopted
With undoped monocrystalline silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator（SOI）Deng.As an example, in the present embodiment,
The constituent material of Semiconductor substrate 200 selects monocrystalline silicon.Isolation structure 201 is formed in Semiconductor substrate 200, as showing
Example, isolation structure 201 be shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS) isolation structure, isolation structure 201
Semiconductor substrate 200 is divided for NMOS area and PMOS areas.Various traps (well) structure is also formed in Semiconductor substrate 200, is
Simplification, it is illustrated that in omitted.
Dummy gate structure 201 ' is respectively formed in the NMOS area of Semiconductor substrate 200 and PMOS areas, as an example, pseudo- grid
Pole structure 201 ' includes the high k dielectric layer 202 stacked gradually from bottom to top and sacrificial gate dielectric layer 203.High k dielectric layer 202
Material includes hafnium oxide, hafnium silicon oxide, nitrogen oxidation hafnium silicon, lanthana, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, oxidation
Barium strontium titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide etc., particularly preferably hafnium oxide, zirconium oxide or aluminium oxide.Sacrificial gate electricity
The material of pole layer 203 includes polysilicon.It should be noted that in dummy gate structure 201 ', high the lower of k dielectric layer 202 can
To form boundary layer, the effect for forming boundary layer is the interfacial characteristics improved between high k dielectric layer 202 and Semiconductor substrate 200,
The material of boundary layer includes Si oxide（SiOx）；High k dielectric layer 202 can be formed above protective layer, form protective layer
Effect is the metal gate material in the metal gate structure for inhibiting to be subsequently formed（Usually aluminium）Into high k dielectric layer 202
Diffusion, the material of protective layer include titanium nitride or tantalum nitride.To put it more simply, it is not shown in figure the boundary layer and the protection
Layer.
The sacrificial gate dielectric layer 203 being along in element layout due to Fig. 2A and its attached drawing to continue moves towards what is obtained
Device profile map, therefore, in the side wall construction 204 and on semiconductor substrate 200 that the both sides of dummy gate structure 201 ' are formed
The contact etch stop layer 205 and interlayer dielectric layer 206 of the covering side wall construction 204 sequentially formed are not shown.Due to figure
3A and its attached drawing to continue be correspond respectively to Fig. 2A and its attached drawing that continues shown by device in along PMOS areas trend
The schematic cross sectional view of obtained device, therefore, side wall construction 204, contact etch stop layer 205 and interlayer dielectric layer 206
It is shown in Fig. 3 A and its attached drawing to continue.
Then, as seen in figs. 2 b and 3b, removal is located at the altered sacrificial gate electrode in the dummy gate structure 201 ' in PMOS areas
Layer 203 forms groove 207 in PMOS areas.The processing step for implementing the removal includes：It is formed on semiconductor substrate 200
Patterned photoresist layer, to cover the dummy gate structure 201 ' being located on NMOS area；Using the patterned photoresist layer as
Mask, etching is located at the sacrificial gate dielectric layer 203 in the dummy gate structure 201 ' in PMOS areas, until exposing high k dielectric layer 202
Until, it should be noted that when forming matcoveredn in high k dielectric layer 202, the exposing protective layer that is etched through is
Only.In the present embodiment, it is described to sacrificial gate dielectric layer 203 be etched under high pressure with HBr and O2For basic etching gas
Dry etching, technological parameter is：The flow 50-500sccm, O of pressure 40-80mTorr, HBr2Flow 2-10sccm,
Source power 100-2000W, bias voltage 50-300V.After implementing the etching, as shown in Figure 2 B, groove 207 with positioned at
Etch residue nitride layer 208 is formed on the side wall that sacrificial gate dielectric layer 203 on NMOS area is in contact；As shown in Figure 3B, in place
There is the residual of sacrificial gate dielectric layer 203 in the place of the side wall construction 204 in PMOS areas and high 202 interfaces of k dielectric layer.
Then, as shown in Fig. 2 C and Fig. 3 C, etching removes the residual of the sacrificial gate dielectric layer 203.In the present embodiment,
It is described to sacrificial gate dielectric layer 203 it is remaining be etched under low pressure with HBr and O2For the dry etching of basic etching gas,
Its technological parameter is：The flow 50-500sccm, O of pressure 2-10mTorr, HBr2Flow 2-10sccm, source power 100-
2000W, bias voltage 50-300V, the pulse frequency 20-150Hz of bias voltage during the pulse ripple, are grasped to etching
The process for making the plasma that room imports the etching gas is in the repetitive cycling state of unlatching, shutdown, wherein, it is described to open
Open the 10%-90% of the time for accounting for the etching process total time of state.After implementing the etching, as shown in Figure 2 C,
The etch residue nitride layer 208 formed on the side wall being in contact with the sacrificial gate dielectric layer 203 on NMOS area of groove 207 is not
It is removed.
Then, as shown in Fig. 2 D and Fig. 3 D, etching removal etch residue nitride layer 208.In the present embodiment, described pair of etching
Layers of residue 208 is etched to Siconi etchings, and the Siconi etchings are with NH3And NF3For basic etching gas.
So far, the processing step that method according to an exemplary embodiment of the present invention is implemented is completed, next, can pass through
Subsequent technique completes the making of entire semiconductor devices, including：Metal gate structure is formed in PMOS areas, as an example, golden
Belong to gate structure and include the workfunction layers stacked from bottom to top and metal gate material layer, wherein, workfunction metal
Layer include one or more layers metal or metallic compound, constituent material be suitable for PMOS device metal material, including ruthenium,
Palladium, platinum, tungsten and its alloy further include carbide, nitride of above-mentioned metallic element etc.；The material of metal gate material layer includes
Tungsten or aluminium.Workfunction layers are formed using atom layer deposition process or physical gas-phase deposition, using chemical vapor deposition
Technique or physical gas-phase deposition form metal gate material layer.Then, chemical mechanical grinding is performed to grind above layers
Material, the grinding are terminated when exposing the sacrificial gate dielectric layer 203 being located on NMOS area.It should be noted that in work function
May be used between metal layer and metal gate material layer atom layer deposition process or physical gas-phase deposition formed from lower and
It is upper to stack the barrier layer formed and soakage layer, wherein, the material on barrier layer includes tantalum nitride or titanium nitride；The material packet of soakage layer
Include titanium or titanium-aluminium alloy.
According to the present invention, point three steps implement etching, and removal is located at after the sacrificial gate dielectric layer 203 in PMOS areas, is formed
The side wall profile being in contact with the sacrificial gate dielectric layer 203 on NMOS area of groove 207 be vertical, after not interfering with
Continue the filling for implementing workfunction layers in groove 207.
It should be noted that for the device architecture as shown in Fig. 2A, following process sequences can also be performed to realize this
What invention proposed implements the method for the sacrificial gate dielectric layer in removal dummy gate structure during post tensioned unbonded prestressed concrete technique, including：Using above-mentioned
The sacrificial gate dielectric layer 203 that the method removal that three steps implement etching is divided to be located on NMOS area；In the groove formed on NMOS area
Another metal gate structure is formed, as an example, another metal gate structure includes another work content stacked from bottom to top
Number metal layer and another metal gate material layer, wherein, another workfunction layers include one or more layers metal or metallization
Object is closed, constituent material is the metal material suitable for NMOS, including titanium, tantalum, aluminium, zirconium, hafnium and its alloy, further includes above-mentioned gold
Belong to carbide, nitride of element etc.；The material of another metal gate material layer includes tungsten or aluminium.Using atom layer deposition process
Or physical gas-phase deposition forms another workfunction layers, using chemical vapor deposition method or physical gas-phase deposition
Form another metal gate material layer.Then, chemical mechanical grinding is performed to grind above layers material, and the grinding is being exposed
It is terminated during sacrificial gate dielectric layer 203 in PMOS areas.Another workfunction layers and another metal gate material layer it
Between may be used atom layer deposition process or physical gas-phase deposition another barrier layer for stacking from bottom to top of formation and
Another soakage layer, wherein, the material on another barrier layer includes tantalum nitride or titanium nitride；The material of another soakage layer includes titanium or titanium
Aluminium alloy.
With reference to Fig. 4, the flow chart of method according to an exemplary embodiment of the present invention is shown, it is whole for schematically illustrating
The flow of a manufacturing process.
In step 401, the Semiconductor substrate with first area and second area is provided, is formed on a semiconductor substrate
There is the dummy grid knot of high k dielectric layer, the protective layer of high k dielectric layer and sacrificial gate dielectric layer including stacking gradually from bottom to top
Structure, wherein, first area is NMOS area, and second area is PMOS areas；Or first area be PMOS areas, second area NMOS
Area；
In step 402, three steps is divided to implement the sacrificial gate electricity that etching removal is located in the dummy gate structure on second area
Pole layer, forms groove；
In step 403, metal gate structure is formed in the trench.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (9)
1. a kind of manufacturing method of semiconductor devices, including：
Semiconductor substrate with first area and second area is provided, be formed on the semiconductor substrate including from lower and
On the high k dielectric layer, the protective layer of the high k dielectric layer and the dummy gate structure of sacrificial gate dielectric layer that stack gradually；
Three steps is divided to implement the sacrificial gate dielectric layer that etching removal is located in the dummy gate structure on the second area, formation ditch
Slot,
Wherein, described point of three steps are implemented to etch and be included：Implement the first etching, to remove the dummy grid being located on the second area
The major part of sacrificial gate dielectric layer in structure；Implement the second etching, to remove the residual fraction of the sacrificial gate dielectric layer；It is real
Third etching is applied, to remove etch residue nitride layer caused by first etching and the described second etching；
Metal gate structure is formed in the trench.
2. according to the method described in claim 1, it is characterized in that, described first be etched under high pressure with HBr and O2Based on
The dry etching of etching gas.
3. according to the method described in claim 2, it is characterized in that, the technological parameter of first etching is：Pressure 40-
The flow 50-500sccm, O of 80mTorr, HBr2Flow 2-10sccm, source power 100-2000W, bias voltage 50-300V.
4. according to the method described in claim 1, it is characterized in that, described second be etched under low pressure with HBr and O2Based on
The dry etching of etching gas.
5. according to the method described in claim 4, it is characterized in that, the technological parameter of second etching is：Pressure 2-
The flow 50-500sccm, O of 10mTorr, HBr2Flow 2-10sccm, source power 100-2000W, bias voltage 50-300V,
During the pulse ripple, the etching gas is imported to etching operation room by the pulse frequency 20-150Hz of bias voltage
The process of plasma, which is in, opens, in the repetitive cycling state of shutdown, wherein, the opening accounts for described the total time
The 10%-90% of the time of two etching processes.
6. according to the method described in claim 1, it is characterized in that, the third is etched to Siconi etchings, the Siconi
Etching is with NH3And NF3For basic etching gas.
7. according to the method described in claim 1, it is characterized in that, the metal gate structure includes stacking from bottom to top
Workfunction layers and metal gate material layer.
8. the method according to the description of claim 7 is characterized in that the workfunction layers and the metal gate material layer
Between further include the barrier layer stacked from bottom to top and soakage layer.
9. according to the method described in claim 1, it is characterized in that, the first area is NMOS area, the second area is
PMOS areas；Or the first area is PMOS areas, the second area is NMOS area.
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| CN102956455A (en) * | 2011-08-19 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor devices |
| CN103390547A (en) * | 2012-05-08 | 2013-11-13 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure with metal gate electrode layers |
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| US9177870B2 (en) * | 2011-12-16 | 2015-11-03 | Taiwan Semiconductor Manufacturing Company Ltd. | Enhanced gate replacement process for high-K metal gate technology |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102956455A (en) * | 2011-08-19 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor devices |
| CN103390547A (en) * | 2012-05-08 | 2013-11-13 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure with metal gate electrode layers |
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