CN104752323B - A kind of semiconductor devices and preparation method thereof - Google Patents
A kind of semiconductor devices and preparation method thereof Download PDFInfo
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- CN104752323B CN104752323B CN201310743149.4A CN201310743149A CN104752323B CN 104752323 B CN104752323 B CN 104752323B CN 201310743149 A CN201310743149 A CN 201310743149A CN 104752323 B CN104752323 B CN 104752323B
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Abstract
The present invention relates to a kind of semiconductor devices and preparation method thereof, methods described includes：Semiconductor substrate is provided, on the semiconductor substrate formed with interlayer dielectric layer, there is space formed with contact hole and photo-etching mark hole, the photo-etching mark hole in the interlayer dielectric layer；Sacrificial material layer, to be filled up completely with the space；Protective layer is formed on the interlayer dielectric layer and the sacrificial material layer；Silicon hole is formed in the Semiconductor substrate and the interlayer dielectric layer；The protective layer is removed, to expose the sacrificial material layer；The sacrificial material layer is removed, to expose the space.The present invention proposes to use a C to prepare as silicon hole（TSV VIA middle）CT protective layer in technique, a C have more preferable Step Coverage ability, can be completely removed compared to SIN, so as to not influence follow-up the first metal layer photoetching（M1photo）Contraposition, efficiently solve OVL and measure problem.
Description
Technical field
The present invention relates to semiconductor applications, in particular it relates to a kind of semiconductor devices and preparation method thereof.
Background technology
In consumer electronics field, multifunctional equipment is increasingly liked by consumer, compared to the simple equipment of function,
Multifunctional equipment manufacturing process will be more complicated, than the chip if desired for integrated multiple difference in functionalitys in circuit version, thus go out
3D integrated circuits are showed（Integrated circuit, IC）Technology, 3D integrated circuits（Integrated circuit, IC）Quilt
A kind of system-level integrated morphology is defined as, multiple chips are stacked in vertical plane direction, so as to save space, each chip
Marginal portion can draw multiple pins as needed, utilize these pins as needed, it would be desirable to the chip of interconnection
Interconnected by metal wire, but aforesaid way still has many deficiencies, for example stacked chips quantity is more, and between chip
Annexation it is more complicated, then just may require that using more metal lines, final wire laying mode is more chaotic, Er Qiehui
Volume is caused to increase.
Therefore, at present in the 3D integrated circuits（Integrated circuit, IC）Silicon hole is mostly used in technology
（Through Silicon Via, TSV）, silicon hole is a kind of perpendicular interconnection for penetrating Silicon Wafer or chip, TSV can storehouse it is more
Piece chip, duck eye is drilled out in chip（Processing procedure can be divided into first drilling and rear two kinds of drilling, Via Fist, Via Last again）, the bottom of from
Portion is packed into metal, is drilled on Silicon Wafer in a manner of etching or laser（via）, then with the conductive material such as thing such as copper, polysilicon, tungsten
Matter is filled up.So as to realize the interconnection between different silicon chips.
3D IC be by the processor chip of former bare crystalline size, programmable logic lock (FPGA) chip, memory chip,
RF chip (RF) or optoelectronic wafers, directly overlapping, and through TSV drilling connections after thinning.In the three-dimensional overlapping skills of 3D IC
Under the assistance of key technology/encapsulation spare part such as art, silicon hole (TSV), intermediate plate (Interposer), enter in limited areal
The maximum chip superposition of row and integration, further reduce SoC chip areas/encapsulation volume and lift chip communication efficiency.
At present, during the combination of two wafers, i.e., after FEOL is completed, before BEOL, usually formed
Contact hole（Contact）After technique, a kind of technology of embedded TSV through hole, so in TSV through hole technical process, CT levels
Protect particularly important, be used as contact hole by depositing SiN（CT）Protective layer, then carry out TSV techniques.
Specifically as illustrated by figs. 1 a-1f, with reference first to Fig. 1 a, there is provided Semiconductor substrate 101, in the Semiconductor substrate
The various components in front end of line are completed on 101, then interlevel dielectric deposition 102 on the semiconductor substrate, in institute
State and contact hole is formed in interlayer dielectric layer（contact）Level, wherein in contact hole（contact）Mainly there is contact hole in level
Two kinds of patterns（pattern）, one type is the pattern of contact hole 103, as the contact hole of interconnection, generally with less size
（It is 0.24 in 0.18 processing procedure）, another is as photo-etching mark pattern（photo mark）104, generally with larger chi
It is very little（Generally higher than 1um）, CT holes as photo-etching mark when metal is filled among can leave larger space 10.In shape
TSV techniques, reference picture 1b, on the interlayer dielectric layer 102, the pattern of the contact hole 103 are performed after into the contact hole
Upper, photo-etching mark pattern（photo mark）Protective layer 105 is formed in 104, at present in semiconductor processing, usually using CVD
SiN is deposited as protective layer, method and cost are more ripe simple, the Cu-Cu combined process in wafer combination（TSV VIA
middle）In be also typically used as CT protective layer and TSVCMP stop-layer, but because having for the SiN is poor
Step is filled（step coverage）Ability, in photo-etching mark pattern（photo mark）Region can not form good filling,
Still there is larger space；Pattern the interlayer dielectric layer 102 and form silicon hole groove, as illustrated in figure 1 c, wherein the protection
105 pairs of CT regions of layer form good protection；Then silicon hole separation layer 106 is deposited（TSV isolation）, the silicon
There is through hole separation layer 106 good step to fill（step coverage）Ability, therefore, the photo-etching mark bore region（CT
photo mark）In space be completely filled, as shown in Figure 1 d, then fill conductive material in the silicon hole groove,
And the protective layer 105 is planarized to, the structure of silicon hole is formed, as shown in Fig. 1 e-1f；The protective layer 105 is finally removed,
But photo-etching mark bore region after removing（CT photo mark）Middle silicon hole absciss layer 106（Oxide）Residual still can not be by
Remove, make follow-up the first metal layer photoetching（M1photo）Processing procedure contraposition CT becomes difficult, and is unfavorable for being aligned（OVL）Measurement.
In the prior art usually using CVD deposition SIN as protective layer, method and cost are more ripe simple,
Also CT protective layer and the stop-layer of TSV planarizations are typically used as in TSV VIA middle techniques, but due to CT layers
Photo-etching mark is used as in secondary（photo mark）CT patterns and as interconnection aperture of contact hole there is great CD differences, lead
Causing can be in photo-etching mark during TSV（photo mark）CT patterns in produce compared with multimedium remain, this is in TSV VIA
Middle techniques SIN solves as protective layer certainty problems faced temporarily without good scheme.
In addition, the protective layer using SIN as CT in TSV technical process can bring some technological problemses, make follow-up M1 light
Scribe journey photoetching（photo）It can not align and be aligned（OVL）It can not measure, how solve the problem, be that current TSV techniques face
Larger challenge.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in specific embodiment part
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed
Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
The present invention is in order to overcome the problem of presently, there are, there is provided a kind of preparation method of semiconductor devices, including：
Semiconductor substrate is provided, on the semiconductor substrate formed with interlayer dielectric layer, shape in the interlayer dielectric layer
Into having contact hole and photo-etching mark hole, the photo-etching mark hole has space；
Sacrificial material layer, to be filled up completely with the space；
Protective layer is formed on the interlayer dielectric layer and the sacrificial material layer；
Silicon hole is formed in the Semiconductor substrate and the interlayer dielectric layer；
The protective layer is removed, to expose the sacrificial material layer；
The sacrificial material layer is removed, to expose the space.
Preferably, the sacrificial material layer selects amorphous carbon.
Preferably, the method for filling the space is：
The sacrificial material layer is deposited in the interlayer dielectric layer and the space, to cover the interlayer dielectric
Layer, and fill the space；
Planarisation step is performed, to remove the sacrificial material layer in the interlayer dielectric layer surface.
Preferably, the method for forming the silicon hole is：
The mask layer of patterning is formed on the protective layer；
Using the mask layer as protective layer, the interlayer dielectric layer and the Semiconductor substrate described in mask etch, with
Form silicon hole groove；
Remove the mask layer；
Separation layer is formed in the silicon hole groove；
The silicon hole groove is filled from conductive material；
Planarisation step is performed, the conductive material is planarized to the protective layer, to form the silicon hole.
Preferably, the method for filling the silicon hole groove is：
Diffusion impervious layer is formed on the separation layer；
The Seed Layer of metal is formed on the diffusion impervious layer；
From electrochemistry electric plating method deposited metal to fill the silicon hole groove.
Preferably, remove the sacrificial material layer from ashing method.
Preferably, the protective layer selects SiN layer；
The interlayer dielectric layer selects oxide skin(coating).
Preferably, the method for forming the contact hole and the photo-etching mark hole is：
The interlayer dielectric layer is patterned, to form contact hole groove and photo-etching mark hole groove；
Conductive material is deposited, to be filled up completely with the contact hole groove, forms contact hole, while be partially filled with the photoetching
Index aperture groove, conductive material is formed in the side wall of photo-etching mark hole groove, the photoetching with formation center with space
Index aperture.
Present invention also offers the semiconductor devices that a kind of above-mentioned method is prepared, the institute in the semiconductor devices
The center for stating photo-etching mark hole has space.
The present invention proposes to use a-C to prepare as silicon hole（TSV VIA middle）CT protective layer in technique, a-C make
For a kind of protective layer and sacrifice layer well, the method for CVD deposition can be used to be covered in the surface of wafer, and compare SIN
, can be to photo-etching mark hole 204 with more preferable Step Coverage ability（CT photo mark）The cavity in region forms good
Filling, makes silicon hole medium（TSV isolation）Photo-etching mark hole 204 can not be deposited on（CT photo mark）Region, institute
With CT surfaces silicon hole medium（TSV isolation）It can be completely removed, so as to not influence follow-up the first metal layer photoetching
（M1photo）Contraposition, efficiently solve OVL and measure problem.
In addition, a-C compares SIN, during CMP and silicon hole medium（oxide）Between have higher selection ratio, can be with
More preferable protection is formed to CT.
In addition, a-C can use ashing（Asher）Mode removes, and a-C is easier to remove compared to SIN, clean and it is not easy
Produce residue.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the device of the present invention and principle.In the accompanying drawings,
Fig. 1 a-1g are the preparation process schematic diagram of the TSV of semiconductor devices described in prior art；
Fig. 2 a-2h are the preparation process schematic diagram of the TSV of semiconductor devices described in the embodiment of the present invention；
Fig. 3 is the specifically TSV of semiconductor devices described in embodiment of the present invention one preparation technology flow chart.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
In order to thoroughly understand the present invention, detailed description will be proposed in following description, to illustrate of the present invention half
The preparation method of conductor device.Obviously, execution of the invention be not limited to semiconductor applications technical staff be familiar with it is special
Details.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, the present invention can also have it
His embodiment.
It should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to the exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative
Intention includes plural form.Additionally, it should be understood that when using term "comprising" and/or " comprising " in this manual
When, it, which is indicated, has the feature, entirety, step, operation, element and/or component, but does not preclude the presence or addition of one or more
Individual other features, entirety, step, operation, element, component and/or combinations thereof.
Now, the exemplary embodiment according to the present invention is more fully described with reference to the accompanying drawings.However, these exemplary realities
Applying example can be implemented with many different forms, and should not be construed to be limited solely to the embodiments set forth herein.Should
Understand be to provide these embodiments be in order that disclosure of the invention is thoroughly and complete, and by these exemplary implementations
The design of example is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, the thickness in layer and region is exaggerated
Degree, and make identical element is presented with like reference characters, thus description of them will be omitted.
The present invention is in order to solve problem present in current semiconductor devices preparation process, there is provided a kind of new preparation side
Method, below in conjunction with the accompanying drawings 2a-2h methods described is further described.
First, step 201 is performed, there is provided Semiconductor substrate 201, formed with various members in the Semiconductor substrate 201
Device.
Specifically, reference picture 2a, in this step, the Semiconductor substrate 201 can be in the following material being previously mentioned
At least one：Silicon, silicon-on-insulator（SOI）, be laminated silicon on insulator（SSOI）, be laminated SiGe on insulator（S-
SiGeOI）And germanium on insulator SiClx（SiGeOI）Deng.Other active areas or active device are could be formed with the substrate
Part, it will not be repeated here.
Step 202 is performed, interlayer dielectric layer 202, the interlayer dielectric layer 202 are formed in the Semiconductor substrate 201
In formed with contact hole 203 and photo-etching mark hole 204, there is space in the photo-etching mark hole 204.
Specifically, as shown in Figure 2 a, interlayer dielectric layer 202 is formed first in the Semiconductor substrate 201, then pattern
Change interlayer dielectric layer 202 to form contact hole opening and photo-etching mark hole opening, Ran Hou in the interlayer dielectric layer 202
Conductive material is filled in the contact hole opening, forms the contact hole 203, while is partially filled with the photo-etching mark hole 204,
It is partially filled with after the photo-etching mark hole 204, forms conductive material layer in the side wall in the photo-etching mark hole 204, but
Larger space is still had in the photo-etching mark hole 204.
Perform step 203, the sacrificial material layer 205 on the interlayer dielectric layer 202, to fill the photo-etching mark
Space in hole 204.
Specifically, as shown in Figure 2 b, sacrificial material layer 205, with the sky being filled up completely with the photo-etching mark hole 204
Gap, the expendable material is preferably to have good step covering power in this step（step coverage）, to guarantee
The space in the photo-etching mark hole 204 is filled up completely with, using the protective layer as the photo-etching mark hole 204.
Preferably, the sacrificial material layer 205 selects amorphous carbon in this step（a-C）, the amorphous carbon（a-
C）As photo-etching mark hole 204（CT photo mark）Locality protection material, is eventually completely removed, and a-C compares SIN
Easily remove, and do not have residual（residue）The problem of
In addition, amorphous carbon（a-C）With preferable Step Coverage ability（step coverage）, can effectively fill out
Fill in the space in photo-etching mark hole 204, and removed in follow-up process, efficiently solve OVL and measure problem.In addition,
A-C compares SIN, during CMP and silicon hole medium（oxide）Between have higher selection ratio, CT can be formed more preferably
Protection；Moreover, a-C can use ashing（Asher）Mode removes, clean and it does not allow to be also easy to produce residue.
In of the invention one specifically embodiment, the amorphous carbon（a-C）Formed by CVD method, it is described
Reacting gas is hydrocarbon source（Hydrocarbon source), it may include gas phase hydrocarbon compound (preferably propylene；), C3H6 and/or
The admixture of gas of steam and carrier gas including liquid-phase hydrocarbon compounds.Between reaction temperature is maintained into about 100 DEG C-about 450 DEG C,
And between preferably about 300 DEG C-about 450 DEG C, to reduce the absorption coefficient of the film of generation, it is possible to deposited from processing gas
a-C:H layers.The processing further comprises chamber pressure maintaining about 2 supports（Torr) between -8 supports.The flow velocity in hydrocarbon source between
Between about 200sccm- about 5000sccm, the flow velocity of carrier gas is between about 300sccm~about 600sccm.
Step 205 is performed, the sacrificial material layer 205 is planarized to the interlayer dielectric layer 202, to remove the interlayer
The sacrificial material layer 205 on the surface of dielectric layer 202.
Specifically, as shown in Figure 2 b, flattening method conventional in field of semiconductor manufacture can be used in this step
To realize the planarization on surface.The non-limiting examples of the flattening method include mechanical planarization method and chemically mechanical polishing
Flattening method.Chemically mechanical polishing flattening method is more often used.
After planarisation steps, the sacrificial material layer 205 on the surface of interlayer dielectric layer 202 is removed, is retained
Sacrificial material layer 205 in the gap.
Step 206 is performed, protective layer 206 is formed on the interlayer dielectric layer 202 and the sacrificial material layer 205.
Specifically, as shown in Figure 2 c, the protective layer 206 can select metal or the hard of oxide to cover in this step
Film layer, the present invention one specifically protective layer 206 described in embodiment select SiN, but be not limited to that SiN, described
SiN thickness can be with relatively thin, such as between 5-100 angstroms, as long as can play a protective role.
The deposition process of the protective layer 206 can select chemical vapor deposition（CVD）Method, physical vapour deposition (PVD)（PVD）
Method or ald（ALD）Low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and the choosing of the formation such as method
Select one kind in epitaxial growth (SEG).Preferred chemical vapor deposition in the present invention（CVD）Method.
Step 207 is performed, patterns the protective layer 206, interlayer dielectric layer 202 and the Semiconductor substrate 201, with
Silicon hole groove 20 is formed in the interlayer dielectric layer 202 and Semiconductor substrate 201.
Specifically, as shown in Figure 2 d, the protective layer 206, interlayer dielectric layer 202 and the Semiconductor substrate 201, with
The shape of the silicon hole groove 20 is formed, in this step protective layer 206 described in wet etching, it is recessed to form the silicon hole
The shape of groove 20, specifically, with the hydrofluoric acid DHF of dilution（Wherein include HF, H2O2And H2O）The oxide hard is etched to cover
Film layer.Wherein, the concentration of the DHF does not limit strictly, in the present invention preferred HF:H2O2:H2O=0.1-1.5:1:5。
Then with the protective layer 206 for mask etch interlayer dielectric layer 202 and the Semiconductor substrate 201, with institute
State and the silicon hole groove 20 is formed in interlayer dielectric layer 202 and Semiconductor substrate 201.The engraving method can select dry method
Etching or wet etching, it is not limited to a certain method.
The number of the silicon hole groove 20 and depth are not limited to a certain number range in this step, in the reality
To apply in example, the number of the silicon hole groove 20 is one, its depth is less than the thickness of the Semiconductor substrate 201, Ke Yigen
According to needing to be configured, will not be repeated here.
Step 208 is performed, separation layer 208. is formed in the protective layer 206 and the silicon hole groove 20
Specifically, as shown in Figure 2 e, in of the invention one specifically embodiment, the separation layer 203 is SiO2Layer,
Its thickness is 8-50 angstroms, but is not limited to the thickness.
The protective layer 206 can pass through chemical vapor deposition（CVD）Method, physical vapour deposition (PVD)（PVD）Method or atom
Layer deposition（ALD）The formation such as method.Preferred ald in the present invention（ALD）Method.
Step 209 is performed, diffusion impervious layer 206 is formed in the silicon hole groove 20.
Specifically, as shown in Figure 2 e, when the critical size of device（critical dimension）Going reduction is to deep Asia
, it is necessary to be reduced using multiple layer metal connecting line construction when RC delays caused by dead resistance and parasitic capacitance when in micrometer range
Between, form diffusion impervious layer over the substrate in the present invention（barrier）（Not shown in figure）, preferably, the resistance
The forming method of barrier 206 can be mainly to select physical vaporous deposition and chemical vapour deposition technique, specifically, can select
Evaporation, electron beam evaporation, plasma spray deposition and sputtering, preferred plasma spray deposition and splash in the present invention
The method of penetrating forms the barrier layer.The thickness on the barrier layer is not limited in a certain numerical value or scope, can be as needed
It is adjusted.
Preferably, the material of diffusion impervious layer 206 can be the one or more in TaN, Ta, TiN, Ti.
Step 210 is performed, conductive material 207 is filled in the silicon hole groove 20, to form through-silicon via structure.
Specifically, as shown in Figure 2 e, from metal material 207, such as from the metallic copper filling silicon hole groove 20
Middle filling conductive material 207, can pass through physical vapour deposition (PVD) in the present invention（PVD）Method or Cu electroplating（ECP）'s
Method fills the silicon hole groove 20 and fills conductive material 207.
Preferably, then in the Seed Layer of the deposited metal copper first on the diffusion impervious layer, the Seed Layer
Deposition process can select chemical vapor deposition（CVD）Method, physical vapour deposition (PVD)（PVD）Method or ald（ALD）Method etc..
Then Cu electroplating is selected（ECP）Method form the metallic copper, preferably, plating when can also make
With additive, the additive is flat dose（LEVELER）, accelerator（ACCELERATORE）And inhibitor
（SUPPRESSOR）.
Preferably, after forming the metallic copper and being formed can also further comprising annealing the step of, annealing can be
2-4 hours are carried out at 80-160 DEG C, to promote copper to recrystallize, long big crystal grain, resistance is reduced and improves stability.
Step 210 is performed, (CMP) technique is chemically-mechanicapolish polished, planarizes the conductive material 207 to the protection
Layer 206.
As shown in figure 2f, table can be realized using flattening method conventional in field of semiconductor manufacture in this step
The planarization in face.The non-limiting examples of the flattening method include mechanical planarization method and chemically mechanical polishing planarization side
Method.Chemically mechanical polishing flattening method is more often used.
Step 211 is performed, the protective layer 206 is removed, to expose the sacrificial material layer 205.
Specifically, as shown in Figure 2 g, the protective layer 206 is removed in this step, to expose the sacrificial material layer 205
And contact hole 203, preferably, removing the sacrificial material layer 205 from dry etching in this step, in this step
CF can be selected in the dry etching4、CHF3Add N in addition2、CO2、O2In it is a kind of as etching atmosphere, wherein gas stream
Measure as CF410-200sccm, CHF310-200sccm, N2Or CO2Or O210-400sccm, the etching pressure are 30-
150mTorr, more preferably etching period 5-120s, preferably 5-60s, 5-30s.
Step 212 is performed, removes the sacrificial material layer 205.
Specifically, reference picture 2h, the sacrificial material layer 205 is removed from ashing method in this step, the present invention's
O is selected in one embodiment2Or contain O2Atmosphere ashing processing, the ashing treatment temperature are carried out to the device
At 800-1500 DEG C, preferably 1100-1200 DEG C, processing time 2-30min.
A-C can use ashing（Asher）Mode removes, and a-C is easier to remove compared to SIN, clean and it does not allow to be also easy to produce
Residue.
Methods described can further include holds high to form metal interconnection structure in the through-silicon via structure, described
Metal pad is formed on metal interconnection structure and forms the metal interconnection structure from Damascus technics in this step.At this
The one of invention specifically in embodiment, is sequentially depositing the first erosion stop-layer, the first dielectric on the first metal layer first
Layer, etching stopping layer, dielectric layer, hard mask layer, oxide hard-mask layer and metal hard mask；Etch the metal hard mask
Layer and the part compound hard mask layer, form opening, then deposit anti-reflective coatings and photoresist layer, and etch to be formed it is logical
Hole opening；Remove the reflectance coating and photoresist layer；Using the metal hard mask layer as dielectric layer described in mask etch, simultaneously
Form multiple contact hole grooves and through hole；The etching stopping layer is etched, to expose in the interlevel dielectric material layer, described another
The metal interconnection structure inlayed is formed in one dielectric layer；Using conductive material（Cu）The groove and through hole are filled, and is planarized
To form electrical connection.
The present invention proposes to use a-C to prepare as silicon hole（TSV VIA middle）CT protective layer in technique, a-C make
For a kind of protective layer and sacrifice layer well, the method for CVD deposition can be used to be covered in the surface of wafer, and compare SIN
, can be to photo-etching mark hole 204 with more preferable Step Coverage ability（CT photo mark）The cavity in region forms good
Filling, makes silicon hole medium（TSV isolation）Photo-etching mark hole 204 can not be deposited on（CT photo mark）Region, institute
With CT surfaces silicon hole medium（TSV isolation）It can be completely removed, so as to not influence follow-up the first metal layer photoetching
（M1photo）Contraposition, efficiently solve OVL and measure problem.
In addition, a-C compares SIN, during CMP and silicon hole medium（oxide）Between have higher selection ratio, can be with
More preferable protection is formed to CT.
Moreover, a-C can use ashing（Asher）Mode removes, and a-C is easier to remove compared to SIN, clean and it is not easy
Produce residue.
Fig. 3 is the preparation technology flow chart of the specifically semiconductor devices described in embodiment of the present invention one, is specifically included
Following steps：
Step 201 provides Semiconductor substrate, on the semiconductor substrate formed with interlayer dielectric layer, the interlayer dielectric
There is space formed with contact hole and photo-etching mark hole, the photo-etching mark hole in layer；
Step 202 sacrificial material layer, to be filled up completely with the space；
Step 203 forms protective layer on the interlayer dielectric layer and the sacrificial material layer；
Step 204 forms silicon hole in the Semiconductor substrate and the interlayer dielectric layer；
Step 205 removes the protective layer, to expose the sacrificial material layer；
Step 206 removes the sacrificial material layer, to expose the space.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (8)
1. a kind of preparation method of semiconductor devices, including：
Semiconductor substrate is provided, on the semiconductor substrate formed with interlayer dielectric layer, in the interlayer dielectric layer formed with
Contact hole and photo-etching mark hole, the photo-etching mark hole have space；
Sacrificial material layer, to be filled up completely with the space, the sacrificial material layer selects amorphous carbon；
Protective layer is formed on the interlayer dielectric layer and the sacrificial material layer；
Silicon hole is formed in the Semiconductor substrate and the interlayer dielectric layer；
The protective layer is removed, to expose the sacrificial material layer；
The sacrificial material layer is removed, to expose the space.
2. according to the method for claim 1, it is characterised in that the method for filling the space is：
The sacrificial material layer is deposited in the interlayer dielectric layer and the space, to cover the interlayer dielectric layer, and
Fill the space；
Planarisation step is performed, to remove the sacrificial material layer in the interlayer dielectric layer surface.
3. according to the method for claim 1, it is characterised in that the method for forming the silicon hole is：
The mask layer of patterning is formed on the protective layer；
Using the mask layer as protective layer, the interlayer dielectric layer and the Semiconductor substrate described in mask etch, to be formed
Silicon hole groove；
Remove the mask layer；
Separation layer is formed in the silicon hole groove；
The silicon hole groove is filled from conductive material；
Planarisation step is performed, the conductive material is planarized to the protective layer, to form the silicon hole.
4. according to the method for claim 3, it is characterised in that the method for filling the silicon hole groove is：
Diffusion impervious layer is formed on the separation layer；
The Seed Layer of metal is formed on the diffusion impervious layer；
From electrochemistry electric plating method deposited metal to fill the silicon hole groove.
5. according to the method for claim 1, it is characterised in that remove the sacrificial material layer from ashing method.
6. according to the method for claim 1, it is characterised in that the protective layer selects SiN layer；
The interlayer dielectric layer selects oxide skin(coating).
7. according to the method for claim 1, it is characterised in that form the side in the contact hole and the photo-etching mark hole
Method is：
The interlayer dielectric layer is patterned, to form contact hole groove and photo-etching mark hole groove；
Conductive material is deposited, to be filled up completely with the contact hole groove, forms contact hole, while be partially filled with the photo-etching mark
Hole groove, conductive material is formed in the side wall of photo-etching mark hole groove, the photo-etching mark with formation center with space
Hole.
8. the semiconductor devices that the method described in a kind of one of claim 1 to 7 is prepared, the institute in the semiconductor devices
The center for stating photo-etching mark hole has space.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201310743149.4A CN104752323B (en) | 2013-12-27 | 2013-12-27 | A kind of semiconductor devices and preparation method thereof |
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| CN201310743149.4A CN104752323B (en) | 2013-12-27 | 2013-12-27 | A kind of semiconductor devices and preparation method thereof |
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| Publication Number | Publication Date |
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| CN104752323A CN104752323A (en) | 2015-07-01 |
| CN104752323B true CN104752323B (en) | 2018-03-20 |
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| CN108511388B (en) * | 2017-02-27 | 2023-07-21 | Imec 非营利协会 | Method for patterning a target layer |
| CN108667437B (en) * | 2018-04-19 | 2022-04-26 | 中芯集成电路（宁波）有限公司 | Film bulk acoustic resonator, manufacturing method thereof and electronic device |
| CN113745297B (en) * | 2021-08-31 | 2023-04-07 | 深圳市华星光电半导体显示技术有限公司 | OLED display panel, pixel repairing method and mobile terminal |
| CN114582721B (en) * | 2022-05-05 | 2022-08-02 | 湖北江城芯片中试服务有限公司 | Method for manufacturing semiconductor device |
| CN115922258B (en) * | 2023-02-07 | 2023-05-09 | 河南工学院 | Casting and milling integrated forming manufacturing method for terahertz metal coating hollow rectangular waveguide cavity |
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