CN104752317A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
- Publication number
- CN104752317A CN104752317A CN201310731501.2A CN201310731501A CN104752317A CN 104752317 A CN104752317 A CN 104752317A CN 201310731501 A CN201310731501 A CN 201310731501A CN 104752317 A CN104752317 A CN 104752317A
- Authority
- CN
- China
- Prior art keywords
- copper metal
- layer
- dielectric layer
- porous low
- interconnect structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a method of manufacturing a semiconductor device, comprising the following steps: providing a semiconductor substrate and sequentially forming an etching stop layer and a porous low-k dielectric layer on the semiconductor substrate; forming a copper metal interconnect structure in the porous low-k dielectric layer; forming a copper metal diffusion barrier layer on the side walls and the bottom of the copper metal interconnect structure through deposition; post-processing the semiconductor substrate to repair the damaged porous low-k dielectric layer and enhance the mechanical strength of the porous low-k dielectric layer; and filling the copper metal interconnect structure with a copper metal interconnect layer. According to the invention, the semiconductor substrate is post-processed after the copper metal diffusion barrier layer is formed through deposition, so that the porous low-k dielectric layer damaged when the copper metal interconnect structure is formed can be repaired, the mechanical strength of the porous low-k dielectric layer can be enhanced, and degradation in the performance of the device is avoided.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of form copper metal interconnect structure time avoid porous low k dielectric layer to sustain damage method.
Background technology
Along with the continuous reduction of dimensions of semiconductor devices, the impact of the capacitive crosstalk between copper metal interconnecting layer is day by day remarkable.In order to solve the problem of capacitive crosstalk, between copper metal interconnecting layer, arrange that porous low k dielectric layer is a kind of mode of well dealing with problems.
For the logical circuit in semiconductor device, the number of plies of copper metal interconnecting layer reaches several layers and even ten several layers, and every one deck copper metal interconnecting layer is formed at corresponding copper metal interconnect structure respectively.As shown in Figure 1A, the Semiconductor substrate 100 being formed with front-end devices is formed with stacked etching stopping layer 101 and porous low k dielectric layer 102 from bottom to top, in porous low k dielectric layer 102, be formed with the copper metal interconnect structure 103 be communicated with described front-end devices by dry etching, it is made up of through hole 103a and groove 103b.Then, implement wet-cleaned, to remove residue and the impurity of described etching generation.Then, as shown in Figure 1B, copper metal diffusion barrier layer 104 is formed by physical vapour deposition (PVD) at the sidewall of copper metal interconnect structure 103 and bottom.Then, copper metal seed layer and copper metal interconnecting layer is formed successively.
Mechanical strength for porous low k dielectric layer 102 is poor, therefore, in above-mentioned technical process, the dry etching implemented, wet-cleaned and physical vapour deposition (PVD) all can cause damage to porous low k dielectric layer 102, and then change the k value (dielectric constant) of porous low k dielectric layer 102, cause the decline of device performance.
Therefore, need to propose a kind of method, to solve the problem.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprising: Semiconductor substrate is provided, form etching stopping layer and porous low k dielectric layer successively on the semiconductor substrate; Copper metal interconnect structure is formed in described porous low k dielectric layer; At sidewall and the bottom deposit formation copper metal diffusion barrier layer of described copper metal interconnect structure; Last handling process is implemented to described Semiconductor substrate, to repair the described porous low k dielectric layer sustained damage, and promotes the mechanical strength of described porous low k dielectric layer.
Further, the implementation step of described last handling process comprises: the atmosphere described Semiconductor substrate being placed in DEMS, the described porous low k dielectric layer sustained damage during to repair and to form described copper metal interconnect structure; Ultraviolet light or infrared irridiation process are implemented to described Semiconductor substrate, is returned to make the dielectric constant of described porous low k dielectric layer the numerical value formed before described copper metal interconnect structure; Argon plasma bombardment processing is implemented, to promote the mechanical strength of described porous low k dielectric layer to described Semiconductor substrate.
Further, the flow of described DEMS is 100-5000sccm, and temperature is 100-500 DEG C.
Further, the power of described ultraviolet light irradiation is greater than 100W, wavelength is 150-400nm, and the power of described infrared irridiation is 50-3000W, wavelength is greater than 400nm.
Further, the power of described argon plasma bombardment is 100-3000W, and pressure is 0.1-10Torr, and the flow of described argon plasma is 100-3000sccm.
Further, the step forming described copper metal interconnect structure comprises: on described porous low k dielectric layer, form stacked resilient coating and hard mask layer from bottom to top; The first opening of the pattern of the groove be used as in described copper metal interconnect structure is formed, to expose described resilient coating in described hard mask layer; The second opening of the pattern of the through hole be used as in described copper metal interconnect structure is formed in described resilient coating and described porous low k dielectric layer; With described hard mask layer for mask, with resilient coating described in step etching and described porous low k dielectric layer, to form described copper metal interconnect structure in described porous low k dielectric layer.
Further, after described etching terminates, also comprise the etching stopping layer removed and exposed by described copper metal interconnect structure and the step implementing etching reprocessing.
Further, after implementing described last handling process, be also included in the step of filling copper metal interconnecting layer in described copper metal interconnect structure.
Further, before implementing described filling, be also included in the step described copper metal diffusion barrier layer being formed copper metal seed layer.
Further, after implementing described filling, also comprise and perform cmp until expose the step of described porous low k dielectric layer
According to the present invention, after deposition forms described copper metal diffusion barrier layer, last handling process is implemented to described Semiconductor substrate, the described porous low k dielectric layer sustained damage when forming described copper metal interconnect structure can be repaired, promote the mechanical strength of porous low k dielectric layer, avoid the decline of device performance.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A shows the schematic cross sectional view forming the device after the copper metal interconnect structure being communicated with front-end devices layer according to prior art;
Figure 1B shows the schematic cross sectional view forming the device after copper metal diffusion barrier layer in the copper metal interconnect structure illustrated in figure ia;
The schematic cross sectional view of the device that Fig. 2 A-Fig. 2 H obtains respectively for method is implemented successively according to an exemplary embodiment of the present invention step;
Fig. 3 is the flow chart of step implemented successively of method according to an exemplary embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, so that the method avoiding porous low k dielectric layer to sustain damage when explaining the formation copper metal interconnect structure of the present invention's proposition.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
[exemplary embodiment]
Below, with reference to Fig. 2 A-Fig. 2 H and Fig. 3, the key step avoiding porous low k dielectric layer to sustain damage when method forms copper metal interconnect structure is according to an exemplary embodiment of the present invention described.
With reference to Fig. 2 A-Fig. 2 H, the schematic cross sectional view of the device that the step that the method according to an exemplary embodiment of the present invention that illustrated therein is is implemented successively obtains respectively.
First, as shown in Figure 2 A, provide Semiconductor substrate 200, adopt chemical vapor deposition method to form etching stopping layer 201, porous low k dielectric layer 202, resilient coating 203 and hard mask layer 204 successively on semiconductor substrate 200.
Be formed with front-end devices on semiconductor substrate 200, in order to simplify, do not give in legend and illustrating.The device that described front-end devices is formed before referring to the back end fabrication (BEOL) implementing semiconductor device, does not limit the concrete structure of front-end devices at this.Described front-end devices comprises grid structure, and as an example, grid structure comprises the gate dielectric and gate material layers that stack gradually from bottom to top.Be formed with side wall construction in the both sides of grid structure, in the Semiconductor substrate 200 of side wall construction both sides, be formed with source/drain region, be channel region between source/drain region; The top and source/drain region of grid structure are formed with self-aligned silicide.
Material preferred SiCN, SiC or SiN of etching stopping layer 201, it with while the etching stopping layer forming the throughhole portions of the copper metal interconnect structure being communicated with described front-end devices wherein, can stop the copper metal being formed at described copper metal interconnect structure to be diffused into the interlayer dielectric layer at described front-end devices place as subsequent etch porous low k dielectric layer 202.
The formation of porous low k dielectric layer 202 comprises the following steps: on etching stopping layer 201, deposit low k dielectric, its constituent material can be selected from the common material with low k-value (dielectric constant is less than 4.0) in this area, include but not limited to that k value is the silicate compound (Hydrogen Silsesquioxane, referred to as HSQ) of 2.6-2.9, k value is the HOSP of 2.8
tM(advanced low-k materials of the mixture based on organic substance and Si oxide that Honeywell company manufactures) and k value are the SiLK of 2.65
tM(a kind of advanced low-k materials that Dow Chemical company manufactures) etc.; Adopt the method such as ultraviolet irradiation or heating to make low k dielectric porous, to form porous low k dielectric layer 202, because porous process implemented by needs, therefore, in the process of deposition low k dielectric, need to add pore creating material precursor, such as C
10h
16(ATRP).
Resilient coating 203 comprises the transition material layer 203a and TEOS(tetraethoxysilane that stack gradually from bottom to top) layer 203b, the effect of transition material layer 203a increases the adhesive force between the constituent material of porous low k dielectric layer 202 and TEOS, avoids the porous structure of mechanical stress to porous low k dielectric layer 202 to cause damage when the effect of TEOS layer 203b is the copper metal in follow-up grinding is filled in the copper metal interconnect structure being communicated with described front-end devices.The constituent material of transition material layer 203a comprises SiN, SiC or SiOC.
Hard mask layer 204 comprises the metal hard mask layer 204a and oxide hardmask layer 204b that stack gradually from bottom to top, the structure of this double-deck hard mask layer can ensure the craft precision of Dual graphing or multiple graphical, ensure the degree of depth of whole figures and the consistency of side wall profile of required formation in hard mask layer 204, namely first the pattern with different characteristic size is formed in oxide hardmask layer 204b, then with the figure of oxide hardmask layer 204b required formation for mask etch metal hard mask layer 204a makes in hard mask layer 204.The constituent material of metal hard mask layer 204a comprises TiN, BN or its combination, preferred TiN; The constituent material of oxide hardmask layer 204b comprises SiO
2, SiON etc., and require that it has good etching selectivity relative to the constituent material of metal hard mask layer 204a.
Then, as shown in Figure 2 B, in hard mask layer 204, the first opening 205 is formed, to expose the resilient coating 203 of below.Described first opening 205 correspondence is communicated with the pattern of the throughhole portions of the copper metal interconnect structure of described front-end devices, and it can comprise multiple figure with different characteristic size.
According to the situation of the figure of required formation, need twice or repeatedly implement the patterning process of described through-hole pattern, each enforcement includes following steps: on oxide hardmask layer 204b, form ODL layer (organic dielectric layer), BARC layer (bottom antireflective coating) and PR layer (photoresist layer) successively; Photoetching, development treatment are carried out to PR layer, to form through-hole pattern in PR layer; With the PR layer of patterning for mask, etch BARC layer, ODL layer and oxide hardmask layer 204b successively, in oxide hardmask layer 204b, form through-hole pattern; Adopt the PR layer of the technique removal patternings such as ashing, BARC layer and ODL layer.Finally, to form the oxide hardmask layer 204b of all required through-hole patterns wherein for mask, etching metal hard mask layer 204a, completes the making of the first opening 205.
Then, as shown in Figure 2 C, to have the hard mask layer 204 of the first opening 205 for mask, etch buffer layers 203 and porous low k dielectric layer 202 successively, until expose etching stopping layer 201.Adopt anisotropic dry method etch technology to implement described etching, in porous low k dielectric layer 202, after described etching terminates, form the through hole 207a of the copper metal interconnect structure being communicated with described front-end devices.
Then, as shown in Figure 2 D, in hard mask layer 204, the second opening 206 is formed, to expose the resilient coating 203 of below.Described second opening 206 correspondence is communicated with the pattern of the trench portions of the copper metal interconnect structure of described front-end devices, and it can comprise multiple figure with different characteristic size.
According to the situation of the figure of required formation, need twice or repeatedly implement the patterning process of described channel patterns, each enforcement includes following steps: on oxide hardmask layer 204b, form another ODL layer, another BARC layer and another PR layer successively; Photoetching, development treatment are carried out to another PR layer, to form channel patterns in another PR layer; With another PR layer of patterning for mask, etch another BARC layer, another ODL layer and oxide hardmask layer 204b successively, in oxide hardmask layer 204b, form channel patterns; Adopt another PR layer of the technique removal patternings such as ashing, another BARC layer and another ODL layer.Finally, to form the oxide hardmask layer 204b of all required channel patterns wherein for mask, etching metal hard mask layer 204a, completes the making of the second opening 206.
Then, as shown in Figure 2 E, there is the hard mask layer 204 of the second opening 206 for mask, etch buffer layers 203 and porous low k dielectric layer 202 successively, adopt anisotropic dry method etch technology to implement described etching, in porous low k dielectric layer 202, after described etching terminates, form the groove 207b of the copper metal interconnect structure being communicated with described front-end devices.
Next, remove the etching stopping layer 201 exposed by through hole 207a, be communicated with described front-end devices to make described copper metal interconnect structure.In the present embodiment, dry method etch technology is adopted to implement the removal of described etching stopping layer 201.Then, adopt wet clean process to implement etching last handling process, to remove the residuals and impurity that aforementioned etching process produces.
The aforementioned technical process forming the copper metal interconnect structure being communicated with described front-end devices is only the one in dual damascene process, what those skilled in the art should know is, other execution mode forming the dual damascene process of described copper metal interconnect structure is also applicable, the trench portions such as first forming described copper metal interconnect structure forms the throughhole portions of described copper metal interconnect structure again, does not repeat them here the implementation step that it is detailed.
Then, as shown in Figure 2 F, at sidewall and the bottom deposit formation copper metal diffusion barrier layer 208 of copper metal interconnect structure 207.In the present embodiment, physical vapour deposition (PVD) is deposited as described in.The material of copper metal diffusion barrier layer 208 is metal, metal nitride or its combination, the combination of preferred Ta and TaN or the combination of Ti and TiN.
Next, last handling process is implemented to Semiconductor substrate 200, to repair the porous low k dielectric layer 202 sustained damage, and promote the mechanical strength of porous low k dielectric layer 202.In the present embodiment, described last handling process comprises the following steps: first, and Semiconductor substrate 200 is placed in DEMS(silicone glass precursor, chemical formula is
) atmosphere in, the flow of porous low k dielectric layer 202, DEMS sustained damage during to repair and to form copper metal interconnect structure 207 is for 100-5000sccm, and temperature is 100-500 DEG C; Then, ultraviolet light or infrared irridiation process are implemented to Semiconductor substrate 200, the numerical value formed before copper metal interconnect structure 207 is returned to make the dielectric constant of porous low k dielectric layer 202, the power of described ultraviolet light irradiation is greater than 100W, wavelength is 150-400nm, and the power of described infrared irridiation is 50-3000W, wavelength is greater than 400nm; Finally, the process of argon (Ar) plasma bombardment is implemented to Semiconductor substrate 200, to promote the mechanical strength of porous low k dielectric layer 202, the power of described argon plasma bombardment is 100-3000W, pressure is 0.1-10Torr, the flow of argon plasma is 100-3000sccm, wherein, Torr represents millimetres of mercury, and sccm represents cc/min.
Then, as shown in Figure 2 G, in copper metal interconnect structure 207, copper metal interconnecting layer 209 is filled.In the present embodiment, electroplating technology is adopted to implement described filling.In order to strengthen the tack between copper metal interconnecting layer 209 and copper metal diffusion barrier layer 208, before implementing described filling, copper metal diffusion barrier layer 208 first forming copper metal seed layer, in order to simplify, not give in figure and illustrating.
Then, as illustrated in figure 2h, perform cmp, until expose porous low k dielectric layer 202, in the process, hard mask layer 204 and resilient coating 203 are all removed.
So far, the processing step that the method according to an exemplary embodiment of the present invention that completes is implemented, next, can complete the making of whole semiconductor device by subsequent technique.According to the present invention, after the sidewall and bottom deposit formation copper metal diffusion barrier layer 208 of copper metal interconnect structure 207, last handling process is implemented to Semiconductor substrate 200, the porous low k dielectric layer 202 sustained damage when forming copper metal interconnect structure 207 can be repaired, promote the mechanical strength of porous low k dielectric layer 202, avoid the decline of device performance.
With reference to Fig. 3, the flow chart of the step that the method according to an exemplary embodiment of the present invention that illustrated therein is is implemented successively, for schematically illustrating the flow process of whole manufacturing process.
In step 301, provide Semiconductor substrate, form etching stopping layer and porous low k dielectric layer successively on a semiconductor substrate;
In step 302, in porous low k dielectric layer, copper metal interconnect structure is formed;
In step 303, at sidewall and the bottom deposit formation copper metal diffusion barrier layer of copper metal interconnect structure;
In step 304, last handling process is implemented to Semiconductor substrate, to repair the porous low k dielectric layer sustained damage, and promotes the mechanical strength of porous low k dielectric layer;
In step 305, in copper metal interconnect structure, copper metal interconnecting layer is filled.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (10)
1. a manufacture method for semiconductor device, comprising:
Semiconductor substrate is provided, forms etching stopping layer and porous low k dielectric layer successively on the semiconductor substrate;
Copper metal interconnect structure is formed in described porous low k dielectric layer;
At sidewall and the bottom deposit formation copper metal diffusion barrier layer of described copper metal interconnect structure;
Last handling process is implemented to described Semiconductor substrate, to repair the described porous low k dielectric layer sustained damage, and promotes the mechanical strength of described porous low k dielectric layer.
2. method according to claim 1, is characterized in that, the implementation step of described last handling process comprises: the atmosphere described Semiconductor substrate being placed in DEMS, the described porous low k dielectric layer sustained damage during to repair and to form described copper metal interconnect structure; Ultraviolet light or infrared irridiation process are implemented to described Semiconductor substrate, is returned to make the dielectric constant of described porous low k dielectric layer the numerical value formed before described copper metal interconnect structure; Argon plasma bombardment processing is implemented, to promote the mechanical strength of described porous low k dielectric layer to described Semiconductor substrate.
3. method according to claim 2, is characterized in that, the flow of described DEMS is 100-5000sccm, and temperature is 100-500 DEG C.
4. method according to claim 2, is characterized in that, the power of described ultraviolet light irradiation is greater than 100W, wavelength is 150-400nm, and the power of described infrared irridiation is 50-3000W, wavelength is greater than 400nm.
5. method according to claim 2, is characterized in that, the power of described argon plasma bombardment is 100-3000W, and pressure is 0.1-10Torr, and the flow of described argon plasma is 100-3000sccm.
6. method according to claim 1, is characterized in that, the step forming described copper metal interconnect structure comprises: on described porous low k dielectric layer, form stacked resilient coating and hard mask layer from bottom to top; The first opening of the pattern of the groove be used as in described copper metal interconnect structure is formed, to expose described resilient coating in described hard mask layer; The second opening of the pattern of the through hole be used as in described copper metal interconnect structure is formed in described resilient coating and described porous low k dielectric layer; With described hard mask layer for mask, with resilient coating described in step etching and described porous low k dielectric layer, to form described copper metal interconnect structure in described porous low k dielectric layer.
7. method according to claim 6, is characterized in that, after described etching terminates, also comprises the etching stopping layer removed and exposed by described copper metal interconnect structure and the step implementing etching reprocessing.
8. method according to claim 1, is characterized in that, after implementing described last handling process, is also included in the step of filling copper metal interconnecting layer in described copper metal interconnect structure.
9. method according to claim 8, is characterized in that, before implementing described filling, is also included in the step described copper metal diffusion barrier layer being formed copper metal seed layer.
10. method according to claim 8, is characterized in that, after implementing described filling, also comprises and performs cmp until expose the step of described porous low k dielectric layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310731501.2A CN104752317B (en) | 2013-12-26 | 2013-12-26 | A kind of manufacture method of semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310731501.2A CN104752317B (en) | 2013-12-26 | 2013-12-26 | A kind of manufacture method of semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104752317A true CN104752317A (en) | 2015-07-01 |
| CN104752317B CN104752317B (en) | 2017-11-10 |
Family
ID=53591801
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310731501.2A Active CN104752317B (en) | 2013-12-26 | 2013-12-26 | A kind of manufacture method of semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104752317B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106971973A (en) * | 2016-01-13 | 2017-07-21 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method, electronic installation |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030205822A1 (en) * | 2002-05-02 | 2003-11-06 | Taiwan Semiconductor Manufacturing Co. Ltd. | Low-strength plasma treatment for interconnects |
| CN100376019C (en) * | 2004-09-30 | 2008-03-19 | 台湾积体电路制造股份有限公司 | Method for treating low-K dielectrics |
| US20100261349A1 (en) * | 2006-10-30 | 2010-10-14 | Novellus Systems, Inc. | Uv treatment for carbon-containing low-k dielectric repair in semiconductor processing |
| CN102655113A (en) * | 2011-03-04 | 2012-09-05 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of interconnection structure |
| TW201243948A (en) * | 2011-04-25 | 2012-11-01 | Applied Materials Inc | UV assisted silylation for recovery and pore sealing of damaged low k films |
| CN102800622A (en) * | 2011-05-26 | 2012-11-28 | 中芯国际集成电路制造(上海)有限公司 | Method for forming dielectric layer |
| CN103474342A (en) * | 2012-06-06 | 2013-12-25 | 中芯国际集成电路制造(上海)有限公司 | Method for repairing damaged dielectric layer |
-
2013
- 2013-12-26 CN CN201310731501.2A patent/CN104752317B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030205822A1 (en) * | 2002-05-02 | 2003-11-06 | Taiwan Semiconductor Manufacturing Co. Ltd. | Low-strength plasma treatment for interconnects |
| CN100376019C (en) * | 2004-09-30 | 2008-03-19 | 台湾积体电路制造股份有限公司 | Method for treating low-K dielectrics |
| US20100261349A1 (en) * | 2006-10-30 | 2010-10-14 | Novellus Systems, Inc. | Uv treatment for carbon-containing low-k dielectric repair in semiconductor processing |
| CN102655113A (en) * | 2011-03-04 | 2012-09-05 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of interconnection structure |
| TW201243948A (en) * | 2011-04-25 | 2012-11-01 | Applied Materials Inc | UV assisted silylation for recovery and pore sealing of damaged low k films |
| CN102800622A (en) * | 2011-05-26 | 2012-11-28 | 中芯国际集成电路制造(上海)有限公司 | Method for forming dielectric layer |
| CN103474342A (en) * | 2012-06-06 | 2013-12-25 | 中芯国际集成电路制造(上海)有限公司 | Method for repairing damaged dielectric layer |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106971973A (en) * | 2016-01-13 | 2017-07-21 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method, electronic installation |
| CN106971973B (en) * | 2016-01-13 | 2020-01-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104752317B (en) | 2017-11-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101882049B1 (en) | Spacers with rectangular profile and methods of forming the same | |
| TW201810591A (en) | Semiconductor device and method for manufacturing the same | |
| US9865473B1 (en) | Methods of forming semiconductor devices using semi-bidirectional patterning and islands | |
| US9748251B1 (en) | Methods of forming semiconductor devices using semi-bidirectional patterning | |
| CN104347476A (en) | Semiconductor device and manufacture method thereof | |
| TW200522203A (en) | Method for fabricating semiconductor device | |
| JP4443465B2 (en) | Method for forming metal wiring of semiconductor element | |
| WO2007116515A1 (en) | Semiconductor device, process for producing the same, method of dry etching, and process for fabricating wiring material | |
| CN1661799B (en) | Semiconductor device | |
| US7575997B2 (en) | Method for forming contact hole of semiconductor device | |
| CN104733373A (en) | Manufacturing method for semiconductor component | |
| JP4677068B2 (en) | Isolation method between conductive metal elements | |
| CN104241114A (en) | Method for manufacturing semiconductor device | |
| CN104658967A (en) | Semiconductor component and manufacturing method thereof | |
| CN104752317A (en) | Method for manufacturing semiconductor device | |
| CN102148216A (en) | Semiconductor structure for interconnection process and manufacturing method thereof | |
| US20220102143A1 (en) | Metal Hard Masks for Reducing Line Bending | |
| CN103531531B (en) | A kind of method being used for producing the semiconductor devices | |
| CN104681483A (en) | Manufacturing method of semiconductor device | |
| CN104347487A (en) | Manufacturing method of semiconductor device | |
| US7015149B2 (en) | Simplified dual damascene process | |
| CN104183538A (en) | Semiconductor device manufacturing method | |
| CN104282656B (en) | A kind of semiconductor devices and its manufacture method | |
| CN104733372B (en) | Method for manufacturing semiconductor device | |
| CN102044471B (en) | Interconnecting structure and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |