CN104750480B - Iterative image processing method on a kind of star based on FPGA - Google Patents
Iterative image processing method on a kind of star based on FPGA Download PDFInfo
- Publication number
- CN104750480B CN104750480B CN201510095534.1A CN201510095534A CN104750480B CN 104750480 B CN104750480 B CN 104750480B CN 201510095534 A CN201510095534 A CN 201510095534A CN 104750480 B CN104750480 B CN 104750480B
- Authority
- CN
- China
- Prior art keywords
- ccd
- parameter
- dual port
- ceil
- port ram
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Image Analysis (AREA)
- Image Processing (AREA)
- Closed-Circuit Television Systems (AREA)
Abstract
Iterative image processing method on a kind of star based on FPGA, a certain size space is opened up in dual port RAM first and is used to store parameter and feedback signal；And by parameter read-in dual port RAM needed for image procossing before valid data arrive；Then before valid data participate in image processing algorithm, these parameters is read from dual port RAM and are latched in register group；Computing is carried out to current a piece of CCD, the feedback parameter for drawing the parameter of adjustment camera status and being calculated for subsequent time, and update the register of storage parameter；Finally after calculating, in the supplemental characteristic write-in dual port RAM that register group is latched, and all CCD are traveled through.The present invention is by controlling the cooperation between dual port RAM and register group, make iterative image Processing Algorithm streamline time-division processing multi-disc different type CCD, particularly suitable for big data quantity and the scan picture algorithm of interative computation be present, such as automatic adjusument algorithm, it can be widely used in current remote sensing camera.
Description
Technical field
The present invention relates to a kind of image processing method, iterative image processing method on particularly a kind of star based on FPGA,
Realized suitable for the hardware of big data quantity, the scan picture algorithm for having interative computation, belong to Real-time Remote Sensing image procossing neck
Domain.
Background technology
With the development of remote sensing technology, people are increasingly urgent to remotely sensed image demand, and the requirement of image quality is also increasingly
It is high.Therefore it is most important for improving Remote Sensing Image Quality with pre-identification, the on-board processing method of pretreatment potentiality.Star at present
Epigraph Processing Algorithm is mainly image preprocessing and some automatic adjusument scheduling algorithms based on image procossing, wherein adaptive
This kind of algorithm, which should be adjusted, to be needed to be solved using repeatedly iteration, computationally intensive, is not suitable for the quick processing to image
With the real-time implementation on hardware.
And FPGA is due to the limitation of structure, particularly suitable for realize data volume it is huge, can be with image that streamline is realized
Adjustment method.So-called pipelining technique：It is that handling process is divided into some steps, whole data processing is " single current to ", that is, is not had
There are feedback or interative computation, the output of previous step is the input of next step.
In order to realize the algorithm of this kind of repeatedly iteration of automatic adjusument in FPGA platform, and adapt to distant at present
Sense camera multi-disc CCD works simultaneously, the requirement that data volume is huge, it is necessary to the implementation method of rational designed image Processing Algorithm,
To utilize the hardware resources such as computing, storage to greatest extent.Meanwhile to make hardware resource effectively play a role, algorithm and framework
Between close fit be critically important, it is necessary to consider effective control method of data flow, arithmetic element made full use of, reduce
The expense of logical resource.
The content of the invention
The technology of the present invention solves problem：Overcome FPGA platform to be bad to handle iterative algorithm this problem, propose one
Iterative image Processing Algorithm realizes framework on kind of the star based on FPGA, using dual port RAM and register group has built a figure
As processing framework, there will be the image processing algorithm of interative computation to be embedded in this framework, by controlling dual port RAM and register group
Read-write realize the switching of computing between the iteration of data and different CCD, enable an image processing algorithm module flowing water
Line handles multi-disc different type CCD, with the FPGA resource for handling a piece of CCD, completes multi-disc CCD processing, improves FPGA
Hardware resource utilization, meet the demand of big data quantity star epigraph interative computation to the full extent.
The present invention technical solution be：Iterative image processing method, step are as follows on a kind of star based on FPGA：
(1) according to iterative image Processing Algorithm on previously given star, determine that each CCD carries out parameter needed for image procossing
Quantity m1The quantity m of feedback parameter is produced with iterative image Processing Algorithm on star2, and according to m1And m2Opened up in dual port RAM
For storing the space of parameter and feedback parameter；
(2) before the arrival of effective image data, jointly controlled by CCD writing address signals and write enable signal, by each
CCD carries out the parameter read-in dual port RAM needed for image procossing；
(3) the iterative image before processing on planet is entered, a piece of CCD is chosen, reads piece CCD in dual port RAM and carry out image
Feedback parameter caused by parameter and previous moment algorithm needed for processing, CCD is subjected to the parameter and previous needed for image procossing
Feedback parameter caused by moment algorithm is latched in register group, and the feedback parameter of initial time algorithm is " 0 "；
(4) CCD chosen in step (3) carries out computing using iterative image Processing Algorithm on previously given star, draws
The characteristic parameter of current time image and the feedback parameter calculated for subsequent time, and update storage current time characteristics of image
The register of parameter calculates the register of feedback parameter with depositing for subsequent time；
(5) after the enabled end of current ccd data and image processing algorithm calculate, by what is chosen in step (3)
In feedback parameter write-in dual port RAM caused by parameter and current time algorithm needed for CCD progress image procossings；
(6) new a piece of CCD, repeat step (3)~step (5) are chosen, until traveling through all CCD.
Number of parameters m in the step (1) according to needed for a piece of CCD carries out image procossing1Produced with image processing algorithm
Raw feedback parameter quantity m2, the opening space in dual port RAM, for storing parameter and feedback signal, it is specially：
If FPGA serial process n piece ccd datas, the space opened up in dual port RAM is：
M=n*2^ceil (log2(2^ceil(log2m1)+m2)), wherein M is the length of memory space in dual port RAM, double
Mouth RAM bit is wide to be determined by bit wide in all parameters is maximum, and ceil represents to round to infinity.
Jointly controlled in the step (2) by CCD writing address signals and write enable signal, each CCD is subjected to image
Parameter read-in dual port RAM needed for processing；Specially：
Before each CCD valid data arrive, parameter signal and parameter enable signal that outside is sent can be by each CCD
Working condition and the parameter that carries out needed for image procossing of each CCD broadcasted, after off-the-air, parse each CCD and carry out
M needed for image procossing1Individual parameter, and writing address signal and write enable signal are controlled by m1Individual parameter read-in dual port RAM.
The writing address signal exports splicing generation by counter, and counter bit wide is ceil (log2m1)+ceil
(log2N), it is n*2^ceil (log by length2m1) individual clock cycle high level flip-flop number, dual port RAM write signal is by three
Divide and be spliced, the ceil (log of Part I interception counter output2m1) the high ceil (log that start of+1bit2N) data,
The data of Part II are " 0 ", and the bit wide of " 0 " is ceil (log2(2^ceil(log2m1)+m2))-ceil(log2m1), mend " 0 "
Effect be write address is crossed over m2Individual parameter；Part III bit wide is ceil (log2m1), interception counter exports low ceil
(log2m1) bit data, above three parts write signal is stitched together to form each CCD progress from high to low according to sequencing
M needed for image procossing1The write address of individual parameter.
Advantage is the present invention compared with prior art：
(1) present invention is under FPGA platform, by the flexible cooperation of register group and dual port RAM, in pipelined fashion
Iterative algorithm is realized, improves FPGA hardware resource utilization, big data quantity star epigraph is met to the full extent and changes
For the demand of computing；
(2) present invention plans ram region for every CCD, makes image processing algorithm pipeline processes by switching address ram
Different CCD, with the FPGA resource for handling a piece of CCD, streamline realizes multi-disc different type CCD processing, to the full extent
Hardware resource is saved, has better adapted to the processing of star epigraph；
(3) framework in the present invention carries out real-time update in calculating process to iterative parameter, suitable for there is interative computation
Scan picture algorithm, there is stronger engineering application value.
Brief description of the drawings
Fig. 1 is the algorithm flow chart of the present invention；
Fig. 2 is that dual port RAM memory space plans schematic diagram；
The timing diagram that Fig. 3 dual port RAMs are read and write and updated with register group；
Fig. 4 write-in dual port RAM data formats realize figure；
Fig. 5 counters generation address ram realizes figure；
Figure is realized in the renewal of Fig. 6 register groups parameter；
Figure is realized in the input of Fig. 7 dual port RAMs.
Embodiment
It is as shown in Figure 1 the algorithm flow chart of the present invention, from fig. 1, it can be seen that a kind of star based on FPGA provided by the invention
Upper iterative image processing method, is comprised the following steps that：
(1) according to iterative image Processing Algorithm on previously given star, determine that each CCD carries out parameter needed for image procossing
Quantity m1The quantity m of feedback parameter is produced with iterative image Processing Algorithm on star2, and according to m1And m2Opened up in dual port RAM
For storing the space of parameter and feedback parameter；Specially：
If FPGA serial process n piece ccd datas, the space opened up in dual port RAM is：
M=n*2^ceil (log2(2^ceil(log2m1)+m2)), wherein M is the length of memory space in dual port RAM, double
Mouth RAM bit is wide to be determined by bit wide in all parameters is maximum, and ceil represents to round to infinity.
m1And m2Asynchronous renewal, m1Individual parameter is carried out mainly outside injection and worked as the parameter and camera of control algolithm
The parameters such as preceding working condition, these parameters are not changed in algorithm calculating process.m2Individual parameter is image processing algorithm calculating process
In caused by, and feed back for subsequent time algorithm calculate, therefore algorithm calculate after need real-time update.
(2) as shown in figure 3, before valid data arrival, each CCD parameter is parsed, by n*m1Individual parameter read-in twoport
RAM.The data format of input dual port RAM produces as shown in Figure 4, by way of selector cascade, by the common n*m of n pieces CCD1It is individual
Parameter is changed into serial mode input dual port RAM, and CCD identifies the parameter for switching different CCD in " writing " and " reading ".Pass through
CCD writing address signals and write enable signal jointly control, and each CCD is carried out into the parameter read-in dual port RAM needed for image procossing；
Specially：
Before each CCD valid data arrive, parameter signal and parameter enable signal that outside is sent can be by each CCD
Working condition and the parameter that carries out needed for image procossing of each CCD broadcasted, after off-the-air, parse each CCD and carry out
M needed for image procossing1Individual parameter, and by writing address signal and write enable signal by m1Individual parameter read-in dual port RAM,
The writing address signal exports splicing generation by counter, and counter bit wide is ceil (log2m1)+ceil
(log2N), it is n*2^ceil (log by length2m1) individual clock cycle high level flip-flop number, dual port RAM write signal is by three
Divide and be spliced, the ceil (log of Part I interception counter output2m1) the high ceil (log that start of+1bit2N) data,
The data of Part II are " 0 ", and the bit wide of " 0 " is ceil (log2(2^ceil(log2m1)+m2))-ceil(log2m1), mend " 0 "
Effect be write address is crossed over m2Individual parameter；Part III bit wide is ceil (log2m1), interception counter exports low ceil
(log2m1) bit data, above three parts write signal is stitched together to form each CCD progress from high to low according to sequencing
M needed for image procossing1The write address of individual parameter.
Ram space planning is as shown in Figure 2.The reason for " 0 " is mended in RAM：Each CCD is set to store the first ground of parameter in RAM
Location is that 2 integral number power starts, and can so realize the address ram with a piece of CCD, passes through address shift and connecting method, production
Raw different CCD dual port RAMs argument address, save FPGA resource.
(3) the iterative image before processing on planet is entered, a piece of CCD is chosen, reads piece CCD in dual port RAM and carry out image
Feedback parameter caused by parameter and previous moment algorithm needed for processing, CCD is subjected to the parameter and previous needed for image procossing
Feedback parameter caused by moment algorithm is latched in register group, and the feedback parameter of initial time algorithm is " 0 "；
Before valid data participate in image processing algorithm, the parameter of three lines broadcast, which has parsed, finishes and has been written into twoport
RAM correspondence positions.Start in the effective rising edge of data, read the m of certain piece CCD in dual port RAM1Individual parameter and previous moment algorithm
The m of feedback2Individual parameter.Read address to be spliced to form by counter output and CCD mark step-by-steps, CCD is identified as a high position, and counter is defeated
It is low level to go out result.Counter bit wide is arranged to ceil (log2(2^ceil(log2m1)+m2)), it is 2^ceil (log by length2
(2^ceil(log2m1)+m2)) the high level flip-flop number of individual clock cycle.CCD is identified as 0,1,2 ..., n-1, each mark
At least cover the piece ccd data valid interval.Distinguished from the data that RAM is read according to address is read, deposit in different registers
In, as shown in Figure 6.Deposit m1The register group of individual parameter follows the data synchronization updating that RAM is read, in data calculation process not
Renewal, the only input as image processing algorithm use.Store m2The register of individual parameter in a data calculating cycle more
Twice newly, renewal for the first time is latched in different registers, for figure respectively after RAM data is read according to the difference for reading address
As processing computing uses.
(4) CCD chosen in step (3) carries out computing using iterative image Processing Algorithm on previously given star, draws
The characteristic parameter of current time image and for subsequent time calculate feedback parameter, renewal current time image features and
The register of feedback parameter is calculated for subsequent time；
Iteration is as follows in image processing algorithm：
Hi=Hnow*r+Hi-1*(1-r)
HiFor last moment and current time iterative value, HnowFor current time image features value, Hi-1For upper a period of time
Iterative value is carved, r is some parameter needed for image procossing.The formula only as an example, using when be defined by actual iterative formula.
(5) after the enabled end of current ccd data and image processing algorithm calculate, by what is chosen in step (3)
In feedback parameter write-in dual port RAM caused by parameter and current time algorithm needed for CCD progress image procossings；" writing " address shape
It is identical with reading RAM data mode above into mode；
(6) new a piece of CCD is chosen, repeat step (3)~step (5), until traveling through all CCD, obtains all figures
As characteristic parameter.
When the present invention carries out image procossing to a piece of CCD, " reading " " writing " to RAM is shared three times, is that data have for the first time
Before effect arrives, by the Parameter analysis of electrochemical of three lines broadcast and RAM is write；It is in the effective rising edge of data for the second time, reads a piece of in RAM
CCD m1+m2Individual parameter；Third time is after image procossing terminates, by m1+m2Relevant position in individual parameter read-in RAM.Read every time
Write operation produces one group of enabled, address and read-write control signal.Different at the time of due to reading and writing generation three times, a certain moment only has
One read-write operation occurs.Address, data are become by the tunnel of selecting module three with enable signal difference significant instant and inputted all the way
To dual port RAM, i.e., which is enabled effective, exports which circuit-switched data and address.Three enable signal logical "or"s merge into one
Individual enable signal, as the enabled of mono- mouth of RAM, a vacant RAM mouth, make for external detection algorithm function and monitoring algorithm
With as shown in Figure 7.
The present invention makes iterative image Processing Algorithm streamline point by controlling the cooperation between dual port RAM and register group
When handle multi-disc different type CCD, particularly suitable for big data quantity and the scan picture algorithm of interative computation be present, such as from
Regulation algorithm etc. is adapted to, can be widely used in current remote sensing camera.
The content not being described in detail in description of the invention belongs to the known technology of professional and technical personnel in the field.
Claims (3)
1. iterative image processing method on a kind of star based on FPGA, it is characterised in that step is as follows：
(1) according to iterative image Processing Algorithm on previously given star, determine that each CCD carries out the number of parameter needed for image procossing
Measure m1The quantity m of feedback parameter is produced with iterative image Processing Algorithm on star2, and according to m1And m2Open up and be used in dual port RAM
Store the space of parameter and feedback parameter；
(2) before the arrival of effective image data, jointly controlled by CCD writing address signals and write enable signal, each CCD is entered
Parameter read-in dual port RAM needed for row image procossing；
(3) the iterative image before processing on planet is entered, a piece of CCD is chosen, reads piece CCD in dual port RAM and carry out image procossing
Feedback parameter caused by required parameter and previous moment algorithm, CCD is subjected to the parameter and previous moment needed for image procossing
Feedback parameter caused by algorithm is latched in register group, and the feedback parameter of initial time algorithm is " 0 "；
(4) CCD chosen in step (3) carries out computing using iterative image Processing Algorithm on previously given star, draws current
The characteristic parameter of time chart picture and the feedback parameter calculated for subsequent time, and update storage current time image features
Register and deposit for subsequent time calculate feedback parameter register；
(5) after the enabled end of current ccd data and image processing algorithm calculate, the CCD chosen in step (3) is entered
In feedback parameter write-in dual port RAM caused by parameter and current time algorithm needed for row image procossing；
(6) new a piece of CCD, repeat step (3)~step (5) are chosen, until traveling through all CCD.
2. iterative image processing method on a kind of star based on FPGA according to claim 1, it is characterised in that：The step
(1) the number of parameters m according to needed for a piece of CCD carries out image procossing1With image processing algorithm caused by feedback parameter quantity
m2, the opening space in dual port RAM, for storing parameter and feedback signal, it is specially：
If FPGA serial process n piece ccd datas, the space opened up in dual port RAM is：
M=n*2^ceil (log2(2^ceil(log2m1)+m2)), wherein M be dual port RAM in memory space length, dual port RAM
Bit wide determines that ceil represents to round to infinity by bit wide in all parameters is maximum.
3. iterative image processing method on a kind of star based on FPGA according to claim 1, it is characterised in that：The step
(2) jointly controlled in by CCD writing address signals and write enable signal, each CCD parameters carried out needed for image procossing are write
Enter dual port RAM；Specially：
Before each CCD valid data arrive, parameter signal and parameter enable signal that outside is sent can be by each CCD works
Make state and parameter that each CCD is carried out needed for image procossing is broadcasted, after off-the-air, parse each CCD and carry out image
M needed for processing1Individual parameter, and writing address signal and write enable signal are controlled by m1Individual parameter read-in dual port RAM；
The writing address signal exports splicing generation by counter, and counter bit wide is ceil (log2m1)+ceil(log2N), by
Length is n*2^ceil (log2m1) individual clock cycle high level flip-flop number, dual port RAM write signal spliced by three parts and
Into (ceil (the log of Part I interception counter output2m1)+1) the high ceil (log that start of bit2N) bit data, the
The data of two parts are " 0 ", and the bit wide of " 0 " is ceil (log2(2^ceil(log2m1)+m2))-ceil(log2m1), mend " 0 "
Effect is write address is crossed over m2Individual parameter；Part III bit wide is ceil (log2m1), interception counter exports low ceil
(log2m1) bit data, above three parts write signal is stitched together to form each CCD progress from high to low according to sequencing
M needed for image procossing1The write address of individual parameter；Wherein n is CCD piece number, and ceil represents to round to infinity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510095534.1A CN104750480B (en) | 2015-03-03 | 2015-03-03 | Iterative image processing method on a kind of star based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510095534.1A CN104750480B (en) | 2015-03-03 | 2015-03-03 | Iterative image processing method on a kind of star based on FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104750480A CN104750480A (en) | 2015-07-01 |
| CN104750480B true CN104750480B (en) | 2017-12-22 |
Family
ID=53590235
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510095534.1A Active CN104750480B (en) | 2015-03-03 | 2015-03-03 | Iterative image processing method on a kind of star based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104750480B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106643666B (en) | 2016-09-13 | 2019-12-06 | 首都师范大学 | moving object detection method and system based on multiple sensors on same platform |
| CN106851084B (en) * | 2016-11-21 | 2019-12-20 | 北京空间机电研究所 | On-satellite real-time processing algorithm annotation updating platform for remote sensing camera |
| CN109345452B (en) * | 2018-09-10 | 2023-01-17 | 武汉精立电子技术有限公司 | Method for realizing rapid linear interpolation of image |
| CN111147691B (en) * | 2019-12-31 | 2022-07-05 | 上海联影医疗科技股份有限公司 | Image processing method, device, equipment and readable storage medium |
| CN112163984A (en) * | 2020-09-11 | 2021-01-01 | 杭州缦图摄影有限公司 | Satellite iterative image processing method based on FPGA |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101246256A (en) * | 2008-01-11 | 2008-08-20 | 中国科学院光电技术研究所 | Scalable high-speed wavefront slope processor based on FPGA |
| CN101420538A (en) * | 2008-12-17 | 2009-04-29 | 北京空间机电研究所 | Imaging circuit system of space multispectral linear array CCD remote sensor |
| CN102231140A (en) * | 2011-06-07 | 2011-11-02 | 上海电力学院 | Method for obtaining data envelopments based on double-port random access memory (DPRAM) |
| CN102684788A (en) * | 2012-04-23 | 2012-09-19 | 北京空间机电研究所 | Communicating device of optical remote sensor |
| CN103678515A (en) * | 2013-11-26 | 2014-03-26 | 北京空间机电研究所 | Extensible and massive remote sensing information processing system of space station |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5247542B2 (en) * | 2009-03-05 | 2013-07-24 | キヤノン株式会社 | Image processing apparatus, image processing apparatus control method, and program |
-
2015
- 2015-03-03 CN CN201510095534.1A patent/CN104750480B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101246256A (en) * | 2008-01-11 | 2008-08-20 | 中国科学院光电技术研究所 | Scalable high-speed wavefront slope processor based on FPGA |
| CN101420538A (en) * | 2008-12-17 | 2009-04-29 | 北京空间机电研究所 | Imaging circuit system of space multispectral linear array CCD remote sensor |
| CN102231140A (en) * | 2011-06-07 | 2011-11-02 | 上海电力学院 | Method for obtaining data envelopments based on double-port random access memory (DPRAM) |
| CN102684788A (en) * | 2012-04-23 | 2012-09-19 | 北京空间机电研究所 | Communicating device of optical remote sensor |
| CN103678515A (en) * | 2013-11-26 | 2014-03-26 | 北京空间机电研究所 | Extensible and massive remote sensing information processing system of space station |
Non-Patent Citations (1)
| Title |
|---|
| 基于FPGA的多格式数据传输设计;王鹏等;《电子测量技术》;20140131;第37卷(第1期);第70-75页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104750480A (en) | 2015-07-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104750480B (en) | Iterative image processing method on a kind of star based on FPGA | |
| CN106227507B (en) | Computing system and its controller | |
| CN104935786B (en) | A kind of method of image signal source and its processing picture signal based on soft processor | |
| CN103473720A (en) | Shield tunnel construction management system based on BIM | |
| CN107590085A (en) | A kind of dynamic reconfigurable array data path and its control method with multi-level buffer | |
| CN106647412A (en) | Data sharing method between distributed controllers based on configuration element | |
| CN103544470B (en) | A kind of moving platform air target Dual band IR isomerism parallel automatic target detection device | |
| CN116362168B (en) | Modeling method and device for GPGPU offline clock and storage medium | |
| CN106850331A (en) | A kind of Ethernet with synchronised clock function hair frame device of field of traffic | |
| CN108154299B (en) | Multi-tide-station long-channel ship tide taking safety analysis system | |
| CN115272701A (en) | Ship target detection method based on adaptive feature extraction and decoupling prediction head | |
| CN102446342A (en) | Reconfigurable binary arithmetical unit, reconfigurable binary image processing system and basic morphological algorithm implementation method thereof | |
| CN107870780A (en) | Data processing equipment and method | |
| CN105684506B (en) | The flow control methods and device of network-on-chip NoC | |
| CN103136032B (en) | A kind of parallel simulation system for multi-core system | |
| CN108446096A (en) | Data computing system | |
| CN103677742B (en) | Many floating-point operations number plus/minus arithmetic and control unit | |
| Ren et al. | Design of a FPGA hardware architecture to detect real-time moving objects using the background subtraction algorithm | |
| CN110187865A (en) | Full flowing water high-throughput accumulator and its data processing method | |
| CN115470663A (en) | Synchronous simulation method, device and medium for oil and gas reservoir digital twin system | |
| CN106250154B (en) | Visual programming system based on the real-time cloud storage of stream data | |
| CN102799549A (en) | Multi-source-port data processing method and device | |
| CN104407988B (en) | A kind of method and system improving data storage efficiency | |
| CN103631559B (en) | Double-instruction multi-floating-point operand division operation controller | |
| CN104597805A (en) | System and method for achieving circular register shifting based on FIFO |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |