CN104734677B - Single stage comparator - Google Patents
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- CN104734677B CN104734677B CN201510176346.1A CN201510176346A CN104734677B CN 104734677 B CN104734677 B CN 104734677B CN 201510176346 A CN201510176346 A CN 201510176346A CN 104734677 B CN104734677 B CN 104734677B
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Abstract
The invention provides a single stage comparator comprising a first voltage terminal, a second voltage terminal, a first input terminal, a second input terminal, an output terminal and a single stage comparison unit. The single stage comparison unit comprises a first switch, a second switch, a third switch, a first current source, a second current source, an inverter, a capacitor and an MOS tube. The first current source is connected to the position between the first voltage terminal and the drain electrode of the MOS tube; the capacitor is connected to the position between the source electrode of the MOS tube and the second voltage terminal; the first switch is connected to the position between the second input terminal and the gate electrode of the MOS tube; the second switch is connected to the position between the first input terminal and the gate electrode of the MOS tube; the second current source and the third switch are connected to the position between the source electrode of the MOS tube and a second power supply terminal sequentially. The input terminal of the inverter is connected to a connection node between the MOS tube and the first current source, and the output terminal of the inverter is connected to the output terminal of a comparator body. Compared with the prior art, the single stage comparator has the advantages that the influence on the comparator overturning threshold by input errors resulted from device mismatch can be reduced.
Description
【Technical field】
The present invention relates to technical field of circuit design, more particularly to a kind of single-stage comparator.
【Background technology】
The amplifying stage of traditional comparator is typically made up of two-layer configuration.Refer to shown in Fig. 1, it is a kind of traditional ratio
Compared with the circuit diagram of device.Comparator in Fig. 1 includes positive input INP, negative input INM, output end OUT, first
Level amplifying stage 110 and second level amplifying stage 120.Wherein, first order amplifying stage 110 include current source I1, PMOS transistor MP1 and
MP2, nmos pass transistor MN1 and MN2；Second level amplifying stage 120 include current source I2, nmos pass transistor MN3, phase inverter INV1 and
INV2。
Comparator in Fig. 1 in the voltage of the voltage higher than negative input INM of positive input INP, output end OUT
It is changed into high level；When the voltage of positive input INP is less than the voltage of negative input INM, output end OUT is changed into low electricity
It is flat.The specific work process of comparator shown in Fig. 1 is introduced in detail below.
When the voltage of positive input INP is less than the voltage of negative input INM, the electric current of PMOS transistor MP2 will
Electric current (i.e. PMOS transistor MP2 will get more electric currents from current source I1) more than PMOS transistor MP1, and NMOS is brilliant
Body pipe MN2 and MN1 constitute current mirror, then the electric current of nmos pass transistor MN2 is equal to the electric current of nmos pass transistor MN1, is also equal to
The electric current of PMOS transistor MP1.So, electric current of the electric current of PMOS transistor MP2 more than nmos pass transistor MN2, NOS transistors
The grid voltage of MN3 is uprised, and causes the drain voltage step-down of nmos pass transistor MN3, so that output end OUT is changed into low electricity
It is flat.
When the voltage of positive input INP is higher than the input voltage of negative input INM, the electricity of PMOS transistor MP2
Flow the electric current (i.e. PMOS transistor MP1 will get more electric currents from current source I1) less than MP1, and nmos pass transistor
MN2 and MN1 constitutes current mirror, then the electric current of nmos pass transistor MN2 is equal to the electric current of nmos pass transistor MN1, is also equal to PMOS brilliant
The electric current of body pipe MP1.So, electric current of the electric current of PMOS transistor MP2 less than nmos pass transistor MN2, nmos pass transistor MN3's
Grid voltage step-down, causes the drain voltage of nmos pass transistor MN3 to uprise, so that output end OUT is changed into high level.
There are two shortcomings in the comparator in Fig. 1：
There is mismatch condition, i.e. both characteristics in actual production and have differences in the firstth, PMOS transistor MP1 and MP2,
For example, there is certain deviation, and random distribution between both threshold voltages, can so cause equivalent comparator input deviation
, there is deviation so as to cause actual turn threshold in (input offset).For example, positive input INP connects input signal
VIN, negative input INM meet a fixed reference potential VREF, when comparator has input deviation, the turn threshold of comparator
It is changed into VIN=VREF+Vos, wherein, input signal VIN is the input voltage of positive input terminal VIP, and VREF is negative input end INM's
Input voltage, Vos is equivalent input deviation, and preferably comparator turn threshold should be VIN=VREF.In addition, NMOS is brilliant
Mismatch between body pipe MN1 and MN2 also can have shared to above-mentioned input deviation Vos so that the excursion of input deviation Vos is more
Greatly.The input deviation Vos of comparator is 20mV to the maximum shown in usual Fig. 1.
Secondth, because comparator is two-layer configuration, every grade all has parasitic capacitance, when can contribute the delay of output signal
Between, cause the output of output signal OUT to postpone.General series is more, and time delay is bigger.
Therefore, it is necessary to provide a kind of improved technical scheme to solve the above problems.
【The content of the invention】
It is an object of the invention to provide a kind of single-stage comparator, it can not only reduce due to defeated caused by device mismatch
Enter influence of the deviation to comparator turn threshold, but also the time delay of comparator output signal can be reduced.
In order to solve the above problems, the present invention provides a kind of single-stage comparator, and it includes first voltage end, second voltage
End, first input end, the second input, output end and single-stage comparing unit.The single-stage comparing unit is defeated for comparing first
Enter the size of the voltage at end and the voltage of the second input, and export the level signal for representing corresponding comparative result, the single-stage
Comparing unit includes first switch, second switch and the 3rd switch, the first current source and the second current source, phase inverter, electric capacity and
Metal-oxide-semiconductor.Wherein, the first current source is connected between first voltage end and the drain electrode of metal-oxide-semiconductor, and capacitance connection is in the source electrode of metal-oxide-semiconductor
And second voltage end between, first switch is connected between the second input and the grid of metal-oxide-semiconductor, and second switch is connected to first
Between input and the grid of metal-oxide-semiconductor, the second current source and the 3rd switchs source electrode and the second source end for being sequentially connected to metal-oxide-semiconductor
Between.Connecting node between the input of phase inverter and metal-oxide-semiconductor and the first current source is connected, and the output end of phase inverter is used as institute
The output end for stating single-stage comparing unit is connected with the output end of single-stage comparator.
Further, the control end of first switch and the 3rd switch is connected with the first control signal, the control of second switch
End processed is connected with the second control signal, when the first control signal controls first switch and three switch conductions, the second control letter
Number control second switch shut-off, the second input is now connected directly to the grid of the metal-oxide-semiconductor, the single-stage comparing unit
Realize the collection of the voltage of the second input；When the first control signal controls first switch and three switch OFFs, the second control
Signal control second switch conducting processed, first input end is now connected directly to the grid of the metal-oxide-semiconductor, and the single-stage compares
Unit realizes the comparing of the voltage of first input end and the voltage of the second input.By setting the first control signal and the second control
Signal processed so that the second input and first input end are alternately connected to the grid of the metal-oxide-semiconductor successively.
Further, first control signal and the second control signal are clock signal, the first control signal and second
There is certain Dead Time between control signal, to avoid switch S1, S2 and S3 from simultaneously turning on.
Further, the grid of the metal-oxide-semiconductor when gate source voltage of metal-oxide-semiconductor when first switch is turned on is turned on equal to second switch
Source voltage.
Further, the first current source and the second current source are equal, and/or the breadth length ratio W/L designs of metal-oxide-semiconductor is larger.
Further, the first voltage end is power end, and the second voltage end is earth terminal, and the metal-oxide-semiconductor is
Nmos pass transistor；The positive pole of the first current source is connected with power end, and its negative pole is connected with the drain electrode of nmos pass transistor, NMOS crystal
The liner body of pipe is connected with earth terminal；The positive pole of the second current source is connected with the source electrode of nmos pass transistor, and its negative pole and the 3rd is switched
A connection end be connected, the 3rd switch another connection end be connected with earth terminal.
Further, the first voltage end is earth terminal, and the second voltage end is power end, and the metal-oxide-semiconductor is
PMOS transistor；The negative pole of the first current source is connected with earth terminal, and its positive pole is connected with the drain electrode of PMOS transistor, PMOS crystal
The liner body of pipe is connected with the source electrode of PMOS transistor；The negative pole of the second current source is connected with the source electrode of PMOS transistor, its positive pole
A connection end with the 3rd switch is connected, and another connection end of the 3rd switch is connected with power end.
Further, the single-stage comparator also include sampling latch unit, the input of the sampling latch unit with it is anti-
The output end of phase device is connected, and its output end is connected with the output end of single-stage comparator, and the sampling latch unit is used for second
The level signal that the single-stage comparing unit of being sampled when after the switch conduction scheduled time is exported, its output end is exported and keeps sampling
The level signal for arriving.
Further, the use latch units include d type flip flop, data input pin and the phase inverter of the d type flip flop
Output end is connected, and its input end of clock is connected with the 3rd control signal, the output end OUT phases of its output end and single-stage comparator
Even, the 3rd control signal triggers the d type flip flop sampling single-stage comparing unit output after the second switch conducting scheduled time
Level signal.
Compared with prior art, the present invention uses single-stage comparator configuration, and the single-stage comparator passes through a metal-oxide-semiconductor reality
Voltage and the voltage of negative input now to positive input is compared, so as to can not only reduce because device mismatch is led
Influence of the input deviation of cause to comparator turn threshold, but also the time delay of comparator output signal can be reduced.
【Brief description of the drawings】
Technical scheme in order to illustrate more clearly the embodiments of the present invention, below will be to that will use needed for embodiment description
Accompanying drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this
For the those of ordinary skill of field, without having to pay creative labor, other can also be obtained according to these accompanying drawings
Accompanying drawing.Wherein：
Fig. 1 is a kind of circuit diagram of traditional comparator；
Fig. 2 is the circuit diagram of present invention single-stage comparator in one embodiment；
Timing diagrams of the Fig. 3 for control signal CK1, CK2 and CK3 in Fig. 2 in one embodiment；
Fig. 4 is the circuit diagram of present invention single-stage comparator in another embodiment.
【Specific embodiment】
It is below in conjunction with the accompanying drawings and specific real to enable the above objects, features and advantages of the present invention more obvious understandable
The present invention is further detailed explanation to apply mode.
" one embodiment " or " embodiment " referred to herein refers in may be included at least one implementation of the invention
Special characteristic, structure or characteristic." in one embodiment " that different places occur in this manual not refers both to same
Individual embodiment, nor the single or selective embodiment mutually exclusive with other embodiment.Unless stated otherwise, herein
In connection, the word that is electrically connected with of the expression that is connected, connects represents and is directly or indirectly electrical connected.
Comparator in the present invention is single-stage comparator configuration, and the single-stage comparator is realized aligning by a metal-oxide-semiconductor
It is compared to the voltage of input and the voltage of negative input, so as to can not only reduce due to defeated caused by device mismatch
Enter influence of the deviation to comparator turn threshold, but also the time delay of comparator output signal can be reduced.
Refer to shown in Fig. 2, it is the circuit diagram of present invention single-stage comparator in one embodiment.The single-stage
Comparator includes power end V, earth terminal G, positive input INP (or first input end), negative input INM (or the
Two inputs), output end OUT and single-stage comparing unit 210.
The single-stage comparing unit 210 be used for compare positive input INP voltage and negative input INM voltage it is big
It is small, and export the level signal for representing corresponding comparative result.The single-stage comparing unit 210 includes first switch S1, second
Switch S2 and the 3rd switch S3, the first current source I1 and the second current source I2, phase inverter INV1, electric capacity C1 and nmos pass transistor
MN1.Wherein, the first current source I1 is connected between the drain electrode of power end V and nmos pass transistor MN1.Specifically, the first current source
The positive pole of I1 is connected with power end V, and its negative pole is connected with the drain electrode of nmos pass transistor MN1；Electric capacity C1 is connected to nmos pass transistor
Source electrode and earth terminal G between, the liner body of nmos pass transistor MN1 is connected with earth terminal G；First switch S1 is connected to negative sense input
Between end INM and the grid of nmos pass transistor MN1, second switch S2 is connected to positive input INP's and nmos pass transistor MN1
Between grid；The switches of second current source I2 and the 3rd S3 is sequentially connected between the source electrode of nmos pass transistor MN1 and earth terminal G,
Specifically, the positive pole of the second current source I2 is connected with the source electrode of nmos pass transistor MN1, a company of its negative pole and the 3rd switch S3
Connect end to be connected, another connection end of the 3rd switch S3 is connected with earth terminal G.
Connecting node phase between the input of the phase inverter INV1 and nmos pass transistor MN1 and the first current source I1
Even, the output end of phase inverter INV1 is used as the output end of the single-stage comparing unit 210 and the output end OUT phases of single-stage comparator
Even.
The control end of the switches of first switch S1 and the 3rd S3 is connected with the first control signal CK1, the control of second switch S2
End processed is connected with the second control signal CK2.When the first control signal CK1 controlling switches S1 and S3 is turned on, the second control signal
CK2 controlling switches S2 is turned off, and negative input INM is now connected directly to the grid of the nmos pass transistor MN1, the list
Level comparing unit 210 realizes the collection of the voltage of negative input；When the first control signal CK1 controlling switches S1 and S3 shut-offs
When, positive input INP is now connected directly to the nmos pass transistor by the second control signal CK2 controlling switches S3 conductings
The grid of MN1, the single-stage comparing unit 210 realizes the ratio of the voltage of positive input INP and the voltage of negative input INM
Compared with by setting the first control signal CK1 and the second control signal CK2 so that negative input INM and positive input INP
The grid of the nmos pass transistor MN1 is alternately connected to successively.It should be noted that the controls of the first control signal CK1 and second
There is certain Dead Time between signal CK2 processed, to avoid switch S1, S2 and S3 from simultaneously turning on.Refer to shown in Fig. 3, its
It is the timing diagram in one embodiment of control signal CK1, CK2 and CK3 in Fig. 2.In the embodiment shown in fig. 3, control
Signal CK1, CK2 and CK3 are clock signal, wherein, controlling switch S1 and S3 lead when the first control signal CK1 is high level
It is logical, controlling switch S1 and S3 shut-off when being low level；Controlling switch S2 conducting when second control signal CK2 is high level, for low
Controlling switch S2 shut-offs during level, the high level of the first control signal CK1 and the second control signal CK is non-overlapping (to control letter
Number there is certain Dead Time between CK1 and Ck2).
For the ease of understanding the present invention, the worked of single-stage comparing unit 210 in Fig. 2 is specifically introduced below in conjunction with Fig. 3
Journey.
When the first control signal CK1 be high level, the second control signal CK2 be low level when, switch S1 and S3 conducting, open
S2 shut-offs are closed, the grid voltage GN1 of nmos pass transistor MN1 is equal to the voltage of negative input INM, now, nmos pass transistor MN1
Common leakage amplifying stage state is operated in, the source voltage (its voltage VC1 for being equal to electric capacity C1) of nmos pass transistor is input into equal to negative sense
The voltage of end INM subtracts the gate source voltage of nmos pass transistor MN1.
When the first control signal CK1 be low level, the second control signal CK2 be high level when, switch S1 and S3 shut-off, open
When closing S2 conductings, the grid voltage GN1 of nmos pass transistor MN1 is equal to the voltage of positive input INP, now, nmos pass transistor
MN1 is operated in common source amplifying stage state, if the grid source of voltage VC1s and nmos pass transistor MN1 of the grid voltage GN1 more than electric capacity C1
Voltage sum, then the drain voltage reduction of nmos pass transistor MN1, causes phase inverter INV1 to export high level；If grid voltage GN1
The gate source voltage sum of voltage VC1 less than electric capacity C1 and nmos pass transistor MN1, then the drain voltage liter of nmos pass transistor MN1
Height, causes phase inverter INV1 to export low level.
The above-mentioned course of work to single-stage comparing unit 210 is further described now.
When S1 and S3 conductings, switch S2 shut-offs is switched, the voltage VC1=INM-Vgs1 (1) stored on electric capacity C1, its
In, INM is the voltage of negative input INM, and Vgs1 is the grid source electricity that nmos pass transistor MN1 is operated in common leakage amplifying stage state
Pressure.
When S1 and S3 shut-offs, switch S2 conductings is switched, what is compared is on the voltage and electric capacity C1 of positive input INP
The gate source voltage sum VA of voltage VC1 and nmos pass transistor MN1, and VA=VC1+Vgs2 (2), wherein, VC1 is to be deposited on electric capacity C1
The voltage of storage, it is equal with the VC1 in formula (1), and Vgs2 is the grid source that nmos pass transistor MN1 is operated in common source amplifying stage state
Voltage.Formula (1) is substituted into formula (2) to understand, VA=INM-Vgs1+Vgs2, due to the Vgs1 and Vgs2 of nmos pass transistor MN1
Approximately equal, therefore, VA=VM, that is to say, that when S1 and S3 shut-offs, switch S2 conductings is switched, what is actually compared is positive
The size of the voltage of input INP and the voltage of negative input INM, i.e., described single-stage comparing unit 210 is in positive input
The voltage of INP exports high level comparison signal when being more than the voltage of negative input INM, small in the voltage of positive input INP
Low level comparison signal is exported when the voltage of negative input INM.
In order to ensure Vgs1 the and Vgs2 approximately equals of nmos pass transistor MN1, metal-oxide-semiconductor need to as follows be analyzed.
According to metal-oxide-semiconductor saturation region current formula:
Solution can be obtained:
Wherein, Vgs is the gate source voltage of metal-oxide-semiconductor, and I is the drain current (it is equal to source current) of metal-oxide-semiconductor, and μ is migration
Rate, Cox is unit area grid capacitance,It is the breadth length ratio of metal-oxide-semiconductor, Vth is the threshold voltage of metal-oxide-semiconductor.
Understood according to formula (3), nmos pass transistor MN1 is operated in the gate source voltage of common leakage amplifying stage stateWherein, I2 is the current value of the second current source I2 in Fig. 2.
Understand that nmos pass transistor MN1 is operated in the gate source voltage of common source amplifying stage state according to formula (3)Wherein, I1 is the current value of the first current source I1 in Fig. 2.
TypicallyRelative Vth is smaller for item, and especially when the breadth length ratio W/L designs of metal-oxide-semiconductor are larger, this is more
It is small.In addition, the first current source I1 and the second current source I2 designs is equal, help to allow difference between Vgs1 and Vgs2 smaller.
That is, design equal by by the first current source I1 and the second current source I2, and by the breadth length ratio W/ of nmos pass transistor MN1
L designs are larger, can very easily realize Vgs1 the and Vgs2 approximately equals of nmos pass transistor MN1.
In summary, by design so that the nmos pass transistor MN1 in Fig. 2 is in the common gate source voltage for leaking amplifying stage state
Vgs1 and the gate source voltage Vgs2 approximately equals in common source amplifying stage state, so that single-stage comparing unit 210 can accurately compare
The voltage of positive input INP and the voltage swing of negative input INM, so that the comparator in the present invention is in the absence of figure
Comparator of the prior art shown in 1 due to input deviation caused by device mismatch, and due to being that single-stage compares, therefore,
Comparator in the present invention can also reduce the time delay of output signal.
Please continue to refer to shown in Fig. 2, the single-stage comparator in the present invention also includes sampling latch unit 220, the sampling
The input of latch units 220 is connected with the output end of phase inverter INV1, the output end OUT phases of its output end and single-stage comparator
Even, the sampling latch unit 220 is in the second switch S2 conducting scheduled times, (i.e. described single-stage comparing unit 210 to be completed
Compare) when sample the level signal of the single-stage comparing unit 210 output, its output end exports and keeps the level letter for sampling
Number.
In the embodiment shown in Figure 2, shown use latch units 220 include d type flip flop ffdf1, the d type flip flop
The data input pin d of ffdf1 is connected with the output end of phase inverter INV1, and its reset terminal r is connected with earth terminal G, the input of its clock
End ck is connected with the 3rd control signal CK3, and its output end is connected with the output end OUT of single-stage comparator, the 3rd control signal CK3
The d type flip flop is triggered afterwards in the second switch S2 conductings scheduled time (i.e. the second control signal CK2 high level scheduled times)
The level signal of the output of ffdf1 sampling single-stages comparing unit 210.It is to realize single-stage comparing unit 210 using the purpose of d type flip flop
Be operated in comparative result it is correct when read comparative result.When single-stage comparing unit 210 is operated in storage state, (i.e. CK1 is height
During level), single-stage comparing unit 210 is exported may be incorrect, can not now read comparative result；When single-stage comparing unit 210
Entered into from storage state and compare state (when CK2 is high level), may due to setting up correct result than single-stage comparing unit 210
When needing certain setup time (or scheduled time), not up to setup time, comparative result is also possible to mistake, now also unsuitable
Read comparative result.In this embodiment, d type flip flop ffdf1 is trailing edge trigger.
Please continue to refer to shown in Fig. 3, in a clock cycle, the rising of high level one end of the second control signal CK2
Along the rising edge of the high level one end earlier than the 3rd control signal CK3；Under the other end of the high level of the 3rd control signal CK3
Drop can so avoid d type flip flop ffdf1 from sampling along the trailing edge of the other end for being slightly sooner in time than the second control signal CK2 high level
The comparative result of mistake；The high level of rising edge to the 3rd control signal CK3 of high level one end of the second control signal CK2 is another
The time (or time delay) of the trailing edge of one end wants long enough, so that single-stage comparing unit 210 has time enough to export correctly
Comparative result, i.e. this time delay are greater than the time delay of single-stage comparing unit 210.In another embodiment, in Fig. 2 D is touched
Hair device ffdf1 also can be replaced rising edge d type flip flop, as long as it can be adopted when the single-stage comparing unit 210 is completed and compared
The level signal of the output of single-stage comparing unit 210 described in sample.
Refer to shown in Fig. 4, it is the circuit diagram of present invention single-stage comparator in another embodiment, Fig. 4
It is the implementation method based on principle of the invention using PMOS transistor.The difference of Fig. 4 and Fig. 2 is, the NMOS in Fig. 2 is brilliant
Body pipe MN1 replaces with PMOS transistor MP1.
Specifically, the single-stage comparator shown in Fig. 4 includes power end V, earth terminal G, positive input INP, negative sense input
End INM, output end OUT, single-stage comparing unit 410 and sampling latch unit 420.
The single-stage comparing unit 410 includes first switch S1, the 2nd S2 and the 3rd S3, the electricity of the first current source I1 and first
Stream source I2, phase inverter INV1, electric capacity C1 and PMOS transistor MP1.Wherein, current source I1 is connected to earth terminal G and PMOS crystal
Between the drain electrode of pipe MP1, specifically, the negative pole of the first current source I1 is connected with earth terminal G, its positive pole and PMOS transistor MP1
Drain electrode be connected；Electric capacity C1 is connected between the source electrode of PMOS transistor and power end V, the liner body of PMOS transistor MP1 with
The source electrode of PMOS transistor MP1 is connected；First switch S1 be connected to negative input INM and PMOS transistor MP1 grid it
Between, second switch S2 is connected between the grid of positive input INP and PMOS transistor MP1；Second current source I2 and the 3rd
Switch S3 be sequentially connected between the source electrode of PMOS transistor MP1 and power end V, specifically, the negative pole of the second current source I2 with
The source electrode of PMOS transistor MP1 is connected, and its positive pole is connected with a connection end of the 3rd switch S3, and the 3rd switchs another of S3
Connection end is connected with power end V.Between the input and PMOS transistor MP1 and the first current source I1 of the phase inverter INV1
Connecting node is connected, the output end of phase inverter INV1 as the single-stage comparing unit 410 output end.
When the first control signal CK1 controlling switches S1 and S3 is turned on, the second control signal CK2 controlling switches S2 shut-offs,
Negative input INM is now connected directly to the grid of the PMOS transistor MP1, the single-stage comparing unit 410 is realized
The collection of the voltage of negative input INM；When the first control signal CK1 controlling switches S1 and S3 is turned off, the second control signal
CK2 controlling switches S3 is turned on, and positive input INP is now connected directly to the grid of the PMOS transistor MP1, the list
Level comparing unit 410 realizes the comparing of the voltage of positive input INP and the voltage of negative input INM, by setting first
Control signal CK1 and the second control signal CK2 so that negative input INM and positive input INP are alternately connected to successively
The grid of the PMOS transistor MP1.
The input of the sampling latch unit 420 is connected with the output end of phase inverter INV1, its output end and single-stage ratio
Output end OUT compared with device is connected, and the sampling latch unit 420 is used to be adopted when the single-stage comparing unit 410 is completed and compared
The level signal of the output of single-stage comparing unit 410 described in sample, its output end is exported and keeps the level signal for sampling.In Fig. 4
In shown embodiment, the sampling latch unit 420 includes d type flip flop ffdf1, the data of trailing edge d type flip flop ffdf1
Input d is connected with the output end of phase inverter INV1, and its reset terminal r is connected (expression does not reset) with earth terminal G, the input of its clock
End ck is connected with the 3rd control signal CK3, and its output end q is connected with the output end OUT of single-stage comparator, the 3rd control signal
CK3 triggers the level signal of the d type flip flop ffdf1 sampling single-stages comparing unit 210 output in trailing edge.
In one embodiment, in Fig. 4 control signal CK1, Ck2 and the timing diagram of CK3 is still as shown in Figure 3.
When the first clock signal CK1 is high level, and second clock signal CK2 is low level, switch S1 and S3 is turned on, opened
S2 shut-offs are closed, the grid voltage GN1 of PMOS transistor MP1 is equal to the voltage of negative input INM, now, PMOS transistor MP1
Be operated in it is common leakage amplifying stage state, the source voltage VC1=INM+ ∣ Vgsp1 ∣ of PMOS transistor MP1, wherein, VC1 be electric capacity C1
And the voltage of the connecting node VC1 between the source electrode of PMOS transistor MP1, INM is the voltage of comparator negative input INM,
Vgsp1 is the gate source voltage that PMOS MP1 is operated in common leakage amplifying stage state.
When the first clock signal CK1 is low level, and second clock signal CK2 is high level, switch S1 and S3 is turned off, opened
S2 conductings are closed, the grid voltage GN1 of PMOS transistor MP1 is equal to the voltage of positive input INP, now, PMOS transistor MP1
Common source amplifying stage state is operated in, what is compared is the size of INP+ | Vgsp2 | and VC1 voltages, wherein, INP is positive input
The voltage of INP, Vgsp2 is the gate source voltage that PMOS MP1 is operated in common source amplifying stage state, and VC1 is the voltage of node VC1
(VC1=INM+ ∣ Vgsp1 ∣), if the drain voltage reduction of (INP+ | Vgsp2 |) ＞ VC1, PMOS transistor MP1, causes anti-phase
Device INV1 exports high level, and comparator output terminal OUT is high level after d type flip flop ffdf1 samples；If (INP+ | Vgsp2
|) ＜ VC1, the drain voltage of PMOS transistor MP1 raises, and causes phase inverter INV1 to export low level, by d type flip flop ffdf1
Comparator output terminal OUT is low level after sampling.
Design equal by by the first current source I1 and the second current source I2, and by the breadth length ratio W/L of PMOS transistor MP1
Design is larger, can very easily realize that Vgsp1 and Vgsp2 are equal.So, what single-stage comparing unit 410 actually compared is
The size of the voltage of positive input INP and the voltage of negative input INM.
In summary, the comparator in the present invention includes single-stage comparing unit, and the single-stage comparing unit passes through a metal-oxide-semiconductor
Realization is compared to the voltage of positive input and the voltage of negative input, so that the comparator in the present invention is not deposited
The input deviation caused by the comparator of the prior art shown in Fig. 1 is due to device mismatch, and due to being that single-stage compares, because
This, the comparator in the present invention can also reduce the time delay of output signal.
In the present invention, " connection ", connected, " company ", " connecing " etc. represents the word being electrical connected, unless otherwise instructed, then
Represent direct or indirect electric connection.
It is pointed out that any change that one skilled in the art is done to specific embodiment of the invention
All without departing from the scope of claims of the present invention.Correspondingly, the scope of claim of the invention is also not merely limited to
In previous embodiment.
Claims (8)
1. a kind of single-stage comparator, it is characterised in that it includes first voltage end, second voltage end, first input end, second defeated
Enter end, output end and single-stage comparing unit,
The single-stage comparing unit is used for the size of the voltage of the voltage and the second input that compare first input end, and exports table
Show the level signal of corresponding comparative result, the single-stage comparing unit includes first switch, second switch and the 3rd switch, first
Current source and the second current source, phase inverter, electric capacity and metal-oxide-semiconductor,
Wherein, the first current source is connected between first voltage end and the drain electrode of metal-oxide-semiconductor, capacitance connection in metal-oxide-semiconductor source electrode and
Between second voltage end, first switch is connected between the second input and the grid of metal-oxide-semiconductor, and it is defeated that second switch is connected to first
Enter end and the grid of metal-oxide-semiconductor between, the second current source and the 3rd switch be sequentially connected to metal-oxide-semiconductor source electrode and second source end it
Between,
Connecting node between the input of phase inverter and metal-oxide-semiconductor and the first current source is connected, and the output end of phase inverter is used as institute
The output end for stating single-stage comparing unit is connected with the output end of single-stage comparator,
The control end of first switch and the 3rd switch is connected with the first control signal, and the control end of second switch is controlled with second
Signal is connected, when the first control signal controls first switch and three switch conductions, the second control signal control second switch
Shut-off, the second input is now connected directly to the grid of the metal-oxide-semiconductor, and the single-stage comparing unit realizes the second input
Voltage collection；When the first control signal controls first switch and three switch OFFs, the second control signal control second
Switch conduction, first input end is now connected directly to the grid of the metal-oxide-semiconductor, and the single-stage comparing unit realizes that first is defeated
Enter the comparing of the voltage at end and the voltage of the second input,
By setting the first control signal and the second control signal so that the second input and first input end alternately connect successively
It is connected to the grid of the metal-oxide-semiconductor.
2. single-stage comparator according to claim 1, it is characterised in that first control signal and the second control signal
Be clock signal, there is certain Dead Time between the first control signal and the second control signal, with avoid switch S1, S2 and
S3 is simultaneously turned on.
3. single-stage comparator according to claim 1, it is characterised in that
The gate source voltage of the metal-oxide-semiconductor when gate source voltage of metal-oxide-semiconductor when first switch is turned on is turned on equal to second switch.
4. single-stage comparator according to claim 3, it is characterised in that
First current source and the second current source are equal.
5. according to any described single-stage comparators of claim 1-4, it is characterised in that
The first voltage end is power end, and the second voltage end is earth terminal, and the metal-oxide-semiconductor is nmos pass transistor；
The positive pole of the first current source is connected with power end, and its negative pole is connected with the drain electrode of nmos pass transistor, the lining of nmos pass transistor
Body is connected with earth terminal；
The positive pole of the second current source is connected with the source electrode of nmos pass transistor, and its negative pole is connected with a connection end of the 3rd switch,
Another connection end of 3rd switch is connected with earth terminal.
6. according to any described single-stage comparators of claim 1-4, it is characterised in that
The first voltage end is earth terminal, and the second voltage end is power end, and the metal-oxide-semiconductor is PMOS transistor；
The negative pole of the first current source is connected with earth terminal, and its positive pole is connected with the drain electrode of PMOS transistor, the lining of PMOS transistor
Body is connected with the source electrode of PMOS transistor；
The negative pole of the second current source is connected with the source electrode of PMOS transistor, and its positive pole is connected with a connection end of the 3rd switch,
Another connection end of 3rd switch is connected with power end.
7. according to any described single-stage comparators of claim 1-4, it is characterised in that
It also includes sampling latch unit, and the input of the sampling latch unit is connected with the output end of phase inverter, its output end
Output end with single-stage comparator is connected, and the sampling latch unit is used for the institute that sampled when after the second switch conducting scheduled time
The level signal of single-stage comparing unit output is stated, its output end is exported and keeps the level signal for sampling.
8. single-stage comparator according to claim 7, it is characterised in that
The sampling latch unit includes d type flip flop, and the data input pin of the d type flip flop is connected with the output end of phase inverter, its
Input end of clock is connected with the 3rd control signal, and its output end is connected with the output end OUT of single-stage comparator, the 3rd control signal
The level signal of the d type flip flop sampling single-stage comparing unit output is triggered after the second switch conducting scheduled time.
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| CN104113310A (en) * | 2013-04-22 | 2014-10-22 | 三星显示有限公司 | Mismatched Differential Circuit |
| CN104320139A (en) * | 2014-09-29 | 2015-01-28 | 清华大学 | Charge matching-based offset correction method of full-symmetric four-terminal dynamic comparator |
| CN204578500U (en) * | 2015-04-14 | 2015-08-19 | 无锡中星微电子有限公司 | Single-stage comparator |
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| EP1511173A2 (en) * | 2003-08-28 | 2005-03-02 | Flying Mole Corporation | Power conversion apparatus and dead time generator |
| CN102420594A (en) * | 2011-12-15 | 2012-04-18 | 无锡中星微电子有限公司 | Comparator |
| CN102843136A (en) * | 2012-09-15 | 2012-12-26 | 复旦大学 | Method for correcting offset of high-speed high-precision large-range low-power-consumption dynamic comparator |
| CN104113310A (en) * | 2013-04-22 | 2014-10-22 | 三星显示有限公司 | Mismatched Differential Circuit |
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