CN104733577A - LED chip of perpendicular structure and manufacturing method thereof - Google Patents
LED chip of perpendicular structure and manufacturing method thereof Download PDFInfo
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- CN104733577A CN104733577A CN201510144465.9A CN201510144465A CN104733577A CN 104733577 A CN104733577 A CN 104733577A CN 201510144465 A CN201510144465 A CN 201510144465A CN 104733577 A CN104733577 A CN 104733577A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 72
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 72
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims description 39
- 230000004888 barrier function Effects 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 22
- 239000010931 gold Substances 0.000 claims description 16
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 14
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 12
- 229910052737 gold Inorganic materials 0.000 claims description 12
- 239000011651 chromium Substances 0.000 claims description 8
- 230000008569 process Effects 0.000 claims description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 6
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052804 chromium Inorganic materials 0.000 claims description 6
- 229910052697 platinum Inorganic materials 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000000460 chlorine Substances 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 4
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910001128 Sn alloy Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 229910052801 chlorine Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- WUUZKBJEUBFVMV-UHFFFAOYSA-N copper molybdenum Chemical compound [Cu].[Mo] WUUZKBJEUBFVMV-UHFFFAOYSA-N 0.000 claims description 3
- SBYXRAKIOMOBFF-UHFFFAOYSA-N copper tungsten Chemical compound [Cu].[W] SBYXRAKIOMOBFF-UHFFFAOYSA-N 0.000 claims description 3
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 2
- 239000011787 zinc oxide Substances 0.000 claims description 2
- 238000004806 packaging method and process Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910015269 MoCu Inorganic materials 0.000 description 1
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 229910004541 SiN Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000005303 weighing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/58—Optical field-shaping elements
- H01L33/60—Reflective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The invention discloses an LED chip of a perpendicular structure and a manufacturing method thereof. The manufacturing method comprises the steps that a first substrate is provided, and an N-type gallium nitride layer, a quantum well layer and a P-type gallium nitride layer are formed on the first substrate; the first substrate is etched to form a first groove, and the N-type gallium nitride layer is exposed; an Ohmic contact layer, a mirror and an insulating layer are formed on the P-type gallium nitride layer, the insulating layer covers the first groove, the portion, in the center of the first groove, of the insulating layer is etched, and the N-type gallium nitride layer is exposed; an N electrode is formed in the first groove, and a bonding layer is formed on the insulating layer and the N electrode; the bonding layer is in bonding with a bonding substrate, and the first substrate is removed; the N-type gallium nitride layer, the quantum well layer and the P-type gallium nitride layer are etched, and a second groove is formed; a P electrode is formed in the second groove. The obtained LED chip of the perpendicular structure is further provided. The chip packaging difficulty is simplified, the expanding evenness of current is improved, and driving under high current is achieved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of light emitting diode (LED) chip with vertical structure and manufacture method thereof.
Background technology
Light-emitting diode (Light Emitting Diode is called for short LED) is a kind of light emitting semiconductor device, the photoelectric properties features such as have energy consumption low, volume is little, the life-span is long, good stability, response is fast, and emission wavelength is stable.The application of wide model has been had at present in fields such as illumination, household electrical appliances, display screen, indicator lights.
In recent years, traditional formal dress structure LED chip is owing to limitting by structure and material, and light emission rate and operating current etc. can not meet development need.In addition, in order to improve quality of lighting and the integrated level of LED product, unit are light efficiency (lm/W/cm2) has become the important indicator weighing LED chip, and formal dress structure LED chip is weak equally to this.
In order to overcome these deficiencies of formal dress led chip, industry proposes a kind of light emitting diode (LED) chip with vertical structure.Light emitting diode (LED) chip with vertical structure can solve these difficult problems well by using the good substrate of heat-conductivity conducting and surface texture technology, thus the heat-sinking capability of light emitting diode (LED) chip with vertical structure and current expansion ability are improved, become the focus product meeting this development trend and require.
But as shown in Figure 1, the P electrode 1 of light emitting diode (LED) chip with vertical structure and N electrode 2 are in the both sides up and down of chip, and its current expansion ability is to be further improved in addition.
Summary of the invention
Main purpose of the present invention is, provides a kind of light emitting diode (LED) chip with vertical structure and manufacture method thereof, improves the current expansion ability of light emitting diode (LED) chip with vertical structure, and simplifies encapsulation difficulty.
For solving the problems of the technologies described above, the invention provides a kind of manufacture method of light emitting diode (LED) chip with vertical structure, comprising:
There is provided front-end architecture, described front-end architecture comprises the first substrate, is formed at the n type gallium nitride layer on described first substrate, quantum well layer and P type gallium nitride layer;
Etch described P type gallium nitride layer and quantum well layer forms the first groove, expose n type gallium nitride layer;
Described P type gallium nitride layer forms ohmic contact layer, speculum and insulating barrier successively, and described insulating barrier covers described first groove, and etching insulating layer is positioned at the part of the first groove central authorities afterwards, exposes n type gallium nitride layer;
In described first groove, form N electrode, described insulating barrier and N electrode form bonded layer;
Bonded substrate is provided, by described bonded layer and described front-end architecture phase bonding, and removes the first substrate;
Etch described n type gallium nitride layer, quantum well layer and P type gallium nitride layer, form the second groove, expose ohmic contact layer;
Surface coarsening process is carried out to described n type gallium nitride layer; And
P electrode is formed in described second groove.
Optionally, for the manufacture method of described light emitting diode (LED) chip with vertical structure, the employing that is formed as of described first groove comprises boron chloride, chlorine and argon gas and etches under plasma environment.
Optionally, for the manufacture method of described light emitting diode (LED) chip with vertical structure, the material of described ohmic contact layer comprises tin indium oxide or zinc oxide, the material of described speculum comprises silver, aluminium, and the material of described insulating barrier comprises one in silica, silicon nitride, silicon oxynitride, aluminium oxide, titanium oxide or laminating structure.
Optionally, for the manufacture method of described light emitting diode (LED) chip with vertical structure, the material of described N electrode comprises nickel/gold, chromium/aluminium/titanium/platinum/gold, chromium/platinum/gold; The material of described bonded layer comprises gold, tin, gold-tin alloy.
Optionally, for the manufacture method of described light emitting diode (LED) chip with vertical structure, the material of described bonded substrate comprises silicon, copper, tungsten copper or molybdenum-copper.
Optionally, for the manufacture method of described light emitting diode (LED) chip with vertical structure, wet etching is adopted to carry out described surface coarsening process.
Accordingly, the present invention also provides a kind of light emitting diode (LED) chip with vertical structure obtained by the manufacture method of described light emitting diode (LED) chip with vertical structure, comprising:
Bonded substrate;
The stacked bonded layer be positioned in described bonded substrate, insulating barrier, speculum, ohmic contact layer, P type gallium nitride layer and quantum well layer;
Run through the N electrode of described insulating barrier, speculum, ohmic contact layer, P type gallium nitride layer and quantum well layer, described insulating barrier realizes the electric isolution of N electrode and P type gallium nitride layer, quantum well layer, and described N electrode is electrically connected described bonded layer;
Be positioned at the n type gallium nitride layer in described quantum well layer and N electrode, described n type gallium nitride layer has rough surface;
Run through the P electrode of described P type gallium nitride layer, quantum well layer and n type gallium nitride layer, described P electrode is electrically connected described ohmic contact layer.
In light emitting diode (LED) chip with vertical structure provided by the invention and manufacture method thereof, N electrode runs through insulating barrier, speculum, ohmic contact layer, P type gallium nitride layer and quantum well layer, is connected to bonded substrate, with bonded substrate jointly as conductive electrode; P electrode runs through P type gallium nitride layer, quantum well layer and n type gallium nitride layer, is connected to ohmic contact layer.Compared to existing technology, simplify chip package difficulty, further improve the expansion uniformity of electric current, achieve driving at higher currents.
Accompanying drawing explanation
Fig. 1 is the structural representation of light emitting diode (LED) chip with vertical structure of the prior art;
Fig. 2 is the flow chart of the manufacture method of light emitting diode (LED) chip with vertical structure in the present invention;
Fig. 3-Figure 11 is the schematic diagram of device architecture in the process of the manufacture method of light emitting diode (LED) chip with vertical structure in the embodiment of the present invention.
Embodiment
Below in conjunction with schematic diagram, light emitting diode (LED) chip with vertical structure of the present invention and manufacture method thereof are described in more detail, which show the preferred embodiments of the present invention, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, a large amount of implementation detail must be made to realize the specific objective of developer, such as, according to regarding system or the restriction about business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, more specifically the present invention is described by way of example with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is, provides a kind of manufacture method of light emitting diode (LED) chip with vertical structure, comprising:
Step S101, provides front-end architecture, and described front-end architecture comprises the first substrate, is formed at the n type gallium nitride layer on described first substrate, quantum well layer and P type gallium nitride layer;
Step S102, etches described P type gallium nitride layer and quantum well layer forms the first groove, exposes n type gallium nitride layer;
Step S103, described P type gallium nitride layer forms ohmic contact layer, speculum and insulating barrier successively, and described insulating barrier covers described first groove, and etching insulating layer is positioned at the part of the first groove central authorities afterwards, exposes n type gallium nitride layer;
Step S104, forms N electrode, described insulating barrier and N electrode forms bonded layer in described first groove;
Step S105, provides bonded substrate, by described bonded layer and described front-end architecture phase bonding, and removes the first substrate;
Step S106, etches described n type gallium nitride layer, quantum well layer and P type gallium nitride layer, forms the second groove, expose ohmic contact layer;
Step S107, carries out surface coarsening process to described n type gallium nitride layer; And
Step S108, forms P electrode in described second groove.
Below enumerate the preferred embodiment of described light emitting diode (LED) chip with vertical structure and manufacture method thereof, to clearly demonstrate content of the present invention, will be clear that, content of the present invention is not restricted to following examples, and other improvement by the routine techniques means of those of ordinary skill in the art are also within thought range of the present invention.
Please refer to Fig. 2, and composition graphs 3-Figure 11, wherein Fig. 2 is the flow chart of the manufacture method of light emitting diode (LED) chip with vertical structure in the present invention; Fig. 3 ~ Figure 11 is the schematic diagram of device architecture in the process of the manufacture method of light emitting diode (LED) chip with vertical structure in the embodiment of the present invention.
As shown in Figure 2, the manufacture method of described light emitting diode (LED) chip with vertical structure comprises:
First, please refer to Fig. 3 and perform step S101, there is provided front-end architecture, described front-end architecture comprises the first substrate 10, is formed at the n type gallium nitride layer (N-GaN) 11 of on described first substrate 10, quantum well layer (MQW) 12 and P type gallium nitride layer (P-GaN) 13.Described first substrate 10 can be Sapphire Substrate, and the preparation of described front-end architecture belongs to common practise, does not describe in detail at this.
Then, please refer to Fig. 4 a and Fig. 4 b, execution step S102, etches described P type gallium nitride layer 13 and quantum well layer 12 forms the first groove 14, exposes n type gallium nitride layer 11.Wherein Fig. 4 a is cutaway view, and Fig. 4 b is vertical view, namely visible, and the first groove 14 is formed in the middle of front-end architecture, and certainly, the quantity of the quantity basis chip unit of the first groove 14 can corresponding change.
In this step, preferably, boron chloride (BCl is utilized
3), chlorine (Cl
2) and the gas such as argon gas (Ar) etch under plasmoid, wherein, n type gallium nitride layer 11 also can be partially etched.According to needs of production, can control to etching condition the sidewall slope realizing the first groove 14.
Then, please refer to Fig. 5-Fig. 6, perform step S103, described P type gallium nitride layer 13 forms ohmic contact layer 15, speculum 16 and insulating barrier 17 successively, described insulating barrier 17 covers described first groove 14, etching insulating layer 17 is positioned at the part of the first groove 14 central authorities afterwards, exposes n type gallium nitride layer 11.This partial insulative layer removed is by occupied by the N electrode that formed afterwards.Concrete, in the present invention, the material of described ohmic contact layer 15 can be tin indium oxide (ITO) or zinc oxide (ZnO) etc., and the material of speculum 16 can be metal such as silver (Ag), aluminium (Al) etc.The material of insulating barrier 17 can be such as SiO
2, SiN, SiON, Al
2o
3, TiO
2in one or more, or the laminating structure (DBR) based on this type of material.Insulating barrier 17 can adopt the method deposition of PECVD to be formed, and electron beam evaporation plating mode also can be adopted to be formed.
Afterwards, please refer to Fig. 7, perform step S104, in described first groove, form N electrode 18, described insulating barrier 17 and N electrode 18 form bonded layer 19.The material of described N electrode 18 can be such as nickel (Ni)/gold (Au), chromium (Cr)/aluminium (Al)/titanium (Ti)/platinum (Pt)/gold (Au), chromium (Cr)/platinum (Pt)/gold (Au) etc., the material of bonded layer 19 can be such as gold (Au), tin (Sn), gold-tin alloy (AuSn) etc.
Afterwards, please refer to Fig. 8, perform step S105, bonded substrate 20 is provided, by described bonded layer 19 and described front-end architecture phase bonding, and removes the first substrate 10.Bonded substrate 20 can be such as comprise the materials such as silicon (Si), copper (Cu), tungsten copper (WCu) alloy or molybdenum copper (MoCu) alloy, thus possesses preferably heat-conductivity conducting.Thus, N electrode 18 just electrically communicates with bonded substrate 20, namely in the present invention bonded substrate 20 as a conductive electrode of light emitting diode (LED) chip with vertical structure.The removal of the first substrate 10 can adopt laser irradiation or chemical method to peel off.
Afterwards, please refer to Fig. 9, perform step S106, etch described n type gallium nitride layer 11, quantum well layer 12 and P type gallium nitride layer 13, form the second groove 21, expose ohmic contact layer 15.The etching of this step can adopt ICP technique to carry out, and etches mesa (step), i.e. mesa etching.
Then, please refer to Figure 10, perform step S107, surface coarsening process is carried out to described n type gallium nitride layer 11.Described surface coarsening processing example is as being employing potassium hydroxide (KOH) solution, sulfuric acid (H
2sO
4) solution etc. carries out wet etching, obtains rough surface 22, to improve light emission rate.
Finally, please refer to Figure 11, perform step S108, in described second groove 21, form P electrode 23.P electrode 23 can be formed by evaporation, and its material can with reference to the material of N electrode.
Thus, light emitting diode (LED) chip with vertical structure manufacture of the present invention completes, and please continue to refer to Figure 11, described light emitting diode (LED) chip with vertical structure comprises:
Bonded substrate 20; The stacked bonded layer 19 be positioned in described bonded substrate 20, insulating barrier 17, speculum 16, ohmic contact layer 15, P type gallium nitride layer 13 and quantum well layer 12; Run through the N electrode 18 of described insulating barrier 17, speculum 16, ohmic contact layer 15, P type gallium nitride layer 13 and quantum well layer 12, described insulating barrier 17 realizes the electric isolution of N electrode 18 and P type gallium nitride layer 13, quantum well layer 12, and described N electrode 18 is electrically connected described bonded layer 19; Be positioned at the n type gallium nitride layer 11 in described P type gallium nitride layer 12 and N electrode 18, described n type gallium nitride layer 11 has rough surface 22; Run through the P electrode 23 of described P type gallium nitride layer 13, quantum well layer 12 and n type gallium nitride layer 11, described P electrode 23 is electrically connected on ohmic contact layer 15.
The P of light emitting diode (LED) chip with vertical structure, N electrode are placed in the both sides of chip by the present invention, bonded substrate is specifically utilized to connect the bottom electrode of N electrode as LED chip, P electrode is then prepared in above bonded substrate by mesa lithographic method, and be embedded in epitaxial layer of gallium nitride (P type gallium nitride layer, quantum well layer and n type gallium nitride layer), at guarantee chip while reliability and light emission rate, the ease of chip package can be improved.Meanwhile, it is more even that the light emitting diode (LED) chip with vertical structure in the present invention can make current expansion distribute, and compared to traditional light emitting diode (LED) chip with vertical structure, can drive under higher electric current.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (7)
1. a manufacture method for light emitting diode (LED) chip with vertical structure, comprising:
There is provided front-end architecture, described front-end architecture comprises the first substrate, is formed at the n type gallium nitride layer on described first substrate, quantum well layer and P type gallium nitride layer;
Etch described P type gallium nitride layer and quantum well layer forms the first groove, expose n type gallium nitride layer;
Described P type gallium nitride layer forms ohmic contact layer, speculum and insulating barrier successively, and described insulating barrier covers described first groove, and etching insulating layer is positioned at the part of the first groove central authorities afterwards, exposes n type gallium nitride layer;
In described first groove, form N electrode, described insulating barrier and N electrode form bonded layer;
Bonded substrate is provided, by described bonded layer and described front-end architecture phase bonding, and removes the first substrate;
Etch described n type gallium nitride layer, quantum well layer and P type gallium nitride layer, form the second groove, expose ohmic contact layer;
Surface coarsening process is carried out to described n type gallium nitride layer; And
P electrode is formed in described second groove.
2. the manufacture method of light emitting diode (LED) chip with vertical structure as claimed in claim 1, is characterized in that, the employing that is formed as of described first groove comprises boron chloride, chlorine and argon gas and etches under plasma environment.
3. the manufacture method of light emitting diode (LED) chip with vertical structure as claimed in claim 1, it is characterized in that, the material of described ohmic contact layer comprises tin indium oxide or zinc oxide, the material of described speculum comprises silver, aluminium, and the material of described insulating barrier comprises one in silica, silicon nitride, silicon oxynitride, aluminium oxide, titanium oxide or laminating structure.
4. the manufacture method of light emitting diode (LED) chip with vertical structure as claimed in claim 1, it is characterized in that, the material of described N electrode comprises nickel/gold, chromium/aluminium/titanium/platinum/gold, chromium/platinum/gold; The material of described bonded layer comprises gold, tin, gold-tin alloy.
5. the manufacture method of light emitting diode (LED) chip with vertical structure as claimed in claim 1, it is characterized in that, the material of described bonded substrate comprises silicon, copper, tungsten copper or molybdenum-copper.
6. the manufacture method of light emitting diode (LED) chip with vertical structure as claimed in claim 1, is characterized in that, adopts wet etching to carry out described surface coarsening process.
7., by the light emitting diode (LED) chip with vertical structure that the manufacture method of the light emitting diode (LED) chip with vertical structure in claim 1-6 described in any one is obtained, it is characterized in that, comprising:
Bonded substrate;
The stacked bonded layer be positioned in described bonded substrate, insulating barrier, speculum, ohmic contact layer, P type gallium nitride layer and quantum well layer;
Run through the N electrode of described insulating barrier, speculum, ohmic contact layer, P type gallium nitride layer and quantum well layer, described insulating barrier realizes the electric isolution of N electrode and P type gallium nitride layer, quantum well layer, and described N electrode is electrically connected described bonded layer;
Be positioned at the n type gallium nitride layer in described quantum well layer and N electrode, described n type gallium nitride layer has rough surface;
Run through the P electrode of described P type gallium nitride layer, quantum well layer and n type gallium nitride layer, described P electrode is electrically connected described ohmic contact layer.
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| CN201510144465.9A CN104733577A (en) | 2015-03-30 | 2015-03-30 | LED chip of perpendicular structure and manufacturing method thereof |
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