CN104732946B - A kind of shift register and display device - Google Patents
A kind of shift register and display device Download PDFInfo
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- CN104732946B CN104732946B CN201510170216.7A CN201510170216A CN104732946B CN 104732946 B CN104732946 B CN 104732946B CN 201510170216 A CN201510170216 A CN 201510170216A CN 104732946 B CN104732946 B CN 104732946B
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Abstract
The embodiment of the invention provides a kind of shift register and display device, it is used to solve in existing shift register because the current potential of lower drawknot node is the control of Electric potentials by upper drawknot node, once the current potential of upper drawknot node fluctuates, the current potential that may result in lower drawknot node is abnormal, so as to abnormal problem occurs in the signal for causing shift register output.The shift register is using the first pull-up module and the current potential of the upper drawknot node of drop-down module control, and using the second current potential for pulling up module and the lower drawknot node of pull-down node control module control, so as to avoiding the current potential of lower drawknot node by the control of Electric potentials of upper drawknot node, and then the current potential of lower drawknot node is avoided to be subject to the current potential of upper drawknot node to influence.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of shift register and display device.
Background technology
Liquid crystal display panel is made up of the liquid crystal pixel matrix of two dimension, and the drive device of liquid crystal display panel is driven including grid
The display data of input is latched and is converted into analog signal by dynamic device and data driven unit, data driven unit in order,
The data wire of liquid crystal display panel is scanned successively；Gate drive apparatus include several shift registers, per one-level shift LD
The signal of the control signal output of device can all be transferred to its upper level shift register reset signal input and its
The control signal input of next stage shift register.The clock signal of input is converted to unlatching or closed by every grade of shift register
Signal is closed from its control signal output output to corresponding gate line.
The typical structure of existing shift register as shown in figure 1, when input signal INPUT is high level, transistor
M1 is turned on, and upper drawknot node PU is high level, therefore, transistor M6 conductings, because now clock signal clk is low level, crystal
Pipe M5 is turned off, therefore, lower drawknot node PD is turned off for low level VSS, transistor M7 and transistor M8, because upper drawknot node PU is
High level, therefore, transistor M3 conductings export clock signal clk now, now the output end OUTPUT of shift register
It is low level.After clock signal clk is changed into high level from low level, input signal INPUT is changed into low level from high level, brilliant
Body pipe M1 is turned off, but due to the memory action of electric capacity C1, therefore, upper drawknot node PU maintains high level, transistor M3, transistor
M5 and transistor M6 are both turned on, and now the output end OUTPUT of shift register is high level, is more than in the size of transistor M6
During the size of transistor M5, the current potential of lower drawknot node PD is still low level.When reset signal RESET is high level, crystal
Pipe M2 and transistor M4 is turned on, and this can cause that the current potential of drawknot node PU is changed into low level, and transistor M3 and transistor M6 is turned off.
From figure 1 it appears that due to the upper drawknot node PU of grid connection of transistor M6, therefore, the electricity of lower drawknot node PD
Position is the control of Electric potentials by upper drawknot node PU, similarly, due to the lower drawknot node PD of the grid connection of transistor M8, therefore, on
The current potential of drawknot node PU is also the control of Electric potentials by lower drawknot node PD, that is to say, that the current potential and lower drawknot of upper drawknot node PU
The current potential of point PD is mutually control, and in this case, once the current potential of upper drawknot node PU fluctuates, this may result in
The current potential of lower drawknot node PD is abnormal, so as to exception occurs in the signal for causing shift register output.
In sum, lower drawknot node (i.e. in the inoperative period of shift register, will be shifted in existing shift register
The grid of transistor M7, M8 that the current potential of the upper drawknot node in the output end and shift register of register is dragged down) current potential
It is that (i.e. when the gate line of shift register connection is selected, i.e. the working hour shift of shift register is posted by upper drawknot node
The grid of the transistor for being used to driving gate line in storage, the grid of transistor M3 in Fig. 1) control of Electric potentials, once pull-up
The current potential of node fluctuates, and the current potential that may result in lower drawknot node is abnormal, so as to cause the letter of shift register output
Number occur abnormal.
The content of the invention
A kind of shift register and display device are the embodiment of the invention provides, is used to solve in existing shift register
In due to the current potential of lower drawknot node be the control of Electric potentials by upper drawknot node, once the current potential of so upper drawknot node fluctuates,
The current potential that may result in lower drawknot node is abnormal, so as to abnormal problem occurs in the signal for causing shift register output.
Based on above mentioned problem, a kind of shift register provided in an embodiment of the present invention, including the first pull-up module, on second
Drawing-die block, transport module, drop-down module and lower drawknot node control module；The first pull-up module, output module and lower drawing-die
The connected tie point of block is upper drawknot node；The tie point that the drop-down module is connected with the lower drawknot node control module is drop-down
Node；The tie point that the second pull-up module, the drop-down module are connected with the pull-down node control module is lower drawknot
The control node of point；
The first pull-up module, for when it is high level to gate trigger signal, upper drawknot node being set into high level；
The second pull-up module, for when the gating trigger signal is high level, by the control section of lower drawknot node
Point is set to high level；
The transport module, the signal for storing the upper drawknot node, and on described the signal of drawknot node control
Under, the clock signal output that will be received；
The drop-down module, for when it is high level to gate end signal, by the upper drawknot node, the lower drawknot node
Control node and the output end of the shift register be set to low level；And the lower drawknot node current potential be high level
When, the output end of the upper drawknot node and the shift register is set to low level；
The pull-down node control module, the signal of the control node for storing the lower drawknot node；And under described
When the control node of drawknot node is high level, the lower drawknot node is set to low level；And in the control section of the lower drawknot node
When point is for low level, the lower drawknot node is set to high level.
A kind of display device provided in an embodiment of the present invention, including shift register provided in an embodiment of the present invention.
The beneficial effect of the embodiment of the present invention includes：
Shift register provided in an embodiment of the present invention and display device, because the current potential of upper drawknot node is by drawing-die on first
Block and drop-down module are controlled, and the current potential of lower drawknot node is controlled by the second pull-up module, pull-down node control module and drop-down module,
When this current potential for avoiding lower drawknot node receives the control of Electric potentials of upper drawknot node, once the current potential of upper drawknot node fluctuates, and may
The current potential of lower drawknot node can be caused abnormal, so as to abnormal problem occurs in the signal for causing shift register output.
Brief description of the drawings
Fig. 1 is the structural representation of shift register of the prior art；
Fig. 2 is one of structural representation of shift register provided in an embodiment of the present invention；
Fig. 3 is one of structural representation of shift register provided in an embodiment of the present invention；
Fig. 4 is one of structural representation of shift register provided in an embodiment of the present invention；
Fig. 5 is one of structural representation of shift register provided in an embodiment of the present invention；
Fig. 6 is one of structural representation of shift register provided in an embodiment of the present invention；
Fig. 7 is the working timing figure of shift register provided in an embodiment of the present invention.
Specific embodiment
A kind of shift register provided in an embodiment of the present invention and display device, using the disparate modules in shift register
Independently to control the current potential of upper drawknot node and the current potential of lower drawknot node, so that the current potential of lower drawknot node does not receive upper drawknot
The influence of point current potential, it is to avoid when the current potential of upper drawknot node fluctuates, the current potential of caused lower drawknot node is abnormal, so as to lead
The signal of shift register output is caused abnormal problem occur.
With reference to Figure of description, to the specific of a kind of shift register provided in an embodiment of the present invention and display device
Implementation method is illustrated.
A kind of shift register provided in an embodiment of the present invention, as shown in Fig. 2 including in the first pull-up module 21, second
Drawing-die block 22, transport module 23, drop-down module 24 and lower drawknot node control module 25；First pull-up module 21, transport module 23
The tie point being connected with drop-down module 24 is upper drawknot node PU；The connection that drop-down module 24 is connected with lower drawknot node control module 25
Point is lower drawknot node PD；Under the tie point that second pull-up module 22, drop-down module 24 are connected with pull-down node control module 25 is
The control node PDC of drawknot node；
First pull-up module 21, for when it is high level to gate trigger signal OUTN-1, upper drawknot node PU being set into height
Level；
Second pull-up module 22, for when it is high level to gate trigger signal OUTN-1, by the control section of lower drawknot node
Point PDC is set to high level；
Under the control of transport module 23, the signal for storing upper drawknot node PU, and signal in upper drawknot node PU, will connect
The clock signal clk output for receiving；
Drop-down module 24, for when it is high level to gate end signal OUTN+1, by upper drawknot node PU, lower drawknot node
The output end OUTN of control node PDC and shift register is set to low level；And lower drawknot node PD current potential be high level
When, the output end OUTN of upper drawknot node PU and shift register is set to low level；
Pull-down node control module 25, the signal of the control node PDC for storing lower drawknot node；And in lower drawknot node
When control node PDC is high level, lower drawknot node PD is set to low level；And lower drawknot node control node PDC be low electricity
Usually, lower drawknot node PD is set to high level.
When shift register provided in an embodiment of the present invention is used in display device, N grades of shift register is received
Gating trigger signal be the N-1 grades of signal of shift register output, the gating that N grades of shift register is received terminates letter
Number it is the signal of N+1 grades of shift register output；The gating trigger signal that first order shift register is received can be first
Beginning trigger signal；The gating end signal that afterbody shift register is received can be the shift register output of redundancy
Signal, the shift register of the redundancy is not connected to the gate line in display device, and the shift register of the redundancy is only responsible for most
Rear stage shift register output gates end signal.
When shift register provided in an embodiment of the present invention is used in display device, adjacent two-stage shift register connects
The clock signal for receiving can be complementary.That is, the one-level shift register in adjacent two-stage shift register connects
When the clock signal for receiving is high level, the clock that another grade of shift register in adjacent two-stage shift register is received
Signal is low level；When the clock signal that the one-level shift register in adjacent two-stage shift register is received is low level
When, the clock signal that another grade of shift register in adjacent two-stage shift register is received is high level.
Alternatively, shift register provided in an embodiment of the present invention is as shown in figure 3, drop-down module includes the first drop-down unit
241 and second drop-down unit 242；
First drop-down unit 241, for when it is high level to gate end signal OUTN+1, by upper drawknot node PU and drop-down
The control node PDC of node is set to low level；And when the current potential of lower drawknot node PD is high level, upper drawknot node PU is set to
Low level；
Second drop-down unit 242, for when it is high level to gate end signal OUTN+1, by the output of shift register
End OUTN is set to low level；And when the current potential of lower drawknot node PD is high level, the output end OUTN of shift register is set to
Low level.
Further, shift register provided in an embodiment of the present invention is as shown in figure 4, wherein, the first pull-up module includes
The first transistor T1；The grid of the first transistor T1 is extremely connected with the first of the first transistor T1, receives gating trigger signal
OUTN-1, the upper drawknot node PU of the second pole connection of the first transistor.
As shown in figure 4, the second pull-up module in shift register provided in an embodiment of the present invention includes transistor seconds
T2；The grid of transistor seconds T2 is extremely connected with the first of transistor seconds T2, reception gating trigger signal OUTN-1, second
The control node PDC of the lower drawknot node of the second pole connection of transistor T2.
As shown in figure 4, transport module in shift register provided in an embodiment of the present invention include third transistor T3 and
First electric capacity C1；First pole of third transistor T3 receives clock signal clk, the upper drawknot node of grid connection of third transistor T3
Second pole of PU, third transistor T3 connects the output end OUTN of shifting deposit unit；First electric capacity C1 is connected to the 3rd crystal
Between the grid of pipe T3 and second pole of third transistor T3.
As shown in figure 4, the first drop-down unit in shift register provided in an embodiment of the present invention includes the 4th transistor
T4, the 5th transistor T5 and the 6th transistor T6；The upper drawknot node PU, the 4th transistor T4 of first pole connection of the 4th transistor T4
Grid receive second pole of gating end signal OUTN+1, the 4th transistor T4 and receive low level signal VSS；5th transistor
Drawknot node PD, the second of the 5th transistor T5 under the grid connection of the upper drawknot node PU, the 5th transistor T5 of the first pole connection of T5
Pole receives low level signal VSS；The control node PDC of the lower drawknot node of the first pole connection of the 6th transistor T6, the 6th transistor
The second pole that the grid of T6 receives gating end signal OUTN+1, the 6th transistor T6 receives low level signal VSS.
As shown in figure 4, the second drop-down unit in shift register provided in an embodiment of the present invention includes the 7th transistor
T7 and the 8th transistor T8；First pole of the 7th transistor T7 connects the output end OUTN, the 7th transistor T7 of shift register
Grid receive second pole of gating end signal OUTN+1, the 7th transistor T7 and receive low level signal VSS；8th transistor
First pole of T8 connects the output end OUTN of shift register, the lower drawknot node PD of grid connection of the 8th transistor T8, and the 8th is brilliant
Second pole of body pipe T8 receives low level signal VSS.
As shown in figure 4, the lower drawknot node control module in shift register provided in an embodiment of the present invention includes that the 9th is brilliant
Body pipe T9 and the tenth transistor T10；The control node PDC of the lower drawknot node of grid connection of the 9th transistor T9, the 9th transistor
Second pole of the lower drawknot node PD, the 9th transistor T9 of the first pole connection of T9 receives low level signal VSS；Tenth transistor T10
The first pole be connected with the grid of the tenth transistor T10, the second pole for receiving high level signal VDD, the tenth transistor T10 connects
Meet lower drawknot node PD；Wherein, the size of the tenth transistor T10 is less than the size of the 9th transistor T9, in general the 9th crystal
The size of pipe T9 is at least five times of the size of the tenth transistor T10, it is preferable that the size of the 9th transistor T9 and the tenth crystal
The ratio between size of pipe T10 is 6：1, or the ratio between the size of size and the tenth transistor T10 of the 9th transistor T9 is 7：1, or
The ratio between the size of the transistor T9 of person the 9th and the size of the tenth transistor T10 are 8：1, so, in the 9th transistor T9 and the tenth
When transistor T10 is simultaneously turned on, the point position of lower drawknot node PD can be just low level.
In the shift register shown in Fig. 1, because clock signal clk is that low and high level constantly switches, therefore, crystal
Pipe M5 can continuous discharge and recharge, this can cause the increase of the power consumption of shift register；And in the shift register shown in Fig. 4, by
In high level signal VDD be direct current, therefore, the tenth transistor T10 is constantly on, will not repeated charge, this can reduce shifting
The power consumption of bit register.
Further, shift register provided in an embodiment of the present invention is as shown in figure 5, lower drawknot node control module also includes
11st transistor T11；First pole of the 11st transistor T11 receives high level signal VDD, the grid of the 11st transistor T11
Pole receives the lower drawknot node PD of the second pole connection of gating end signal OUTN+1, the 11st transistor T11.
After gating end signal OUTN+1 is changed into high level from low level, due to the in the shift register shown in Fig. 5
Ten transistor T10 and the 11st transistor T11 are both turned on, the 9th transistor T9 shut-offs, the current potential rising of lower drawknot node PD points
Speed is higher than the rate of climb of the current potential of lower drawknot node PD in the shifting deposit unit shown in Fig. 4, because, in Fig. 4 institutes
The shift register for showing, when it is high level to gate end signal OUTN+1, the 9th transistor T9 shut-offs, only the tenth transistor
T10 is turned on.
Further, shift register provided in an embodiment of the present invention is as shown in fig. 6, lower drawknot node control module also includes
Second electric capacity C2；Second electric capacity C2 is connected between the grid of the 9th transistor T9 and upper drawknot node PU.
So, upper drawknot node PU current potential occur bootstrapping (after being changed into high level from ground level in clock signal clk,
Due to the coupling of the first electric capacity C1, the current potential of upper drawknot node PU is further raised) after, the control node PDC of lower drawknot node
Current potential also due to the coupling of the second electric capacity C2 and further raise, so that it is guaranteed that the 9th transistor T9 turn on, and then
Ensure that lower drawknot node PD is low level.
It should be noted that for the transistor of field of liquid crystal display, drain electrode and source electrode are not distinguished clearly, because
The first of the transistor being previously mentioned in this embodiment of the present invention extremely can be the source electrode of transistor, or the leakage of transistor
Pole, the second of transistor extremely can be the drain electrode of transistor, or the source electrode of transistor.When being carried in the embodiment of the present invention
During the source electrode of the extremely transistor of the first of the transistor for arriving, the second extremely crystal of the transistor being previously mentioned in the embodiment of the present invention
The drain electrode of pipe；When the first extremely drain electrode of transistor of the transistor being previously mentioned in the embodiment of the present invention, the embodiment of the present invention
In the source electrode of the second of transistor the extremely transistor that is previously mentioned.
In order to further illustrate shift register provided in an embodiment of the present invention, said with reference to the timing diagram shown in Fig. 7
Bright its operation principle.
As shown in fig. 7, the work schedule of shift register provided in an embodiment of the present invention can be divided into four-stage.Its
In, clock signal clk B and clock signal clk are two clock signals of complementation.
1st stage：Gating trigger signal OUTN-1 is high level, and gating end signal OUTN+1 is low level, clock letter
Number CLK is low level, therefore, the first transistor T1, transistor seconds T2 are both turned on；The first transistor T1 is turned on and is caused the first electricity
Hold C1 to charge, so that the current potential of upper drawknot node PU is pulled to high potential, third transistor T3 is opened, now due to clock signal
CLK is low level, therefore, the output end OUTN of shift register is low level；Transistor seconds T2 is turned on, in Fig. 4, Fig. 5 or
In shift register shown in Fig. 6, the grid source electrode parasitic capacitance and grid drain parasitic capacitance of the 9th transistor T9 charge, and the 9th is brilliant
The current potential of the grid of body pipe T9 is pulled to high potential (in the shift register shown in Fig. 6, the second electric capacity C2 also charges), i.e., under
To high level, the 9th transistor T9 is turned on the potential rise of the control node PDC of drawknot node, because the size of the 9th transistor T9 is big
In the size of the tenth transistor T10, therefore, the current potential of lower drawknot node PD is low level.
2nd stage：Gating trigger signal OUTN-1 is low level, and gating end signal OUTN+1 is low level, clock letter
Number CLK is high level, therefore, the first transistor T1, transistor seconds T2 are turned off；Due to the memory action of the first electric capacity C1,
Therefore, upper drawknot node is still high level, and third transistor T3 is still opened, now because clock signal clk is high level, because
This, the output end OUTN of shift register is high level, due to the coupling of the first electric capacity C1, therefore, upper drawknot node PU's
Current potential is further raised；Although transistor seconds T2 is turned off, due in the shift register shown in Fig. 4, Fig. 5 or Fig. 6, the 9th
The grid source electrode parasitic capacitance of transistor T9 and the memory action of grid drain parasitic capacitance, the current potential of the grid of the 9th transistor T9 according to
So for high potential, (in the shift register shown in Fig. 6, the second electric capacity C2 can also store the electricity of the grid of the 9th transistor T9
Position), therefore, the current potential of the control node PDC of lower drawknot node is still high level, and the 9th transistor T9 is still turned on, due to the
Size of the size of nine transistor T9 more than the tenth transistor T10, therefore, the current potential of lower drawknot node PD remains as low level.
3rd stage：Gating trigger signal OUTN-1 is low level, and gating end signal OUTN+1 is high level, clock letter
Number CLK is low level, therefore, the 4th transistor T4, the 6th transistor T6 and the 7th transistor T7 are both turned on；Due to the 4th crystal
Pipe T4 is turned on, therefore, the first electric capacity C1 electric discharges, the current potential of upper drawknot node PU is down to low level, third transistor T3 shut-offs；Due to
7th transistor T7 is turned on, therefore, the output end OUTN of shift register is low level；Because the 6th transistor T6 is turned on, because
This, the node PDC that controls of lower drawknot node is low level, and the 9th transistor T9 is turned off, because the tenth transistor T10 is constantly on,
Therefore, lower drawknot node PD is high level；In Fig. 5 or Fig. 6, because gating end signal OUTN+1 is high level, therefore, the tenth
One transistor T11 is turned on, and this can cause that the current potential of lower drawknot node PD is raised rapidly.
4th stage：Gating trigger signal OUTN-1 is low level, and gating end signal OUTN+1 is low level, clock letter
Number CLK is low level, but because the tenth transistor T10 conductings, and the 9th transistor T9 are turned off, therefore, lower drawknot node PD is
High level, the 5th transistor T5 and the 8th transistor T8 are both turned on, so that the output of upper drawknot node PU and shift register
End OUTN is low level.
Afterwards, shift register always worked at for the 4th stage, until shift register provided in an embodiment of the present invention is received
Start to re-execute for the 1st stage again to gating when trigger signal OUTN-1 is high level.3rd stage and the 4th stage are the present invention
The inoperative period of the shift register that embodiment is provided, the 1st stage and the 2nd stage are that displacement provided in an embodiment of the present invention is posted
The working hour of storage.
Display device provided in an embodiment of the present invention includes shift register provided in an embodiment of the present invention.
It will be appreciated by those skilled in the art that accompanying drawing is a schematic diagram for preferred embodiment, module or stream in accompanying drawing
Journey is not necessarily implemented necessary to the present invention.
It will be appreciated by those skilled in the art that the module in device in embodiment can be divided according to embodiment description
It is distributed in the device of embodiment, it is also possible to carry out respective change and be disposed other than in one or more devices of the present embodiment.On
Stating the module of embodiment can merge into a module, it is also possible to be further split into multiple submodule.
The embodiments of the present invention are for illustration only, and the quality of embodiment is not represented.
Obviously, those skilled in the art can carry out various changes and modification without deviating from essence of the invention to the present invention
God and scope.So, if these modifications of the invention and modification belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising these changes and modification.
Claims (11)
1. a kind of shift register, it is characterised in that including the first pull-up module, the second pull-up module, transport module, lower drawing-die
Block and lower drawknot node control module；The tie point that the first pull-up module, the transport module are connected with drop-down module is upper
Drawknot node；The tie point that the drop-down module is connected with the lower drawknot node control module is lower drawknot node；Second pull-up
The tie point that module, the drop-down module are connected with the lower drawknot node control module is the control node of lower drawknot node；
The first pull-up module, for when it is high level to gate trigger signal, upper drawknot node being set into high level；
The second pull-up module, for when the gating trigger signal is high level, the control node of lower drawknot node being put
It is high level；
The transport module, the signal for storing the upper drawknot node, and on described under the control of the signal of drawknot node, will
The clock signal output for receiving；
The drop-down module, for when it is high level to gate end signal, by the upper drawknot node, the control of the lower drawknot node
The output end of node processed and the shift register is set to low level；And when the current potential of the lower drawknot node is high level,
The output end of the upper drawknot node and the shift register is set to low level；
The lower drawknot node control module, the signal of the control node for storing the lower drawknot node；And in the lower drawknot
When the control node of point is high level, the lower drawknot node is set to low level；And the control node in the lower drawknot node is
During low level, the lower drawknot node is set to high level.
2. shift register as claimed in claim 1, it is characterised in that the drop-down module includes the first drop-down unit and the
Two drop-down units；
First drop-down unit, for when it is high level to gate end signal, by the upper drawknot node and the lower drawknot
The control node of point is set to low level；And when the current potential of the lower drawknot node is high level, the upper drawknot node is set to
Low level；
Second drop-down unit, for when the gating end signal is high level, by the output of the shift register
End is set to low level；And when the current potential of the lower drawknot node is high level, the output end of the shift register is set to low
Level.
3. shift register as claimed in claim 1, it is characterised in that the first pull-up module includes the first transistor；
The grid of the first transistor is extremely connected with the first of the first transistor, receives the gating trigger signal,
The upper drawknot node of second pole connection of the first transistor.
4. shift register as claimed in claim 1, it is characterised in that the second pull-up module includes transistor seconds；
The grid of the transistor seconds is extremely connected with the first of the transistor seconds, receives the gating trigger signal,
Second pole of the transistor seconds connects the control node of the lower drawknot node.
5. shift register as claimed in claim 1, it is characterised in that the transport module includes third transistor and first
Electric capacity；
First pole of the third transistor receives the clock signal, and the grid of the third transistor connects the upper drawknot
Point, the second pole of the third transistor connects the output end of the shift register；
First capacitance connection is between the grid of the third transistor and the second pole of the third transistor.
6. shift register as claimed in claim 2, it is characterised in that first drop-down unit include the 4th transistor,
5th transistor and the 6th transistor；
First pole of the 4th transistor connects the upper drawknot node, and the grid of the 4th transistor receives the gating knot
Beam signal, the second pole of the 4th transistor receives low level signal；
First pole of the 5th transistor connects the upper drawknot node, and the grid of the 5th transistor connects the lower drawknot
Point, the second pole of the 5th transistor receives low level signal；
First pole of the 6th transistor connects the control node of the lower drawknot node, and the grid of the 6th transistor is received
The gating end signal, the second pole of the 6th transistor receives low level signal.
7. shift register as claimed in claim 2, it is characterised in that second drop-down unit include the 7th transistor and
8th transistor；
First pole of the 7th transistor connects the output end of the shift register, and the grid of the 7th transistor is received
The gating end signal, the second pole of the 7th transistor receives low level signal；
First pole of the 8th transistor connects the output end of the shift register, the grid connection of the 8th transistor
The lower drawknot node, the second pole of the 8th transistor receives low level signal.
8. shift register as claimed in claim 1, it is characterised in that the lower drawknot node control module includes the 9th crystal
Pipe and the tenth transistor；
The grid of the 9th transistor connects the control node of the lower drawknot node, the first pole connection of the 9th transistor
The lower drawknot node, the second pole of the 9th transistor receives low level signal；
First pole of the tenth transistor is connected with the grid of the tenth transistor, receives high level signal, described
Second pole of ten transistors connects the lower drawknot node；
Wherein, size of the size of the tenth transistor less than the 9th transistor.
9. shift register as claimed in claim 8, it is characterised in that the lower drawknot node control module also includes the 11st
Transistor；
First pole of the 11st transistor receives high level signal, and the grid of the 11st transistor receives the gating
End signal, the second pole of the 11st transistor connects the lower drawknot node.
10. shift register as claimed in claim 8, it is characterised in that the lower drawknot node control module also includes second
Electric capacity；
Second capacitance connection the 9th transistor grid and it is described between drawknot node.
11. a kind of display devices, it is characterised in that including the shift register as described in claim 1~10 is any.
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| CN105957556A (en) * | 2016-05-11 | 2016-09-21 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit, display apparatus, and driving method of shift register unit |
| CN106504720B (en) * | 2017-01-04 | 2022-08-23 | 合肥鑫晟光电科技有限公司 | Shifting register unit and driving method thereof, grid driving device and display device |
| CN108648714B (en) | 2018-07-11 | 2020-06-26 | 京东方科技集团股份有限公司 | Shifting register unit, driving method, grid driving circuit and display device |
| CN111243489B (en) * | 2020-03-24 | 2022-11-01 | 合肥鑫晟光电科技有限公司 | Shifting register, driving method thereof and grid driving circuit |
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| KR102040648B1 (en) * | 2013-06-21 | 2019-11-05 | 엘지디스플레이 주식회사 | Shift register and display device using the same |
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