CN104731704A - Method for testing NAND (NOT-AND) FLASH management software - Google Patents
Method for testing NAND (NOT-AND) FLASH management software Download PDFInfo
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- CN104731704A CN104731704A CN201310721564.XA CN201310721564A CN104731704A CN 104731704 A CN104731704 A CN 104731704A CN 201310721564 A CN201310721564 A CN 201310721564A CN 104731704 A CN104731704 A CN 104731704A
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Abstract
The invention relates to a method for testing NAND (NOT-AND) FLASH management software. The method has the advantages that data in NAND FLASH memories are logically read, data are physically directly written into the NAND FLASH memories, data transit mechanisms of the NAND FLASH management software can be quickly triggered, accordingly, the product testing time can be shortened, and the testing expenditure can be saved; the method can be applied to different types of NAND FLASH management software of different operating systems.
Description
Technical field
The present invention relates to method of testing, particularly a kind of method of testing of NAND FLASH management software.
Background technology
NAND FLASH internal memory is the one in flash internal memory, the non-linear macroelement pattern of its inner employing, and the realization for solid-state large-capacity internal memory provides cheap effective solution.It is larger that NAND-FLASH storer has capacity, the advantages such as rewriting speed is fast, be applicable to the storage of mass data, thus in the industry cycle obtain and apply more and more widely, as embedded product comprises the USB flash disk etc. of digital camera, MP3 walkman memory card, compact.But the situation of bit reversal easily appears in NAND FLASH internal memory, the reliability that reliable NAND FLASH management software just can ensure NAND FLASH internal memory must be equipped with.
The principle of existing NAND FLASH management software is that trigger data moves mechanism when NAND FLASH flip bit reaches the critical value of design, by the data-moving through error correction to another address, and by logical address that the physical address map of NAND FLASH uses to operating system.Rely on this cover management software NAND FLASH internal memory just can use in some occasions higher to safety requirements, such as industrial machine, automobile etc.Therefore, the reliability of NAND FLASH management software that uses of product and coverage just become the key factor concerning life of product and reliability.
In order to test the reliability of NAND FLASH management software, generally write test procedure on the read-write interface that provides at management software, test procedure does repeatedly read-write operation to NAND FLASH internal memory, voltage fluctuation is coordinated to test again, with the situation making NAND FLASH reach bit flipping or damage as early as possible, mechanism is moved, the effect of checking NAND FLASH management software with trigger data.But tested by power down and often need trigger data to move mechanism more than several ten thousand times, need several days consuming time time to several week, efficiency is low, have impact on the time that product is released to a great extent.
Summary of the invention
The object of the present invention is to provide a kind of method of testing that can complete the NAND FLASH management software of the test process of NAND FLASH management software at short notice.
A method of testing for NAND FLASH management software, it is for testing the NAND FLASH management software run on a processor.NAND FLASH internal memory is connected on the processor by a NAND FLASH controller.Described method of testing comprises four steps.Wherein step one, reads the data field of the block of specifying logical address and backup area data as the first data and the second data by described NAND FLASH management software from described NAND FLASH internal memory, and obtains the physical address of the first data simultaneously.Step 2, closes the ECC verifying function of described NAND FLASH controller, walks around described NAND FLASH management software, wipes the data on described NAND FLASH memory block according to described physical address direct physical.Step 3, walk around described NAND FLASH management software, directly in the data field of described physical address write the 3rd data, in described second data of backup area write, wherein the quantity of the 3rd data difference data bit compared with the first data is greater than the ECC critical value of described NAND FLASH management software and is less than the maximum error correction figure place of ECC.Step 4, open the ECC verifying function of described NAND FLASH controller, the double data being read the described appointment logical address of NAND FLASH internal memory by described NAND FLASH management software, obtain when second time reads the physical address that now described appointment logical address is corresponding, and the result that root reads exports the result.
Preferably, described processor is also connected with an external computer equipment by serial ports, to be described processors perform when the request of data of appointment logical address receiving the reading described NAND FLASH internal memory that described external computer equipment sends in the action of reading the first and second data in described step one, described processor sends to described external computer equipment to preserve after reading described first and second data, obtain the physical address of the first data simultaneously and send to described external computer equipment.
Preferably, after described external computer equipment receives described first and second data, according to described first data genaration the 3rd data, then control described processor and perform described step 2 to step 4.
Preferably, in step 4, if first time in twi-read, the data that read were the described 3rd and second data, the data that second time reads are first and second data, and the physical address that second time obtains is different from the physical address that step one obtains, then judge that described NAND FLASH management software is correct, described external computer equipment exports the information be verified by display device; If the data that second time reads still be the described 3rd and second data, then judge that described NAND FLASH management software is made mistakes, described external computer equipment is by the information of display device output authentication failed.
The method of testing of NAND FLASH management software of the present invention adopts logic to read by adopting during the data reading NAND FLASH internal memory, the data-moving mechanism of the mode rapid triggering NAND FLASH management software adopting physics to write direct when NAND FLASH internal memory write data, the test duration of product can be reduced, save test funds.This method of testing can be applicable to the different NAND FLASH management software of different operating system.
Accompanying drawing explanation
Fig. 1 is the system architecture diagram of the method for testing application of the NAND FLASH management software of an embodiment.
Embodiment
Below in conjunction with specific embodiment and accompanying drawing, the method for testing to NAND FLASH management software of the present invention is described in further detail.
In one embodiment, the method of testing of NAND FLASH management software of the present invention is applied in system as shown in Figure 1, and this system comprises processor, connect NAND FLASH controller (hereinafter referred to as controller) on a processor and connect NAND FLASH internal memory (hereinafter referred to as internal memory) on a processor by controller.In addition, processor is also connected with external computer equipment by serial communication interface.Controller is the bridge that processor connects internal memory, and primary responsibility controls read-write and ECC (Error Correcting Code, bug check and correction code) verification operation.
In the present embodiment, the arm processor that processor uses for electric apparatus mounted on vehicle, it runs WinCE operating system, and in-built NAND FLASH management software (hereinafter referred to as management software) and NAND FLASH testing software (hereinafter referred to as testing software).External computer equipment runs and has serial ports testing software, be mainly used in control processor and perform testing software.
NAND FLASH management software is responsible for checking and is processed ECC check results; the bad block of management NAND FLASH internal memory; it is by arranging each sector(sector) the data(data in region) district allows to make mistakes the critical value of figure place; move the sector data that figure place of makeing mistakes reaches critical value in time, guarantee protected data before there is the mistake that ECC can not correct.NAND FLASH management software exposes read-write to WinCE operating system and obtains the interface of NAND FLASH data in EMS memory.And be the logical address that operating system uses by the physical address map of NAND FLASH internal memory.
NAND FLASH testing software is responsible for realizing internally depositing into the read operation of row logic by management software, is also responsible for walking around management software and directly internally deposits into row physical write operation, is also responsible for being communicated with external computer equipment by serial communication interface.Wherein logic read operation needs the NAND FLASH being called controller by operating system to read interface.
Serial ports testing software is responsible for exporting test interface to user, and this test interface includes but not limited to that test process and result are shown, the setting frame etc. of parameter.User by this test interface the logic of carrying out during test read and physical write number of operations and the operation address of internal memory is set and is revised.
In one embodiment, the method for testing of NAND FLASH management software of the present invention mainly comprises the following steps:
Step 1: sent the instruction starting test by external computer equipment to processor, and the request sending that reading NAND FLASH specifies block (block) data of logical address (logic address1).
Step 2: processor by management software from NAND FLASH read specify logical address logic address1 data (data) district and backup (spare) district data as the first data and the second data, send to external computer equipment to preserve the first and second data, obtain the physical address (Physical address1) of the first data simultaneously and send to external computer equipment to preserve (because the second data (spare) can read by the first data address).
Step 3: send reading command to processor by external computer equipment, processor revises the first data to generate the 3rd data, make the quantity of the 3rd data difference data bit compared with the first data be greater than the ECC critical value of management software, and figure place of makeing mistakes need be less than the maximum error correction figure place of ECC.
Step 4: external computer equipment sends the ECC verifying function of instructs control processor closing controller after execution of step 3, walk around management software, according to the data on physical address (Physical address1) the direct physical erasing NAND FLASH block that step 2 obtains.
Step 5: external computer equipment sends instruction and walks around management software to processor, directly in Physical address1 data field write the 3rd data, re-writes the second data at backup area.
Step 6: external computer equipment sends instructions to the ECC verifying function that controller opened by processor, and the double data being read logic address1 by management software, and the data (in this called after the 4th data) that second time reads are sent to external computer equipment by serial ports.Obtain physical address Physical address2 corresponding to now logic address1 when second time read data simultaneously.
Step 7: according to the data received, external computer equipment judges that whether management software is qualified, and generate the result and export to user by test interface.Concrete, in step 6, the data that read should be the 3rd and second data first time, also namely by the data be physically written in Physical address1 block, and in this reading process, management software finds that the figure place of makeing mistakes of the data preset in block has exceeded the figure place of makeing mistakes of every sector permission, therefore other block(Physical address2 is moved by after data (comprising data district and the spare district) error correction in Physical address1 block, different from Physical address1) on, and the data physical address Physical address2 after moving is mapped to logic address1.Then second time is data of Physical address2 in the data that logic address1 reads.Therefore, if the 4th data are identical with the first and second data, and Physical address1 is different from Physical address2 then judges that management software is correct.So, trigger data can move mechanism through a flow process, the effect of checking nand flash management software, reduces the test duration of product, saves test funds.This method of testing can be applicable to the different NAND FLASH management software of different operating system, only needs to change hardware-related part, such as, with nand flash controller register relevant portion.
In other embodiments, can multiple exercise step 1 to step 7, with checking of modifying to the data of blcok different in internal memory, guarantee verify accuracy.
In other embodiments, external computer equipment can not be relied on, all testing procedures of processor complete independently.Need in test process block data pre-set by serial ports.
Although the description of this invention carries out in conjunction with above specific embodiment, those skilled in the art can carry out many replacements, modifications and variations, be apparent according to above-mentioned content.Therefore, all like this substitute, improve and change be all included in the spirit and scope of attached claim.
Claims (4)
1., for the method for testing to the NAND FLASH management software run on a processor, wherein a NAND FLASH internal memory is connected on the processor by a NAND FLASH controller; Described method of testing comprises:
Step one, reads the data field of the block of specifying logical address and backup area data as the first data and the second data by described NAND FLASH management software from described NAND FLASH internal memory, and obtains the physical address of the first data simultaneously;
Step 2, closes the ECC verifying function of described NAND FLASH controller, walks around described NAND FLASH management software, wipes the data on described NAND FLASH memory block according to described physical address direct physical;
Step 3, walk around described NAND FLASH management software, directly in the data field of described physical address write the 3rd data, in described second data of backup area write, wherein the quantity of the 3rd data difference data bit compared with the first data is greater than the ECC critical value of described NAND FLASH management software and is less than the maximum error correction figure place of ECC; And
Step 4, open the ECC verifying function of described NAND FLASH controller, the double data being read the described appointment logical address of NAND FLASH internal memory by described NAND FLASH management software, obtain when second time reads the physical address that now described appointment logical address is corresponding, and the result that root reads exports the result.
2. the method for testing of NAND FLASH management software according to claim 1, it is characterized in that, described processor is also connected with an external computer equipment by serial ports, to be described processors perform when the request of data of appointment logical address receiving the reading described NAND FLASH internal memory that described external computer equipment sends in the action of reading the first and second data in described step one, described processor sends to described external computer equipment to preserve after reading described first and second data, obtain the physical address of the first data simultaneously and send to described external computer equipment.
3. the method for testing of NAND FLASH management software according to claim 2, it is characterized in that, after described external computer equipment receives described first and second data, according to described first data genaration the 3rd data, then control described processor and perform described step 2 to step 4.
4. the method for testing of NAND FLASH management software according to claim 3, it is characterized in that, in step 4, if first time in twi-read, the data that read were the described 3rd and second data, the data that second time reads are first and second data, and the physical address that second time obtains is different from the physical address that step one obtains, then judge that described NAND FLASH management software is correct, described external computer equipment exports the information be verified by display device; If the data that second time reads still be the described 3rd and second data, then judge that described NAND FLASH management software is made mistakes, described external computer equipment is by the information of display device output authentication failed.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106933696A (en) * | 2015-12-31 | 2017-07-07 | 北京国睿中数科技股份有限公司 | ECC function verification methods |
| CN107808686A (en) * | 2016-09-09 | 2018-03-16 | 北京忆恒创源科技有限公司 | Read error method of testing and device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040054637A1 (en) * | 2000-11-24 | 2004-03-18 | Fumio Negoro | Software synchronous specifying method, validating method, verifying method and testing method |
| CN102201267A (en) * | 2010-03-26 | 2011-09-28 | 上海摩波彼克半导体有限公司 | Platform system for realizing circuit verification of Nandflash flash memory controller based on FPGA (Field Programmable Gate Array) and method thereof |
| CN102279776A (en) * | 2010-06-11 | 2011-12-14 | 无锡中星微电子有限公司 | Error checking and correcting ability testing method and device |
| CN102646453A (en) * | 2011-02-18 | 2012-08-22 | 安凯(广州)微电子技术有限公司 | Method and system for testing error correcting code module in NandFlash controller |
-
2013
- 2013-12-24 CN CN201310721564.XA patent/CN104731704B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040054637A1 (en) * | 2000-11-24 | 2004-03-18 | Fumio Negoro | Software synchronous specifying method, validating method, verifying method and testing method |
| CN102201267A (en) * | 2010-03-26 | 2011-09-28 | 上海摩波彼克半导体有限公司 | Platform system for realizing circuit verification of Nandflash flash memory controller based on FPGA (Field Programmable Gate Array) and method thereof |
| CN102279776A (en) * | 2010-06-11 | 2011-12-14 | 无锡中星微电子有限公司 | Error checking and correcting ability testing method and device |
| CN102646453A (en) * | 2011-02-18 | 2012-08-22 | 安凯(广州)微电子技术有限公司 | Method and system for testing error correcting code module in NandFlash controller |
Non-Patent Citations (1)
| Title |
|---|
| 张崙等: "《32位嵌入式***硬件设计与调试》", 31 May 2005 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106933696A (en) * | 2015-12-31 | 2017-07-07 | 北京国睿中数科技股份有限公司 | ECC function verification methods |
| CN107808686A (en) * | 2016-09-09 | 2018-03-16 | 北京忆恒创源科技有限公司 | Read error method of testing and device |
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