CN104718626A - 具有减小的栅极到源极与栅极到漏极重叠电容的金属栅极mos晶体管 - Google Patents

具有减小的栅极到源极与栅极到漏极重叠电容的金属栅极mos晶体管 Download PDF

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CN104718626A
CN104718626A CN201380053370.5A CN201380053370A CN104718626A CN 104718626 A CN104718626 A CN 104718626A CN 201380053370 A CN201380053370 A CN 201380053370A CN 104718626 A CN104718626 A CN 104718626A
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马诺耶·梅赫罗特拉
新美广明
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Abstract

通过沿着已被形成为位于较远离源极(220)及漏极(222)处的侧壁结构(236)的内侧形成高k栅极电介质(226)来减小具有金属栅极(230)及所述高k栅极电介质(226)的MOS晶体管(200)的栅极到源极与栅极到漏极重叠电容。

Description

具有减小的栅极到源极与栅极到漏极重叠电容的金属栅极MOS晶体管
技术领域
本发明涉及MOS晶体管，且更特定来说，涉及金属栅极MOS晶体管及形成此类晶体管的方法。
背景技术
金属氧化物半导体(MOS)晶体管是众所周知的半导体装置，其可实施为n沟道(NMOS)装置或p沟道(PMOS)装置。MOS晶体管具有由沟道分离的间隔开的源极区及漏极区以及位于所述沟道上方且通过栅极电介质层与所述沟道绝缘的栅极。金属栅极MOS晶体管是一种利用金属栅极及高k栅极电介质层的类型的MOS晶体管。
图1图解说明现有技术金属栅极MOS晶体管100。MOS晶体管100包含半导体本体110，半导体本体110具有单晶硅衬底区112及接触衬底区112的沟槽隔离结构114。另外，半导体本体110包含各自接触衬底区112的源极120及漏极122。源极120及漏极122各自具有与衬底区112的导电性类型相反的导电性类型。源极120包含经轻掺杂区120L及经重掺杂区120H。类似地，漏极122包含经轻掺杂区122L及经重掺杂区122H。此外，衬底区112具有位于源极120与漏极122之间的沟道区124。
如图1中所进一步展示，MOS晶体管100包含接触沟道区124且位于沟道区124上方的高k栅极电介质结构126及接触栅极电介质结构126且位于沟道区124上方的金属栅极130。MOS晶体管100还包含接触栅极电介质结构126且横向环绕栅极130的侧壁间隔件132。
MOS晶体管100另外包含接触侧壁间隔件132且位于源极120及漏极122上方的不导电互连电介质结构138。电介质结构138可用蚀刻止挡层140及接触蚀刻止挡层140且位于蚀刻止挡层140上方的电介质层142来实施。
晶体管的阈值电压是在沟道区的顶表面处形成反转层所需的栅极电压，其足以允许电流从源极区流动到漏极区。在NMOS晶体管的情况中，n型掺杂剂原子形成反转层，而在PMOS晶体管的情况中，p型掺杂剂原子形成反转层。
在操作中，关于NMOS晶体管，当存在正漏极到源极电压VDS且栅极到源极电压VGS比阈值电压更正时，NMOS晶体管接通且电子从源极区流动到漏极区。当栅极到源极电压VGS比阈值电压更负时，MOS晶体管关断且无电子(除极小泄漏电流之外)从源极区流动到漏极区。
关于PMOS晶体管，当存在负漏极到源极电压VDS且栅极到源极电压VGS比阈值电压更负时，PMOS晶体管接通且空穴从源极区流动到漏极区。当栅极到源极电压VGS比阈值电压更正时，PMOS晶体管关断且无空穴(除极小泄漏电流之外)从源极区流动到漏极区。
MOS晶体管100的问题之一是，高k栅极电介质结构126实质上增加了栅极到源极与栅极到漏极重叠电容。因此，需要一种减小与高k电介质结构相关联的栅极到源极与栅极到漏极重叠电容的金属栅极MOS晶体管。
发明内容
本发明提供一种减小栅极到源极与栅极到漏极重叠电容的金属栅极MOS晶体管及形成所述晶体管的方法。
在所描述的实施例中，一种半导体结构包含具有一导电性类型的半导体区。所述半导体结构还包含各自接触所述半导体区的源极及漏极。间隔开的源极及漏极各自具有与所述半导体区的导电性类型相反的导电性类型。所述半导体结构进一步包含所述半导体区的沟道区，所述沟道区位于所述源极与所述漏极之间。另外，所述半导体结构包含接触所述沟道区且位于所述沟道区上方的栅极电介质及接触所述栅极电介质且位于所述栅极电介质上方的金属栅极。所述金属栅极具有下部宽度及大于所述下部宽度的上部宽度。
替代地，所述半导体结构包含具有一导电性类型的半导体区。所述半导体结构还包含各自接触所述半导体区的源极及漏极。间隔开的源极及漏极各自具有与所述半导体区的导电性类型相反的导电性类型。所述半导体结构进一步包含所述半导体区的沟道区，所述沟道区位于所述源极与所述漏极之间。另外，所述半导体结构包含接触所述沟道区且位于所述沟道区上方的栅极电介质及接触所述栅极电介质且位于所述栅极电介质上方的金属栅极。此外，所述半导体结构包含接触所述栅极电介质且横向环绕所述栅极电介质及所述金属栅极两者的不导电侧壁间隔件。所述不导电侧壁间隔件的一部分垂直位于所述半导体区与所述金属栅极正中间。
一种形成半导体结构的方法包含形成接触半导体区的栅极结构。所述栅极结构具有牺牲栅极电介质及牺牲栅极。所述牺牲栅极电介质接触所述半导体区。所述牺牲栅极接触所述牺牲栅极电介质。所述半导体区具有一导电性类型。所述方法还包含蚀刻掉所述牺牲栅极电介质的一部分以形成牺牲电介质结构及腔。所述牺牲电介质结构接触所述牺牲栅极及所述半导体区。所述腔垂直位于所述牺牲栅极的一部分正下方。所述方法进一步包含在已形成所述牺牲电介质结构之后，形成接触所述半导体区的源极及漏极。所述源极及所述漏极各自具有与所述半导体区的所述导电性类型相反的导电性类型。
附图说明
图1是图解说明现有技术金属栅极MOS晶体管100的横截面图。
图2是图解说明根据本发明的原理的金属栅极MOS晶体管200的实例的横截面图。
图3A-3M是图解说明根据本发明的原理形成金属栅极MOS晶体管的方法300的实例的横截面图。
具体实施方式
图2图解说明金属栅极MOS晶体管200的实例，晶体管200通过沿着已被形成为位于较远离源极及漏极处的侧壁结构的内侧形成高k栅极电介质来减小栅极到源极与栅极到漏极重叠电容。
如图2中所展示，MOS晶体管200包含半导体本体210。半导体本体210又包含单晶硅衬底区212及接触衬底区212的沟槽隔离结构214。另外，半导体本体210包含各自接触衬底区212的源极220及漏极222。
间隔开的源极220及漏极222各自具有与衬底区212的导电性类型相反的导电性类型。源极220包含经轻掺杂区220L及经重掺杂区220H。类似地，漏极222包含经轻掺杂区222L及经重掺杂区222H。此外，衬底区212具有位于源极220与漏极222之间的沟道区224。
如图2中所进一步展示，MOS晶体管200还包含接触沟道区224且位于沟道区224上方的高k栅极电介质226。高k栅极电介质结构226可用若干种材料来实施，例如氧化铪及氧化硅铪的顺序层。
MOS晶体管200另外包含接触栅极电介质结构226且位于沟道区224上方的金属栅极230。金属栅极230具有上部宽度W1大于下部宽度W2的T形状。此外，金属栅极230具有顶表面232及接触顶表面232的外表面234。高k栅极电介质结构226接触并覆盖金属栅极230的外表面234的全部。金属栅极230可用若干种材料来实施，例如氮化钛、氮化钽及铝的顺序层。
MOS晶体管200还包含接触高k栅极电介质结构226且横向环绕高k栅极电介质结构226及金属栅极230两者的侧壁间隔件236。此外，侧壁间隔件236的一部分垂直位于金属栅极230的一部分与沟道区224正中间。侧壁间隔件236还可包含彼此接触的若干个个别侧壁间隔件，例如接触氮化物(具有薄氧化物底衬)侧壁间隔件的氧化物侧壁间隔件。侧壁间隔件236可用若干种材料来实施，例如氧化物及氮化物。
MOS晶体管200另外包含接触侧壁间隔件236且位于源极220及漏极222上方的不导电互连电介质结构238。在本实例中，电介质结构238用蚀刻止挡层240及接触蚀刻止挡层240且位于蚀刻止挡层240上方的电介质层242来实施。蚀刻止挡层240可各自用若干种材料来实施，例如氮化硅或氧氮化硅。电介质层242可用若干种材料来实施，例如氧化物。MOS晶体管200以与MOS晶体管100实质上相同的方式操作，只不过MOS晶体管200具有更小的栅极到源极与栅极到漏极重叠电容。
图3A-3M图解说明形成金属栅极MOS晶体管的方法300的实例。方法300利用经部分完成的以常规方式形成的晶体管结构308，晶体管结构308包含半导体本体310。半导体本体310又包含单晶硅衬底区312及接触衬底312的沟槽隔离结构314。
如图3A中所展示，方法300通过形成接触衬底区312且位于衬底区312上方的牺牲栅极电介质层316而开始。在本实例中，使用常规程序将牺牲栅极电介质层316形成为相对厚的，具有(例如)1nm-5nm的厚度。牺牲栅极电介质层316可用若干种牺牲材料来实施，例如氧化物。
在已形成牺牲栅极电介质层316之后，使用常规程序将牺牲栅极层318形成为接触牺牲栅极电介质层316且位于牺牲栅极电介质层316上方。牺牲栅极层318可用若干种牺牲材料来实施，例如多晶硅。
此后，使用常规程序在牺牲栅极层318上形成经图案化掩模320。经图案化掩模可以若干种方式来实施，例如硬掩模或经图案化光致抗蚀剂层。(通常通过沉积氧化物层、随后沉积上覆氮化物层来形成硬掩模。接下来在所述氮化物层上形成经图案化光致抗蚀剂层，且接着蚀刻掉所述氮化物层的经暴露区。在蚀刻之后移除经图案化光致抗蚀剂层以形成硬掩模。)
如图3B中所展示，在已形成经图案化掩模320之后，使用常规程序蚀刻掉牺牲栅极层318及牺牲栅极电介质层316的经暴露区以暴露衬底区312的顶表面且形成牺牲栅极结构321。牺牲栅极结构321又包含接触衬底区312且位于衬底区312上面的牺牲栅极电介质322及接触牺牲栅极电介质322且位于牺牲栅极电介质322上方的牺牲栅极324。在蚀刻之后，以常规方式移除经图案化掩模320。
如图3C中所展示，在已移除经图案化掩模320之后，借助实质上移除比硅更多的电介质322的蚀刻剂来对牺牲栅极电介质322进行湿蚀刻或进行各向同性干蚀刻。所述蚀刻形成接触牺牲栅极324及衬底区312且位于牺牲栅极324与衬底区312之间的牺牲电介质结构326，及垂直位于牺牲栅极324的一部分与衬底区312正中间的腔328。在本实例中，腔328被形成为具有1nm到5nm的深度(水平地进行测量)。
如图3D中所展示，在已形成牺牲电介质结构326之后，使用常规程序在衬底区312、牺牲栅极324及牺牲电介质结构326上保形地形成不导电耐蚀刻层330以给腔328加衬。在本实例中，耐蚀刻层330被形成为具有1nm到5nm的厚度。
耐蚀刻层330可用若干种材料来形成，例如氮化物。可通过使用(例如)以下工艺来形成氮化物层：常规氮化硅化学气相沉积(CVD)或原子层沉积(ALD)工艺(其在氮化物层之前形成薄氧化物底衬)、常规重氮化氧化物生长工艺(例如，在氨中的热氧化物生长)、CVD氮化物与氮化氧化物生长的组合或常规等离子氮化工艺。
举例来说，当牺牲栅极324用多晶硅实施且牺牲电介质结构326用氧化物实施时，可由氮化物形成耐蚀刻层330。当耐蚀刻层330用氮化物来实施时，具有较薄氮化物层会减小电容。
在已形成耐蚀刻层330之后，使用常规步骤在耐蚀刻层330上形成不导电层332以覆盖耐蚀刻层330并填充腔328。不导电层332可用若干种材料来形成，例如经沉积氧化物或在纯一氧化二氮(N2O)、纯一氧化氮(NO)气体或N2O气体与NO气体的组合中生长的氧化物。在本实例中，不导电层332被形成为具有1nm到2nm的厚度。
如图3E中所展示，在已形成不导电层332之后，对耐蚀刻层330及不导电层332进行各向异性蚀刻直到牺牲栅极324的顶表面被暴露为止。所述各向异性蚀刻形成具有不导电耐蚀刻区段336及不导电区段338的侧壁间隔件334。(在耐蚀刻层330厚到足以填充腔328时可省略不导电层332及不导电结构338。)
如图3F中所展示，在已形成侧壁间隔件334之后，以常规方式将掺杂剂植入到衬底区312中以形成间隔开的经轻掺杂区340及342。经轻掺杂区340及342具有与衬底区312的导电性类型相反的导电性类型。
如图3G中所展示，在已形成经轻掺杂区340及342之后，将不导电侧壁间隔件344形成为接触侧壁间隔件334且横向环绕牺牲栅极324。不导电侧壁间隔件344可以若干种方式来形成。举例来说，可在牺牲栅极324及侧壁间隔件334上形成氮化物层，且接着对其进行各向异性蚀刻直到牺牲栅极324的顶表面被暴露以形成侧壁间隔件344。侧壁间隔件334与侧壁间隔件344共同形成侧壁间隔件345。
如图3H中所展示，在已形成侧壁间隔件345之后，以常规方式将掺杂剂植入到衬底区312以及经轻掺杂区340及342中以形成间隔开的经重掺杂区346及348。经重掺杂区346及348各自具有与衬底区312的导电性类型相反的导电性类型。
经轻掺杂区340及经重掺杂区346形成源极350，而经轻掺杂区342及经重掺杂区348形成漏极352。源极区350及漏极区352界定衬底区312的沟道区354，沟道区354位于源极区350与漏极区352之间且分离源极区350与漏极区352。
如图3I中所展示，在已形成源极区350及漏极区352之后，以常规方式将不导电互连电介质层356形成为接触牺牲栅极324、侧壁间隔件345、源极区350及漏极区352且位于这各者上方。在本实例中，通过首先使用常规程序将不导电蚀刻止挡层360沉积为接触牺牲栅极324、侧壁间隔件345、源极区350及漏极区352且位于这各者上方来形成互连电介质层356。
此后，将不导电电介质层362形成为接触蚀刻止挡层360且位于蚀刻止挡层360上方。蚀刻止挡层360可用若干种材料来实施，例如氮化硅或氧氮化硅，而电介质层362可用若干种材料来实施，例如氧化物。
如图3J中所展示，在已形成电介质层356之后，例如借助化学-机械抛光对电介质层356进行平面化，直到牺牲栅极324的顶表面被暴露为止。在本实例中，通过首先对电介质层362进行平面化直到检测到蚀刻止挡层360的顶表面来对电介质层356进行平面化。此后，借助湿/干蚀刻移除蚀刻止挡层360及电介质层362直到牺牲栅极324的顶表面被暴露为止。
所述平面化形成接触侧壁间隔件345且位于源极350及漏极352上方的互连电介质结构364。在本实例中，互连电介质结构364包含接触侧壁间隔件345的蚀刻止挡区段366及接触蚀刻止挡区段366的电介质区段368。(可任选地省略蚀刻止挡层360及蚀刻止挡区段366。)由于所述平面化，牺牲栅极324及互连电介质结构364的顶表面实质上位于同一平面中。
如图3K中所展示，在已暴露牺牲栅极324的顶表面之后，使用常规蚀刻剂及程序移除牺牲栅极324。接下来，使用常规蚀刻剂及程序移除牺牲电介质结构326以形成暴露耐蚀刻区段336及沟道区354的顶表面的开口370。
如图3L中所展示，在已形成开口370之后，以常规方式将高k栅极电介质层372形成为给开口370加衬且接触电介质结构364的顶表面。具有与侧壁间隔件345不同的材料组成的高k栅极电介质层372可用若干种材料来实施，例如氧化铪及氧化硅铪的顺序层。
接下来，以常规方式将金属层374沉积为接触高k栅极电介质层372且填充开口370。金属层374可用各自部分地填充开口370的若干种材料来实施，例如氮化钛、氮化钽及铝的顺序层。
如图3M中所展示，在已沉积金属层374之后，例如借助化学-机械抛光对高k电介质层372及金属层374进行平面化，直到电介质结构364的顶表面已被暴露为止。所述平面化在开口370中形成金属栅极380以及接触金属栅极380及沟道区354的高k电介质结构382。金属栅极380及高k电介质结构382形成栅极结构384。所述平面化还形成金属栅极MOS晶体管390。由于所述平面化，电介质结构364、金属栅极380及高k电介质结构382的顶表面实质上位于同一平面中。此后，方法300以常规步骤继续。
本发明的优点之一是，金属栅极230/380与源极区220/350及漏极区222/352分离将金属栅极130与源极区120及漏极区122分离的较大距离。所述分离距离越大，就会越多地减小重叠电容。
因此，牺牲栅极电介质层316被形成为越厚，将金属栅极230/380与源极区220/350及漏极区222/352分离的垂直距离就越大。此外，腔328被形成为越深，将金属栅极230/380与源极区220/350及漏极区222/352分离的水平距离就越大。
所属领域的技术人员将了解，在所主张发明的范围内，可对所描述实施例做出修改，并且许多其它实施例也为可能的。

Claims (20)

1.一种半导体结构，其包括：
半导体区，其具有一导电性类型；
源极，其接触所述半导体区，所述源极具有与所述半导体区的所述导电性类型相反的导电性类型；
漏极，其接触所述半导体区，所述漏极位于与所述源极间隔开之处，且具有与所述半导体区的所述导电性类型相反的导电性类型；
所述半导体区的沟道区，其位于所述源极与所述漏极之间；
栅极电介质，其接触所述沟道区且位于所述沟道区上方；及
金属栅极，其接触所述栅极电介质且位于所述栅极电介质上方，所述金属栅极具有下部宽度及大于所述下部宽度的上部宽度。
2.根据权利要求1所述的结构，其中所述金属栅极具有顶表面及接触所述顶表面的外表面；且所述栅极电介质接触所述外表面的全部。
3.根据权利要求1所述的结构，其进一步包括接触所述栅极电介质且横向环绕所述栅极电介质及所述金属栅极两者的不导电侧壁间隔件。
4.根据权利要求3所述的结构，其中所述栅极电介质及所述不导电侧壁间隔件具有不同材料组成。
5.根据权利要求4所述的结构，其中所述栅极电介质为高k栅极电介质。
6.根据权利要求5所述的结构，其中所述不导电侧壁间隔件包含氮化物区。
7.根据权利要求3所述的结构，其中所述不导电侧壁间隔件的一部分垂直位于所述半导体区与所述金属栅极正中间。
8.根据权利要求3所述的结构，其中所述不导电侧壁间隔件的一部分垂直位于所述沟道区与所述金属栅极正中间。
9.根据权利要求4所述的结构，其进一步包括接触所述不导电侧壁间隔件且位于所述源极及所述漏极上方的互连电介质结构。
10.一种半导体结构，其包括：
半导体区，其具有一导电性类型；
源极，其接触所述半导体区，所述源极具有与所述半导体区的所述导电性类型相反的导电性类型；
漏极，其接触所述半导体区，所述漏极位于与所述源极间隔开之处，且具有与所述半导体区的所述导电性类型相反的导电性类型；
所述半导体区的沟道区，其位于所述源极与所述漏极之间；
栅极电介质，其接触所述沟道区且位于所述沟道区上方；
金属栅极，其接触所述栅极电介质且位于所述栅极电介质上方；及
不导电侧壁间隔件，其接触所述栅极电介质且横向环绕所述栅极电介质及所述金属栅极两者，所述不导电侧壁间隔件的一部分垂直位于所述半导体区与所述金属栅极正中间。
11.根据权利要求10所述的结构，其中所述栅极电介质及所述不导电侧壁间隔件具有不同材料组成。
12.根据权利要求11所述的结构，其中所述栅极电介质为高k栅极电介质。
13.根据权利要求12所述的结构，其中所述不导电侧壁间隔件包含氮化物区。
14.根据权利要求11所述的结构，其中所述金属栅极具有顶表面及接触所述顶表面的外表面；且所述栅极电介质接触所述顶表面的全部。
15.根据权利要求14所述的结构，且其进一步包括接触所述不导电侧壁间隔件且位于所述源极及所述漏极上方的互连电介质结构。
16.一种形成半导体结构的方法，其包括：
形成接触半导体区的栅极结构，所述栅极结构具有牺牲栅极电介质及牺牲栅极，所述牺牲栅极电介质接触所述半导体区，所述牺牲栅极接触所述牺牲栅极电介质，所述半导体区具有一导电性类型；
蚀刻掉所述牺牲栅极电介质的一部分以形成牺牲电介质结构及腔，所述牺牲电介质结构接触所述牺牲栅极及所述半导体区，所述腔垂直位于所述牺牲栅极的一部分正下方；及
在已形成所述牺牲电介质结构之后，形成接触所述半导体区的源极及漏极，所述源极及所述漏极各自具有与所述半导体区的所述导电性类型相反的导电性类型。
17.根据权利要求16所述的方法，其进一步包括形成接触所述牺牲电介质结构及所述牺牲栅极的不导电侧壁间隔件，所述不导电侧壁间隔件的一部分在所述腔中垂直位于所述半导体区与所述牺牲栅极正中间。
18.根据权利要求17所述的方法，其进一步包括在已形成所述不导电侧壁间隔件之后移除所述栅极结构以形成开口，所述开口暴露所述半导体区的沟道区。
19.根据权利要求18所述的方法，其进一步包括在所述开口中形成栅极电介质结构及金属栅极，所述栅极电介质结构接触所述半导体区，所述金属栅极接触所述栅极电介质结构。
20.根据权利要求19所述的方法，其中所述栅极电介质结构与所述不导电侧壁间隔件具有不同材料组成。
CN201380053370.5A 2012-11-08 2013-11-08 具有减小的栅极到源极与栅极到漏极重叠电容的金属栅极mos晶体管 Active CN104718626B (zh)

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CN104718626B (zh) 2018-01-19
US20140124874A1 (en) 2014-05-08

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