CN104716018B - The color method and mixed solution of N traps and deep N-well - Google Patents
The color method and mixed solution of N traps and deep N-well Download PDFInfo
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- CN104716018B CN104716018B CN201310684651.2A CN201310684651A CN104716018B CN 104716018 B CN104716018 B CN 104716018B CN 201310684651 A CN201310684651 A CN 201310684651A CN 104716018 B CN104716018 B CN 104716018B
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- 239000011259 mixed solution Substances 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000004065 semiconductor Substances 0.000 claims abstract description 71
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 54
- 238000004040 coloring Methods 0.000 claims abstract description 49
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims abstract description 27
- 229910017604 nitric acid Inorganic materials 0.000 claims abstract description 27
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims abstract description 23
- 239000008367 deionised water Substances 0.000 claims abstract description 22
- 229910021641 deionized water Inorganic materials 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims description 29
- 150000002500 ions Chemical class 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 230000035484 reaction time Effects 0.000 claims description 4
- 239000002210 silicon-based material Substances 0.000 claims description 3
- 238000004458 analytical method Methods 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 6
- 238000005516 engineering process Methods 0.000 abstract description 6
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 12
- 239000007789 gas Substances 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000001514 detection method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000003153 chemical reaction reagent Substances 0.000 description 3
- 239000003086 colorant Substances 0.000 description 3
- 239000007853 buffer solution Substances 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- -1 fluorine ions Chemical class 0.000 description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- BLIQUJLAJXRXSG-UHFFFAOYSA-N 1-benzyl-3-(trifluoromethyl)pyrrolidin-1-ium-3-carboxylate Chemical compound C1C(C(=O)O)(C(F)(F)F)CCN1CC1=CC=CC=C1 BLIQUJLAJXRXSG-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000000872 buffer Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000012916 structural analysis Methods 0.000 description 1
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- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention discloses a kind of N traps in semiconductor devices and the color method and mixed solution of deep N-well.The present invention is first performed etching before being coloured to N traps and deep N-well to semiconductor structure, so that semiconductor structure becomes loose, so that subsequent mixed solution is coloured to loose N traps and deep N-well region；It is 20 that volume ratio is employed in coloring process:50:The new mixed solution of 1 deionized water, 70% concentration nitric acid and 49% concentration hydrofluoric acid so that the colouring rate to N traps and deep N-well is controllable, and good coloring effect can be reached.When the present invention solves progress FA analyses at present, the problem of difficult is coloured to N traps in the semiconductor devices less than 90nm making technologies and deep N-well.
Description
Technical Field
The invention relates to a semiconductor analysis technology, in particular to a method for coloring an N well and a deep N well in fault analysis and a mixed solution for coloring the N well and the deep N well.
Background
Coloring (stain) is a common means used in FA (Failure Analysis) to detect doping profiles or structure profiles. For example, for the cross-section CA (structural Analysis) Analysis of a SEM (Scanning Electron Microscope) of a Semiconductor device, HF (hydrofluoric acid) coloring is required, for GOX (Gate Oxide) coloring, for NMOS (N-Metal-Oxide-Semiconductor) doping detection, N-type doping etching liquid coloring is required.
However, in FA, the doping profile detection for N-well (N-well) and Deep N-well (DNW, Deep N-well) is a difficult problem.
Fig. 1 is a schematic structural diagram of a Semiconductor device, which is a CMOS (complementary Metal-Oxide-Semiconductor) device and includes an NMOS and a PMOS. As shown in fig. 1, the structure includes a substrate 1, a deep N well 2 formed in the substrate 1, and an STI (Shallow Trench Isolation) 3 formed above the deep N well 2, and PMOS and NMOS respectively located at two sides of the STI 3. Wherein the PMOS includes: the semiconductor device comprises an N well 41 formed in a substrate 1, a gate 43 located on the substrate 1, source/drain regions 42 located on two sides of the gate 43 and located in the substrate 1, and side walls 44 located on two sides of the gate 43 and located above the substrate 1. The NMOS includes: the semiconductor device comprises a P well 51 formed in a substrate 1, a gate 53 located on the substrate 1, source/drain regions 52 located on two sides of the gate 53 and located in the substrate 1, and side walls 54 located on two sides of the gate 53 and located above the substrate 1. The NMOS and PMOS structures are substantially the same, but are separated into N-type and P-type by doping ions, wherein the NMOS is located above the P-well 51, the NMOS source/drain region 52 is N-type doped, the PMOS is located above the N-well 41, and the PMOS source/drain region 42 is P-type doped. An Inter Layer Dielectric (ILD) 6 is formed over the NMOS and PMOS, and vias 7 may be provided in the NMOS and/or PMOS source/drain regions 42, 52 and gates 43, 53 for circuit connection, as required by the circuit design.
As shown in fig. 1, in the CMOS structure, the source/drain region, the lightly doped drain region, etc. are shallow in position, and the used reagent is liable to penetrate and react with the relevant region to be colored, but for the N-well 41 and the deep N-well 2, since they are deep (at the bottom of PMOS), the reagent for coloring is difficult to enter the N-well 41 and the deep N-well 2, or coloring is excessive to affect other regions so as to blur the doping profile, and each region is indistinguishable, thereby affecting FA detection.
For coloring semiconductor devices, the more advanced the process, the lower the doping concentration, and the less susceptible the coloring reaction. In addition, it should be noted that in the MOS device, the doping concentration of the N-well and the deep N-well is lower than that of the other portions of the MOS device, and therefore the N-well and the deep N-well are also the portions of the MOS device that are most difficult to be colored.
At present, 98% acetic acid (CH) is generally used as the coloring agent for the N-well 41 and the deep N-well 23OOH), 70% nitric acid (HNO)3) And 49% hydrofluoric acid (HF) in a volume ratio of 100:20:1, for example, 100ml of 98% acetic acid, 20ml of 70% nitric acid and 1ml of 49% hydrofluoric acid, wherein the acetic acid is used as a buffer to dilute the acidity of the coloring agent, the nitric acid is used to oxidize silicon elements, and the hydrofluoric acid is used to react with the oxide to form the outline of the colored region, the mixed solution can color the N well 41 and the deep N well 2 well in a process in which the CD (Critical Dimension) is 90nm or more, and the coloring time with the mixed solution is 19 to 21s (seconds), preferably 20s, for a semiconductor device manufactured by 90nm, the doping concentration at which the mixed solution can be colored using the conventional coloring agent is at least 1 × 1013atoms/cm2On the order of (atoms/cm) for example, an N-well doping concentration of about 2.8 × 10 for a 90nm process13atoms/cm2The doping concentration of the deep N-well is about 1.1 × 1013atoms/cm2Both of them have a doping concentration of 1 × 1013atoms/cm2On the order of magnitude, the existing mixed solution can achieve good results in the coloration of 90nm technology N-wells and deep N-wells, but for semiconductor devices under advanced manufacturing processes with smaller CDs (e.g., 65nm, 45nm, 32 nm), the doping concentration of the N-well and the deep N-well is lower and is lower than 1 × 1013atoms/cm2And the coloring is less easy, and the coloring using the existing mixed solution is difficult to control. If the coloring time is slightly longer, the entire well structure is easily broken, as shown by the black area in fig. 2, and in fig. 2, the gates 43, 53, the source/drain regions 42, 52, the N-well 41, the P-well 51, and the deep N-well 2 are all over-colored and difficult to distinguish due to over-coloring. If the coloring time is slightly short, the coloring effect cannot be achieved, and only the gate electrode 53 and the source/drain region 52 in the shallow region are colored as shown in the mesh region of fig. 3. Therefore, the existing mixed solution and coloring method are difficult to be applied in the advanced process technology with CD less than 90nmA semiconductor device is provided.
Disclosure of Invention
In view of this, the present invention provides a method for coloring an N-well and a deep N-well of a semiconductor device, so as to color the N-well and the deep N-well of the semiconductor device in an advanced process with a CD smaller than 90nm, so that the colored region has a clear outline and is favorable for FA detection.
The technical scheme of the application is realized as follows:
a method of coloring N-wells and deep N-wells, comprising:
etching the semiconductor structure to loosen the semiconductor structure;
and reacting the loose semiconductor structure by adopting a mixed solution of deionized water, nitric acid and hydrofluoric acid so as to color the N well and the deep N well in the semiconductor structure.
Further, etching the semiconductor structure includes:
using XeF2And etching the semiconductor structure by using gas, so that F ions in the semiconductor structure etch silicon materials in the semiconductor structure, and further the semiconductor structure is loosened.
Further, when etching, XeF2The gas flow can be controlled at 3 × 106～8×106nm3And/s, the etching reaction time is 1-5 s.
Further, the mixed solution is formed by mixing deionized water, 70% nitric acid and 49% hydrofluoric acid, and the volume ratio of the deionized water to the 70% nitric acid to the 49% hydrofluoric acid is 20:50: 1.
Further, the duration of the reaction of the loose semiconductor structure by adopting the mixed solution of deionized water, nitric acid and hydrofluoric acid is 24-36 s.
Further, the semiconductor structure includes:
a substrate;
a deep N-well formed in the substrate;
an N well in the substrate above the deep N well;
a gate electrode on the substrate;
the source/drain regions are positioned at two sides of the grid electrode and in the substrate; and
and the side walls are positioned on two sides of the grid and positioned above the substrate.
Further, the mixed solution is formed by mixing deionized water, 70% nitric acid and 49% hydrofluoric acid, and the volume ratio of the deionized water to the 70% nitric acid to the 49% hydrofluoric acid is 20:50: 1.
According to the coloring method and the mixed solution for the N well and the deep N well, the semiconductor structure is etched before coloring so as to be loosened, so that the loosened N well and the deep N well are colored by the mixed solution, and a new mixed solution of deionized water, 70% nitric acid and 49% hydrofluoric acid in a volume ratio of 20:50:1 is adopted in the coloring process, so that the coloring rate of the N well and the deep N well is controllable, and a good coloring effect can be achieved. The invention solves the problem that N wells and deep N wells in semiconductor devices with the process technology less than 90nm are difficult to color when FA analysis is carried out at present.
Drawings
FIG. 1 is a schematic diagram of a semiconductor device;
FIG. 2 is a schematic illustration of a prior art method of failing to tint N-wells and deep N-wells of a semiconductor device fabricated at less than 90 nm;
FIG. 3 is a schematic diagram of a prior art method for failing to color N-wells and deep N-wells of a semiconductor device fabricated at less than 90 nm;
FIG. 4 is a flow chart of an embodiment of an N-well and deep N-well shading method of the present invention;
FIG. 5 is a schematic diagram of an embodiment of a semiconductor structure after etching in the method of the present invention;
FIG. 6 is a schematic view of an embodiment of the semiconductor structure colored by the mixed solution of the present invention in the method of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and examples.
An embodiment of a semiconductor structure using the N-well and deep N-well coloration methods of the present invention may be referred to the structure shown in fig. 1, which includes: the semiconductor device comprises a substrate 1, a deep N well 2 formed in the substrate 1, an N well 41 in the substrate 1 and located above the deep N well 2, a gate 43 located above the substrate 1, source/drain regions 42 located on two sides of the gate 43 and located in the substrate 1, and side walls 44 located on two sides of the gate 43 and located above the substrate 1, wherein the substrate 1 is made of silicon. The structure is a common PMOS structure in the art, and in a CMOS, the structure further includes an NMOS that is the same as the PMOS structure, and details are not repeated here.
As shown in fig. 4, the coloring method of the N-well and the deep N-well of the present invention includes:
etching the semiconductor structure to loosen the semiconductor structure;
and reacting the loose semiconductor structure by adopting a mixed solution of deionized water, nitric acid and hydrofluoric acid so as to color the N well and the deep N well in the semiconductor structure.
The method for coloring the N-well and the deep N-well according to the present invention will be described in detail with reference to fig. 5 and 6.
Step 1, etching the semiconductor structure to loosen the semiconductor structure.
In this step 1, XeF is used2Etching the semiconductor structure by using (xenon difluoride) gas so that fluorine ions in the semiconductor structure etch silicon materials in the semiconductor structure. As a specific example, when etching, XeF2The gas flow can be controlled at 3 × 106～8×106nm3Cubic nanometer/second (nm/s), preferably 6.9 × 106nm3And/s, controlling the etching reaction time to be 1-5 s (second), preferably 3 s. The semiconductor structure after the step 1 can be seen in FIG. 5, in which XeF is performed2After the etching of the gas, the structures of the gate electrodes 43 and 53, the source/drain regions 42 and 52, the N-well 41, the P-well 51 and the deep N-well 2 in the semiconductor structure become loose, and when the next step of coloring is performed, the loose structure can make the mixed solution used for coloring easily infiltrate to be in sufficient contact with the loose regions so as to facilitate reaction, otherwise, the mixed solution and the colored regions are difficult to react due to the lower doping concentrations of the N-well 41 and the deep N-well 2. Note that XeF is used in the present step 12The process of etching the semiconductor structure by the gas does not damage the doping concentration in the semiconductor structure.
And 2, reacting the loose semiconductor structure by adopting a mixed solution of deionized water, nitric acid and hydrofluoric acid so as to color the N well and the deep N well in the semiconductor structure.
In step 2, the mixed solution is prepared from deionized water (DI water) and 70% nitric acid (HNO)3) And 49% hydrofluoric acid at a volume ratio of 20:50:1, and the mixed solution of the present invention is prepared by mixing 20ml of deionized water, 50ml of 70% nitric acid, and 1ml of 49% hydrofluoric acid. In the mixed solution, deionized water is used as a buffer solution to dilute the acidity of the mixed solution, nitric acid is used for oxidizing silicon elements, and hydrofluoric acid is used for reacting with the oxide to form the contour of the coloring area. In the step 2, the deionized water, the nitric acid and the hydrofluoric acid are adoptedThe duration of the reaction of the mixed acid solution on the loose semiconductor structure is 24-36 s, and preferably 30 s.
The mixed solution is adopted in the step 2, and the doping concentration range can be in 1 × 1012～1×1013atoms/cm2(experiments prove that the applicable doping concentration of the mixed solution can be as small as 1 × 1012atoms/cm2) N-well and deep N-well are colored, the color is less than 1 × 1012～1×1013atoms/cm2The doping concentration range of the N well and the deep N well is suitable for the N well and the deep N well in the advanced semiconductor manufacturing process with the CD less than 90nm, such as the N well and the deep N well in 65nm, 55nm and 45nm processes, and is suitable for detecting the profile of a well region.
Compared with the mixed solution adopted in the prior art, the mixed solution provided by the invention comprises the following components in percentage by weight: the deionized water is used as a buffer solution to replace acetic acid to dilute the acidity of the coloring reagent, so that H in the mixed solution is reduced+The content of ions (hydrogen ions) is reduced, so that the acidity of the mixed solution is reduced, and the influence of coloring is weakened; the nitric acid with the largest proportion is adopted, the oxidation effect of the mixed solution is enhanced, and more nitric acid is needed to oxidize the silicon element in consideration of nitric acid oxidation and lower doping concentrations of the N well and the deep N well; the proportion of hydrofluoric acid is slightly increased, so that the coloring rate can be accelerated, and the reaction process can be controlled.
The practical coloring experiment result of the semiconductor device by the method of the invention can observe the outline of the N well and the deep N well under SEM, and can achieve very clear effect.
According to the coloring method and the mixed solution for the N well and the deep N well, the semiconductor structure is etched before coloring so that the semiconductor structure becomes loose, the mixed solution is favorable for coloring the loose N well and the deep N well area, and a new mixed solution of deionized water, 70% concentration nitric acid and 49% concentration hydrofluoric acid in a volume ratio of 20:50:1 is adopted in the coloring process, so that the coloring rate of the N well and the deep N well is controllable, and a good coloring effect can be achieved. The invention solves the problem that N wells and deep N wells in semiconductor devices with the process technology less than 90nm are difficult to color when FA analysis is carried out at present.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (7)
1. A method of coloring N-wells and deep N-wells, comprising:
etching the semiconductor structure to loosen the semiconductor structure;
reacting a loose semiconductor structure by adopting a mixed solution of deionized water, nitric acid and hydrofluoric acid so as to color an N well and a deep N well in the semiconductor structure; wherein,
the N well and the deep N well are the N well and the deep N well in the advanced semiconductor manufacturing process with the critical dimension CD smaller than 90 nm.
2. The method of claim 1 wherein etching the semiconductor structure comprises:
using XeF2And etching the semiconductor structure by using gas, so that F ions in the semiconductor structure etch silicon materials in the semiconductor structure, and further the semiconductor structure is loosened.
3. The method of coloring N-wells and deep N-wells of claim 2, wherein:
during etching, XeF2The gas flow can be controlled at 3 × 106～8×106nm3And/s, the etching reaction time is 1-5 s.
4. The method for coloring an N-well and a deep N-well according to claim 1, wherein the mixed solution is formed by mixing deionized water, 70% nitric acid and 49% hydrofluoric acid, and the volume ratio of the deionized water, the 70% nitric acid and the 49% hydrofluoric acid is 20:50: 1.
5. The method of claim 4, wherein the reaction time of the loose semiconductor structure with the mixed solution of deionized water, nitric acid and hydrofluoric acid is 24-36 s.
6. The method of colouring N-wells and deep N-wells according to any of claims 1 to 5, wherein the semiconductor structure comprises:
a substrate;
a deep N-well formed in the substrate;
an N well in the substrate above the deep N well;
a gate electrode on the substrate;
the source/drain regions are positioned at two sides of the grid electrode and in the substrate; and
and the side walls are positioned on two sides of the grid and positioned above the substrate.
7. A mixed solution of N-well and deep N-well coloring, characterized by: the mixed solution is formed by mixing deionized water, 70% nitric acid and 49% hydrofluoric acid, and the volume ratio of the deionized water to the 70% nitric acid to the 49% hydrofluoric acid is 20:50: 1; wherein,
the N well and the deep N well are the N well and the deep N well in the advanced semiconductor manufacturing process with the critical dimension CD smaller than 90 nm.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5421958A (en) * | 1993-06-07 | 1995-06-06 | The United States Of America As Represented By The Administrator Of The United States National Aeronautics And Space Administration | Selective formation of porous silicon |
| CN101996880A (en) * | 2009-08-14 | 2011-03-30 | 中芯国际集成电路制造(上海)有限公司 | Method for exposing semiconductor substrate and invalidation analysis method |
| CN102044461A (en) * | 2009-10-20 | 2011-05-04 | 中芯国际集成电路制造(上海)有限公司 | Detection method used for failure analysis of semiconductor device |
| CN102115024A (en) * | 2009-12-30 | 2011-07-06 | 中国科学院微电子研究所 | System and method for releasing MEMS structure by etching silicon sacrificial layer |
| CN202815008U (en) * | 2012-09-21 | 2013-03-20 | 中国科学院地质与地球物理研究所 | Accelerometer |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS4831031B1 (en) * | 1968-11-20 | 1973-09-26 |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5421958A (en) * | 1993-06-07 | 1995-06-06 | The United States Of America As Represented By The Administrator Of The United States National Aeronautics And Space Administration | Selective formation of porous silicon |
| CN101996880A (en) * | 2009-08-14 | 2011-03-30 | 中芯国际集成电路制造(上海)有限公司 | Method for exposing semiconductor substrate and invalidation analysis method |
| CN102044461A (en) * | 2009-10-20 | 2011-05-04 | 中芯国际集成电路制造(上海)有限公司 | Detection method used for failure analysis of semiconductor device |
| CN102115024A (en) * | 2009-12-30 | 2011-07-06 | 中国科学院微电子研究所 | System and method for releasing MEMS structure by etching silicon sacrificial layer |
| CN202815008U (en) * | 2012-09-21 | 2013-03-20 | 中国科学院地质与地球物理研究所 | Accelerometer |
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