CN104715732B - Grid driving circuit and display device - Google Patents
Grid driving circuit and display device Download PDFInfo
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- CN104715732B CN104715732B CN201510116755.2A CN201510116755A CN104715732B CN 104715732 B CN104715732 B CN 104715732B CN 201510116755 A CN201510116755 A CN 201510116755A CN 104715732 B CN104715732 B CN 104715732B
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- 235000008694 Humulus lupulus Nutrition 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 8
- 239000004973 liquid crystal related substance Substances 0.000 description 8
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- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 229910021419 crystalline silicon Inorganic materials 0.000 description 3
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- 238000012986 modification Methods 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
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- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
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- 239000011787 zinc oxide Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
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- 239000010408 film Substances 0.000 description 1
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Abstract
The invention discloses a grid driving circuit which comprises multiple stages of grid driving units. Each stage of grid driving unit comprises switch elements from first to tenth, wherein a first stable unit is composed of the fourth switch element and the fifth switch element, the control end, namely, the fourth control end of the fourth switch element and the fifth control end of the fifth switch element, of the first stable unit is connected with the public end of the sixth switch element and the seventh switch element, and a second stable unit is composed of the tenth switch element. The invention further provides a display device. The stable units of the grid driving circuit and the display device are composed of the switch elements, the control end of each first stable unit is charged through the corresponding switch elements each time a clock signal hops, the stability of the voltage of the control end of each first stable unit is ensured, and therefore the stability of a grid driving signal is improved; each stage of grid driving unit is only composed of the corresponding ten switch elements, and therefore the design of a narrow frame is facilitated, cost is low, and power consumption is low.
Description
Technical field
The present invention relates to display technology field, particularly to a kind of gate driver circuit and display device.
Background technology
Liquid crystal indicator (liquid crystal display, lcd) possesses frivolous, energy-conservation, radiationless etc. many excellent
Point, has therefore gradually replaced traditional cathode ray tube (crt) display.Liquid crystal display is widely used in height at present
The clear electronics such as DTV, desk computer, personal digital assistant (pda), notebook computer, mobile phone, digital camera
In equipment.
Taking thin film transistor (TFT) (thin film transistor, tft) liquid crystal indicator as a example, comprising: liquid crystal
Show panel and drive circuit, wherein, display panels include a plurality of gate line and a plurality of data lines, and two adjacent grids
Line intersects to form a pixel cell with two adjacent data line, and each pixel cell at least includes a tft.Drive circuit
Including gate driver circuit (gate drive circuit) and source electrode drive circuit (source drive circuit).With
Producer the cost degradation of liquid crystal indicator is pursued and manufacturing process raising, be originally arranged at display panels with
Outer drive circuit integrated chip is arranged on the glass substrate of display panels and becomes possibility, for example, grid is driven
Dynamic integrated circuit is arranged at array base palte (gate ic in array, gia) above thus simplifying the manufacture of liquid crystal indicator
Journey, and reduce production cost.
Display panels with the basic functional principle of drive circuit are: gate driver circuit is by electrically connecting with gate line
Pulling up transistor of connecing sends gate drive signal to gate line, sequentially opens the tft of every a line, then by source drive electricity
The pixel cell of one full line is charged to each required voltage by road simultaneously, to show different GTGs.I.e. first by the first row
Gate driver circuit pulled up transistor by it thin film transistor (TFT) of the first row opened, then by source electrode drive circuit to
The pixel cell of a line is charged.When the pixel cell of the first row is charged, gate driver circuit is just by this row film crystal
Pipe is closed, and then the gate driver circuit of the second row is pulled up transistor by it and opens the thin film transistor (TFT) of the second row, then by
Source electrode drive circuit carries out discharge and recharge to the pixel cell of the second row.So sequentially go down, when the pixel of last column of having substituted the bad for the good
Unit, just starts to charge up from the first row again.
At present, gate driver circuit adopts the tft of non-crystalline silicon mostly, but because non-crystalline silicon mobility is relatively low, and non-crystalline silicon
Threshold voltage drift characteristic, play in gate driver circuit transmission effect tft cannot long-time stable be operated in one stable
Grid voltage under, therefore, the difference of this operating characteristic of tft is finally easily caused the failure of signal transmission.Additionally, grid
Drive circuit mostly using gate drive signal as transmission signal so that the grid voltage of tft playing output action cannot reach
To ideal height, so that the time delayses of gate drive signal output, even more so that gate drive signal cannot have been realized
The transmission of effect.
Prior art typically adopts new tft processing technology for example with indium gallium zinc oxide igzo (indium
Gallium zinc oxide, igzo) tft or using bistable system or increase tft breadth length ratio to solve the above problems,
But said method is unfavorable for the design of the narrow frame of liquid crystal indicator, high cost and power consumption is big.
Content of the invention
The main technical problem to be solved in the present invention is to provide a kind of gate driver circuit, and it can export stable grid
While drive signal, be conducive to the design of narrow frame, low cost and small power consumption.
For solving above-mentioned technical problem, the invention provides a kind of gate driver circuit, it includes multiple raster data model lists
Unit, described every grade of drive element of the grid includes first switch element, second switch element, the 3rd switch element, the 4th switch unit
Part, the 5th switch element, the 6th switch element, the 7th switch element, the 8th switch element, the 9th switch element, the tenth switch
Element.
Wherein, first switch element includes the first path terminal, the first control end, alternate path end, described first path terminal
Receive the first pulse signal, described first control end receives the first transmission signal, and signal is transmitted for this level in described alternate path end
Outfan.Second switch element includes third path end, the second control end, fourth passage end, and described third path end receives
First clock signal, described second control end is connected with the described alternate path end of described first switch element, and passes through first
Electric capacity is connected with described fourth passage end, and described fourth passage end is the outfan of every grade of drive element of the grid.
3rd switch element includes fifth passage end, the 3rd control end, clematis stem terminal, described fifth passage end with described
The described alternate path end of first switch element is connected, and described 3rd control end receives the second transmission signal, and clematis stem terminal connects
Receive the second pulse signal.4th switch element includes the 7th path terminal, the 4th control end, the 8th path terminal, described 7th path
End is connected with the described fourth passage end of described second switch element, and described 8th path terminal receives low reference voltage.
5th switch element includes the 9th path terminal, the 5th control end, the tenth path terminal, described 9th path terminal with described
Described second control end of second switch element is connected, and described 5th control end is controlled with the described 4th of described 4th switch element
End processed is connected, and described tenth path terminal receives described low reference voltage.6th switch element includes the 11st path terminal, the 6th control
End processed, the 12nd path terminal, described 11st path terminal receives described first clock signal, described 6th control end and described the
11 path terminal are connected, and the 12nd path terminal is connected with described 5th control end of described 5th switch element.7th switch unit
Part includes the tenth threeway terminal, the 7th control end, the 14th path terminal, and described tenth threeway terminal and described 7th control end are equal
It is connected with described 5th control end of described 5th switch element, described 14th path terminal receives described low reference voltage.
8th switch element includes the 15th path terminal, the 8th control end, the tenth clematis stem terminal, described 15th path terminal
It is connected with described 5th control end of described 5th switch element, described 8th control end is described with described second switch element
Second control end is connected, and described tenth clematis stem terminal receives described low reference voltage.9th switch element includes the 17th path
Described 5th control end of end, the 9th control end, the 18th path terminal, described 17th path terminal and described 5th switch element
It is connected, described 9th control end receives second clock signal, described 18th path terminal receives described low reference voltage.Tenth opens
Close element and include the 19th path terminal, the tenth control end, the 20th path terminal, described 19th path terminal and described second switch
The described fourth passage end of element is connected, and described tenth control end receives described second clock signal, described 20th path terminal
Receive described low reference voltage.
Preferably, described first electric capacity is the described fourth passage end of described second switch element and described second control end
Between parasitic capacitance.
Preferably, it is provided with independence between described second control end of described second switch element and described fourth passage end
Storage capacitance, described first electric capacity is between the described fourth passage end of described second switch element and described second control end
Parasitic capacitance and described separate storage electric capacity sum.
Preferably, if described gate driver circuit includes n level drive element of the grid, the institute of n-th grade of drive element of the grid
The described first transmission signal stating the described first control end reception of first switch element is with n-th grade of drive element of the grid upwards
The upper two-stage transmission signal of the drive element of the grid output of difference two-stage, wherein, n is integer, and n >=3.
Preferably, if described gate driver circuit includes n level drive element of the grid, the institute of n-th grade of drive element of the grid
The described second transmission signal stating the described 3rd control end reception of the 3rd switch element is downward with n-th grade of drive element of the grid
The lower two-stage transmission signal of the drive element of the grid output of difference two-stage, n≤n-2.
Preferably, if described gate driver circuit includes n level drive element of the grid, the institute of n-th grade of drive element of the grid
Described first pulse signal stating the described first path terminal reception of first switch element is with n-th grade of drive element of the grid upwards
The upper level gate drive signal of the drive element of the grid output of difference one-level, wherein, n is integer, and n >=2.
Preferably, if described gate driver circuit includes n level drive element of the grid, the institute of n-th grade of drive element of the grid
Described second pulse signal stating the described clematis stem terminal reception of the 3rd switch element is downward with n-th grade of drive element of the grid
The next stage gate drive signal of the drive element of the grid output of difference one-level, wherein, n is integer, and 0≤n≤n-1.
Preferably, described first clock signal and described second clock signal are inversion signal.
Preferably, the breadth length ratio of described 6th switch element is more than or equal to the breadth length ratio of described 7th switch element.
The present invention also provides a kind of display device, and described display device includes above-mentioned gate driver circuit.
In the gate driver circuit of the present invention and display device, first stablizes unit (the 4th switch element and the 5th switch unit
Part) and second stablize unit (the tenth switch element) and formed by switch element, and each saltus step of the first clock signal is all logical
Cross control end that the 6th switch element stablizes unit to first (the 4th control end of the 4th switch element and the 5th switch element
5th control end) charge it is ensured that first stablizes the stability of the voltage of the control end of unit, thus improve raster data model letter
Number stability, and every grade of drive element of the grid is only made up of to the tenth switch element first switch element, is conducive to narrow side
The design of frame, low cost and small power consumption.
By the detailed description below with reference to accompanying drawing, the other side of the present invention and feature become obvious.But should know
Road, accompanying drawing be only explain purpose design, not as the restriction of the scope of the present invention, this is because its should refer to attached
Plus claim.It should also be noted that unless otherwise noted it is not necessary to scale accompanying drawing, they are only tried hard to conceptually
Structure described herein and flow process are described.
Brief description
Fig. 1 is that the circuit structure of n-th grade of drive element of the grid in the gate driver circuit of first embodiment of the invention shows
It is intended to.
Fig. 2 is the time diagram of n-th grade of drive element of the grid in the gate driver circuit of first embodiment of the invention.
Fig. 3 is that the gate driver circuit of first embodiment of the invention and the grid of prior art drive at normal temperatures and under high temperature
The analog result contrast schematic diagram of the magnitude of voltage of node qb in galvanic electricity road.
Fig. 4 is that the gate driver circuit of first embodiment of the invention is identical in work with the gate driver circuit of prior art
After time first stablizes the current analog Comparative result schematic diagram of unit.
Fig. 5 be the first order drive element of the grid of the gate driver circuit of first embodiment of the invention under cryogenic extremely
The analog result schematic diagram of the gate drive signal of level V drive element of the grid output.
Specific embodiment
For further illustrating that the present invention is to reach technological means and effect that predetermined goal of the invention is taken, below in conjunction with
Accompanying drawing and preferred embodiment, to according to its specific embodiment of display panels proposed by the present invention, method, step, structure,
Feature and effect, after describing in detail such as.
For the present invention aforementioned and other technology contents, feature and effect, following cooperation with reference to schema preferable reality
Apply in the detailed description of example and can clearly present.By the explanation of specific embodiment, when to the present invention can be reach predetermined
Technological means that purpose is taken and effect be able to more deeply and specific understand, but institute's accompanying drawings be only provide with reference to
Purposes of discussion, is not used for the present invention is any limitation as.
Although the present invention describes different elements, signal, port, assembly or portion using first, second, third, etc. term
Point, but these elements, signal, port, assembly or part are not limited by these terms.These terms are intended merely to one
Individual element, signal, port, assembly or part are made a distinction with another element, signal, port, assembly or part.In the present invention
In, element, port, assembly or part and another element, port, assembly or part " being connected ", " connection " it is possible to understand that
For being directly electrically connected with, or it can be appreciated that there is the indirect electric connection of intermediary element.Unless otherwise defined, otherwise originally
Invent all terms (including technical term and scientific terminology) being used to have and ordinary skill people of the art
The meaning that member is generally understood that.
The gate driver circuit (also referred to as shift register) of the present invention includes multistage drive element of the grid and (also referred to as shifts
Deposit unit), the drive element of the grid of every one-level is corresponding with the every a line gate line on display floater respectively to be electrically connected with, thus
Gate drive signal is sequentially gradually applied on every row gate line, the annexation between drive element of the grid will hereinafter
Elaborate.
Fig. 1 is that the circuit structure of n-th grade of drive element of the grid in the gate driver circuit of first embodiment of the invention shows
It is intended to.The present embodiment gate driver circuit, including multistage drive element of the grid as shown in Figure 1, n-th grade of drive element of the grid is used
In output gate drive signal gn, to drive a corresponding gate line on display floater respectively.As shown in figure 1, every grade of grid
Pole driver element include first switch element m1, second switch element m2, the 3rd switch element m3, the 4th switch element m4,
Five switch element m5, the 6th switch element m6, the 7th switch element m7, the 8th switch element m8, the 9th switch element m9, the tenth
Switch element m10.
Wherein, first switch element m1 includes the first path terminal, the first control end, alternate path end, the first path termination
Receive the first pulse signal, the first control end receives the first transmission signal, alternate path end is the outfan of this grade of transmission signal, uses
Transmit signal qn in exporting this level.Second switch element m2 includes third path end, the second control end, fourth passage end, and the 3rd
Path terminal receives the first clock signal clka, and the second control end is connected with the alternate path end of first switch element m1, and passes through
First electric capacity c1 is connected with fourth passage end, and fourth passage end is the outfan of every grade of drive element of the grid, for exporting this level
Gate drive signal gn.
3rd switch element m3 includes fifth passage end, the 3rd control end, clematis stem terminal, and fifth passage end is opened with first
The alternate path end closing element m1 is connected, and the 3rd control end receives the second transmission signal, and clematis stem terminal receives the second pulse letter
Number.4th switch element m4 includes the 7th path terminal, the 4th control end, the 8th path terminal, and the 7th path terminal is first with second switch
The fourth passage end of part m2 is connected, and the 8th path terminal receives low reference voltage vgl.
5th switch element m5 includes the 9th path terminal, the 5th control end, the tenth path terminal, and the 9th path terminal is opened with second
The second control end closing element m2 is connected, and the 5th control end is connected with the 4th control end of the 4th switch element m4, the tenth path
End receives low reference voltage vgl.6th switch element m6 includes the 11st path terminal, the 6th control end, the 12nd path terminal, the
11 path terminal receive the first clock signals clka, and the 6th control end is connected with the 11st path terminal, the 12nd path terminal and the
5th control end of five switch element m5 is connected.7th switch element m7 include the tenth threeway terminal, the 7th control end, the 14th
Path terminal, the tenth threeway terminal and the 7th control end are all connected with the 5th control end of the 5th switch element m5, the 14th path
End receives low reference voltage vgl.
8th switch element m8 includes the 15th path terminal, the 8th control end, the tenth clematis stem terminal, the 15th path terminal with
5th control end of the 5th switch element m5 is connected, and the 8th control end is connected with second control end of second switch element m2, the
Ten clematis stem terminals receive low reference voltage vgl.9th switch element m9 include the 17th path terminal, the 9th control end, the 18th
Path terminal, the 17th path terminal is connected with the 5th control end of the 5th switch element m5, and the 9th control end receives second clock letter
Number clkc, the 18th path terminal receives low reference voltage vgl.Tenth switch element m10 includes the 19th path terminal, the tenth control
End, the 20th path terminal, the 19th path terminal is connected with the fourth passage end of second switch element m2, the tenth control end reception the
Two clock signals clkc, the 20th path terminal receives low reference voltage vgl.
Wherein, the 4th switch element m4 and the 5th switch element m5 composition first stablizes unit, the tenth switch element m10 structure
Second is become to stablize unit.
Wherein, the alternate path end of first switch element m1, second control end of second switch element m2, the 5th switch unit
The common port of the 8th control end of the 9th path terminal of part m5 and the 8th switch element m8 is designated as node q, the 4th switch element m4
The 4th control end, the 5th control end of the 5th switch element m5, the 12nd path terminal of the 6th switch element m6, the 7th switch
17th path of the tenth threeway terminal, the 15th path terminal of the 8th switch element m8 and the 9th switch element m9 of element m7
The common port at end is designated as node qb.
Wherein, the first electric capacity c1 is the parasitic electricity between the fourth passage end of second switch element m2 and the second control end
Hold.Certainly it will be appreciated by those skilled in the art that, can also be in second control end and the 4th of second switch element m2
Separate storage electric capacity is set between path terminal, and now, the first electric capacity c1 is the fourth passage end and second of second switch element m2
Parasitic capacitance between control end and separate storage electric capacity sum.
In an embodiment of the present invention, if gate driver circuit includes n level drive element of the grid, n-th grade of grid drives
The first transmission signal that first control end of the first switch element m1 of moving cell receives is with n-th grade of drive element of the grid upwards
The upper two-stage transmission signal qn-2 of the drive element of the grid output of difference two-stage, wherein, n is integer, and n >=3.
In an embodiment of the present invention, if gate driver circuit includes n level drive element of the grid, n-th grade of grid drives
The second transmission signal that 3rd control end of the 3rd switch element m3 of moving cell receives is downward with n-th grade of drive element of the grid
Lower two-stage transmission the signal qn+2, n≤n-2 of the drive element of the grid output of difference two-stage.
In an embodiment of the present invention, if gate driver circuit includes n level drive element of the grid, n-th grade of grid drives
The first pulse signal that first path terminal of the first switch element m1 of moving cell receives is with n-th grade of drive element of the grid upwards
The upper level gate drive signal gn-1 of the drive element of the grid output of difference one-level, wherein, n is integer, and n >=2.
In an embodiment of the present invention, if gate driver circuit includes n level drive element of the grid, n-th grade of grid drives
The second pulse signal that the clematis stem terminal of the 3rd switch element m3 of moving cell receives is downward with n-th grade of drive element of the grid
The next stage gate drive signal gn+1 of the drive element of the grid output of difference one-level, wherein, n is integer, and 0≤n≤n-1.
It should be noted that because first order drive element of the grid does not differ the drive element of the grid of one-level upwards, the
One-level drive element of the grid and second level drive element of the grid differ the drive element of the grid of two-stage, afterbody grid upwards
Pole driver element does not differ downwards the drive element of the grid of one-level, and last two-stage drive element of the grid does not differ downwards two-stage
Drive element of the grid, so the first pulse signal that first order drive element of the grid receives, first order drive element of the grid, the
The first transmission signal that two grades of drive element of the grid receive, afterbody drive element of the grid receives described second pulse signal,
Transmission No. the second that last two-stage drive element of the grid receives is intended to be provided by external signal circuit.
In the present embodiment, first switch element is n-type transistor to the tenth switch element m1～m10.First control end
It is grid to the tenth control end.First path terminal of first switch element m1, the third path end of second switch element m2, the 3rd
The fifth passage end of switch element m3, the 7th path terminal of the 4th switch element m4, the 9th path terminal of the 5th switch element m5,
11st path terminal of the 6th switch element m6, the tenth threeway terminal of the 7th switch element m7, the of the 8th switch element m8
15 path terminal, the 17th path terminal of the 9th switch element m9, the 19th path terminal of the tenth switch element m10 are leakage
Pole.The alternate path end of first switch element m1, the fourth passage end of second switch element m2, the 6th of the 3rd switch element m3 the
Path terminal, the 8th path terminal of the 4th switch element m4, the tenth path terminal of the 5th switch element m5, the 6th switch element m6
12nd path terminal, the 14th path terminal of the 7th switch element m7, the tenth clematis stem terminal of the 8th switch element m8, the 9th open
Close the 18th path terminal of element m9, the 20th path terminal of the tenth switch element m10 is source electrode.
Certainly, it will be appreciated by persons skilled in the art that first switch element also may be used to the tenth switch element m1～m10
To be realized, such as p-type transistor using other switch elements.Below with first switch element m1 to the tenth switch element m1
～m10 is for specifically to introduce specific embodiment and its operation principle of the present invention as a example n-type transistor.
Refer to Fig. 2, its be first embodiment of the invention gate driver circuit in n-th grade of drive element of the grid when
Sequence schematic diagram.Wherein, n is integer, and 3≤n≤n-2.As shown in Fig. 2 the first clock signal clka and second clock signal
Clkc is inversion signal that is to say, that the cycle phase of the first clock signal clka and second clock signal clkc is with dutycycle phase
With, and when the first clock signal clka is high level, second clock signal clkc is low level, when the first clock signal clka
During for low level, second clock signal clkc is high level.
The work process of every one-level drive element of the grid is divided into pre-charging stage, pull-up stage, drop-down stage, stabilization sub stage
4 stages:
Pre-charging stage is the first stage: first switch element m1 first control end receive first transmission signal i.e. to
The upper two-stage transmission signal qn-2 of the drive element of the grid output of upper difference two-stage is high level, and when its magnitude of voltage is about first
The twice of the high level of clock signal clka, element m1 is sufficiently conductive for first switch, when the first pulse signal differs one-level upwards
Drive element of the grid output upper level gate drive signal gn-1 be high level when, voltage node q at pass through turn on
The upper level gate drive signal gn-1 that first switch element m1 is differed the drive element of the grid output of one-level upwards is pre-charged,
Second switch element m2 turns on；Further, since the voltage at node q is precharged, the 8th switch element m8 conducting, at node qb
Voltage by conducting the 8th switch element m8 be pulled low to low reference voltage vgl so that the 5th switch element m5 close
Close, drop-down to node q to stop.
The pull-up stage is second stage: when the level of the first clock signal clka is by low uprising, due in pre-charging stage
Node q has been precharged, and therefore, second switch element m2 turns on, due to the conducting of second switch element m2, and due to first
The boot strap of electric capacity c1, the voltage at node q is further pulled up, and at node q voltage be further pulled up so that second
Switch element m2 is conductively more abundant, so that this grade of raster data model letter of the outfan output of this grade of drive element of the grid
Number gn is drawn high by the first clock signal clka by the second switch element m2 of conducting.
It should be noted that in the present invention, can directly adopt the fourth passage end and second of second switch element m2
Parasitic capacitance between control end as the first electric capacity c1, or in order to lift pull-up effect, can also be in second switch element
Separate storage electric capacity is set between second control end of m2 and fourth passage end, and separate storage electric capacity is with second switch element m2's
Parasitic capacitance in parallel collectively as the first electric capacity c1, that is, the first electric capacity c1 be equal to the fourth passage end of second switch element m2 with
Parasitic capacitance between second control end and separate storage electric capacity sum.
The drop-down stage is the phase III: the first clock signal clka is changed into low level from high level, due in the pull-up stage
Under being further pulled up of voltage at node q, and the second transmission signal i.e. drive element of the grid output of difference two-stage downwards
The transmission signal qn+2 of two-stage is about changed into the twice of the first clock signal clka high level, the 3rd switch element m3 conducting, when the
When the two pulse signals i.e. next stage gate drive signal gn+1 of the drive element of the grid output of difference one-level downwards is high level,
Voltage at node q passes through the 3rd switch element m3 of conducting by the second pulse signal i.e. downward raster data model list differing one-level
The next stage gate drive signal gn+1 of unit's output remains high level, and element m2 is in the conduction state for second switch, this grade of grid
The gate drive signal gn of the outfan output of pole driver element passes through the second switch element m2 of conducting by the first clock signal
Clka drags down；As the second pulse signal i.e. next stage gate drive signal gn of the drive element of the grid output of difference one-level downwards
+ 1 from high level be changed into low level when, the voltage at node q by conducting the 3rd switch element m3 by the second pulse signal be
The next stage gate drive signal gn+1 of the drive element of the grid output of difference one-level drags down downwards.
Stabilization sub stage is fourth stage: because the voltage at drop-down stage, node q is pulled low, therefore, second switch unit
Part m2 closes, it is to avoid the impact to gate drive signal gn for first clock signal clka, and the 8th switch element m8 closes simultaneously,
Stopped drop-down to node qb point.When the first clock signal clka is changed into high level from low level, the 6th switch element m6
Conducting, node qb is electrically charged by the 6th switch element m6 of conducting, and the grid of the 7th switch element m7 is the voltage of node qb
The voltage of the grid more than the 8th switch element m8 is the voltage of node q, and the voltage of source electrode of the 7th switch element m7 and
The voltage of the source electrode of eight switch element m8 is identical, and therefore, the grid of the 7th switch element m7 and the voltage difference of source electrode are more than the
The grid of eight switch element m8 and the voltage difference of source electrode, therefore, the impedance of the 7th switch element m7 is less than the 8th switch element
Impedance, the 8th switch element m8 the electric leakage of node qb is caused drop-down be negligible, the voltage of node qb point can pass through
6th switch element m6 of conducting is driven high.4th switch element m4 and the 5th switch element m5 conducting, node q passes through conducting
5th switch element m5 maintains low level, and gate drive signal gn maintains low level by the 4th switch element of conducting.
When second clock signal clkc is changed into high level from low level, the tenth switch element m10 conducting, gate drive signal gn passes through
Tenth switch element m10 of conducting maintains low level, meanwhile, the 9th switch element m9 conducting, node qb passes through the of conducting
Nine switch element m9 are pulled low, and the 4th switch element m4 and the 5th switch element m5 closes.
The first of the first control end reception of the first switch element m1 of the gate driver circuit of the present invention is transmitted signal and is
The upper two-stage of the drive element of the grid output of difference two-stage transmits magnitude of voltage about first clock signal of signal qn-2 upwards
The twice of the high level of clka so that first switch element m1 can mobility is low or low temperature under conditions of all can fully lead
Logical, node q can be pre-charged to the high level of the first clock signal clka, and then has made the switch element (second of output action
Switch element m2) can be sufficiently conductive, the efficiency for charge-discharge of the first electric capacity c1 improves, and then is ensureing between drive element of the grid
The lossless transmission of signal while so that gate driver circuit export preferable gate drive signal.
In an embodiment of the present invention, the breadth length ratio of the 6th switch element m6 is more than the wide long of the 7th switch element m7
Than.The impedance of the 6th switch element m6 when the breadth length ratio of the 6th switch element m6 is more than the breadth length ratio of the 7th switch element m7
Less than the impedance of the 7th switch element m7, the voltage difference between the grid of the 6th switch element m6 and source electrode is less than the 7th switch
Voltage difference between the grid of element m7 and source electrode, therefore, after gate driver circuit longtime running, the 6th switch element
The threshold voltage drift of m6 can be less than the threshold voltage drift of the 7th switch element m7, and then the impedance phase of the 7th switch element m7
Bigger for the 6th switch element m6, therefore the voltage difference between the grid of the 7th switch element m7 and source electrode becomes big,
That is, the magnitude of voltage of node qb increases, and then compensate for the 4th switch element m4 and the 5th switch unit to a certain extent
The problem that the electric current that part m5 brings because threshold voltage drifts about reduces compensate for the first stabilizing power stablizing unit, improves
The stability of gate driver circuit.
Certainly it will be appreciated by those skilled in the art that, the breadth length ratio of the 6th switch element m6 also can be opened equal to the 7th
Close the breadth length ratio of element m7.When the breadth length ratio of the 6th switch element m6 is equal to the 7th switch element m7, the magnitude of voltage of node qb
High level and low level and half equal to the first clock signal clka, it is to avoid the magnitude of voltage of node qb is excessive, and causes
The threshold values excessive situation of drift of the 4th switch element m4 and the 5th switch element m5, no matter and any manufacturing process condition,
Under temperature conditionss, the magnitude of voltage of node qb remains constant, considerably increases the stability of gate driver circuit.
Fig. 3 is that the gate driver circuit of first embodiment of the invention and the grid of prior art drive at normal temperatures and under high temperature
The analog result contrast schematic diagram of the magnitude of voltage of node qb in galvanic electricity road.Wherein, 1. at normal temperatures (27 degrees Celsius) this
The analog result of the magnitude of voltage of node qb in the gate driver circuit of bright first embodiment, 2. existing for (27 degrees Celsius) under room temperature
Have the analog result of the magnitude of voltage of node qb in the gate driver circuit of technology, 3. under (70 degrees Celsius) at high temperature this
The analog result of the magnitude of voltage of node qb in the gate driver circuit of bright first embodiment, 4. existing for (70 degrees Celsius) under high temperature
There is the analog result of the magnitude of voltage of node qb in the gate driver circuit of technology, please also refer to Fig. 1 and Fig. 3, due to first
Each saltus step of clock signal clka is all by the 6th switch element m6 to the first control end (the 4th switch element stablizing unit
4th control end of m4 and the 5th control end of the 5th switch element m5) charge it is ensured that the first control end stablizing unit is
The stability of the voltage of node qb, therefore, the magnitude of voltage of the node qb of the gate driver circuit of first embodiment of the invention is in height
Magnitude of voltage under temperature and room temperature is all more stable.
Fig. 4 is that the gate driver circuit of first embodiment of the invention is identical in work with the gate driver circuit of prior art
After time first stablizes the current analog Comparative result schematic diagram of unit.Wherein, 5. for the first moment gate driver circuit
The first current analog result stablizing unit, 6. for being later than the grid drive of the second moment first embodiment of the invention in the first moment
The first of galvanic electricity road stablizes the current analog result of unit, 7. for the second moment prior art gate driver circuit first steady
The current analog result of order unit.Wherein, the first electric current stablizing unit refers to the 4th switch element m4 and the 5th switch element
Electric current sum on m5.Please also refer to Fig. 1 and Fig. 4, the breadth length ratio due to the 6th switch element m6 is more than the 7th switch element
The breadth length ratio of m7 is the impedance less than the 7th switch element m7 for the impedance of the 6th switch element m6, the grid of the 6th switch element m6
Voltage difference and source electrode between is less than the voltage difference between the grid of the 7th switch element m7 and source electrode, therefore, in grid
After drive circuit longtime running, the threshold voltage drift of the 6th switch element m6 can be less than the threshold values electricity of the 7th switch element m7
Pressure drift, and then the impedance of the 7th switch element m7 is bigger for the 6th switch element m6, so, the 7th switch unit
Voltage difference between the grid of part m7 and source electrode becomes big that is to say, that the magnitude of voltage of node qb increases, and then to a certain degree
On compensate for the 4th switch element m4 and the 5th switch element m5 due to threshold voltage positive excursion so that impedance becomes big and brings
Electric current reduce problem compensate for the first stabilizing power stablizing unit, therefore, the raster data model of first embodiment of the invention
The first of circuit stablize unit electric current drop-out value be significantly less than prior art stable unit electric current drop-out value, therefore, phase
For prior art, the gate driver circuit stability of the present invention is higher.
Fig. 5 be the first order drive element of the grid of the gate driver circuit of first embodiment of the invention under cryogenic extremely
The analog result schematic diagram of the gate drive signal of level V drive element of the grid output.Wherein, g1 is that (minus 20 take the photograph in low temperature
Family name's degree) under the conditions of first embodiment of the invention gate driver circuit the first order drive element of the grid output raster data model letter
Number analog result, g2 is of the gate driver circuit of first embodiment of the invention under the conditions of low temperature (minus 20 degrees Celsius)
The analog result of the gate drive signal of two grades of drive element of the grid outputs, g3 is basis under the conditions of low temperature (minus 20 degrees Celsius)
The analog result of the gate drive signal of third level drive element of the grid output of the gate driver circuit of invention first embodiment,
G4 is the fourth stage raster data model of the gate driver circuit of first embodiment of the invention under the conditions of low temperature (minus 20 degrees Celsius)
The analog result of the gate drive signal of unit output, g5 is that the present invention first is implemented under the conditions of low temperature (minus 20 degrees Celsius)
The analog result of the gate drive signal of level V drive element of the grid output of the gate driver circuit of example.
Please also refer to Fig. 1 and Fig. 5, the first control termination of the first switch element m1 of the gate driver circuit of the present invention
The the first transmission signal the received i.e. upper two-stage of the drive element of the grid output of difference two-stage upwards transmits the magnitude of voltage of signal qn-2
It is about the twice of the high level of the first clock signal clka, so that first switch element m1 can be low or low temperature in mobility
Under the conditions of all can be sufficiently conductive, node q can be pre-charged to the high level of the first clock signal clka, and then has made output action
Switch element (second switch element m2) can be sufficiently conductive, the efficiency for charge-discharge of the first electric capacity c1 improves, and then is ensureing grid
So that the preferable raster data model of gate driver circuit output is believed while the lossless transmission of the signal between the driver element of pole
Number.Therefore, the first order drive element of the grid of the gate driver circuit of first embodiment of the invention is to level V under cryogenic
The rise time of gate drive signal of drive element of the grid output is all comparatively short with fall time, that is, the raster data model letter exporting
Number more satisfactory.
The present invention also provides a kind of display device, and it includes gate driver circuit, and gate driver circuit includes multistage such as Fig. 1
Shown drive element of the grid, n-th grade of drive element of the grid is used for exporting gate drive signal gn, to drive display floater respectively
On a corresponding gate line.As shown in figure 1, every grade of drive element of the grid includes first switch element m1, second switch unit
Part m2, the 3rd switch element m3, the 4th switch element m4, the 5th switch element m5, the 6th switch element m6, the 7th switch element
M7, the 8th switch element m8, the 9th switch element m9, the tenth switch element m10.
Wherein, first switch element m1 includes the first path terminal, the first control end, alternate path end, the first path termination
Receive the first pulse signal, the first control end receives the first transmission signal, alternate path end is the outfan of this grade of transmission signal, uses
Transmit signal qn in exporting this level.Second switch element m2 includes third path end, the second control end, fourth passage end, and the 3rd
Path terminal receives the first clock signal clka, and the second control end is connected with the alternate path end of first switch element m1, and passes through
First electric capacity c1 is connected with fourth passage end, and fourth passage end is the outfan of every grade of drive element of the grid, for exporting this level
Gate drive signal gn.
3rd switch element m3 includes fifth passage end, the 3rd control end, clematis stem terminal, and fifth passage end is opened with first
The alternate path end closing element m1 is connected, and the 3rd control end receives the second transmission signal, and clematis stem terminal receives the second pulse letter
Number.4th switch element m4 includes the 7th path terminal, the 4th control end, the 8th path terminal, and the 7th path terminal is first with second switch
The fourth passage end of part m2 is connected, and the 8th path terminal receives low reference voltage vgl.
5th switch element m5 includes the 9th path terminal, the 5th control end, the tenth path terminal, and the 9th path terminal is opened with second
The second control end closing element m2 is connected, and the 5th control end is connected with the 4th control end of the 4th switch element m4, the tenth path
End receives low reference voltage vgl.6th switch element m6 includes the 11st path terminal, the 6th control end, the 12nd path terminal, the
11 path terminal receive the first clock signals clka, and the 6th control end is connected with the 11st path terminal, the 12nd path terminal and the
5th control end of five switch element m5 is connected.7th switch element m7 include the tenth threeway terminal, the 7th control end, the 14th
Path terminal, the tenth threeway terminal and the 7th control end are all connected with the 5th control end of the 5th switch element m5, the 14th path
End receives low reference voltage vgl.
8th switch element m8 includes the 15th path terminal, the 8th control end, the tenth clematis stem terminal, the 15th path terminal with
5th control end of the 5th switch element m5 is connected, and the 8th control end is connected with second control end of second switch element m2, the
Ten clematis stem terminals receive low reference voltage vgl.9th switch element m9 include the 17th path terminal, the 9th control end, the 18th
Path terminal, the 17th path terminal is connected with the 5th control end of the 5th switch element m5, and the 9th control end receives second clock letter
Number clkc, the 18th path terminal receives low reference voltage vgl.Tenth switch element m10 includes the 19th path terminal, the tenth control
End, the 20th path terminal, the 19th path terminal is connected with the fourth passage end of second switch element m2, the tenth control end reception the
Two clock signals clkc, the 20th path terminal receives low reference voltage vgl.
Wherein, the 4th switch element m4 and the 5th switch element m5 composition first stablizes unit, the tenth switch element m10 structure
Second is become to stablize unit.
Wherein, the alternate path end of first switch element m1, second control end of second switch element m2, the 5th switch unit
The common port of the 8th control end of the 9th path terminal of part m5 and the 8th switch element m8 is designated as node q, the 4th switch element m4
The 4th control end, the 5th control end of the 5th switch element m5, the 12nd path terminal of the 6th switch element m6, the 7th switch
17th path of the tenth threeway terminal, the 15th path terminal of the 8th switch element m8 and the 9th switch element m9 of element m7
The common port at end is designated as node qb.
In an embodiment of the present invention, if gate driver circuit includes n level drive element of the grid, n-th grade of grid drives
The first transmission signal that first control end of the first switch element m1 of moving cell receives is with n-th grade of drive element of the grid upwards
The upper two-stage transmission signal qn-2 of the drive element of the grid output of difference two-stage, wherein, n is integer, and n >=3.
In an embodiment of the present invention, if gate driver circuit includes n level drive element of the grid, n-th grade of grid drives
The second transmission signal that 3rd control end of the 3rd switch element m3 of moving cell receives is downward with n-th grade of drive element of the grid
Lower two-stage transmission the signal qn+2, n≤n-2 of the drive element of the grid output of difference two-stage.
In an embodiment of the present invention, if gate driver circuit includes n level drive element of the grid, n-th grade of grid drives
The first pulse signal that first path terminal of the first switch element m1 of moving cell receives is with n-th grade of drive element of the grid upwards
The upper level gate drive signal gn-1 of the drive element of the grid output of difference one-level, wherein, n is integer, and n >=2.
In an embodiment of the present invention, if gate driver circuit includes n level drive element of the grid, n-th grade of grid drives
The second pulse signal that the clematis stem terminal of the 3rd switch element m3 of moving cell receives is downward with n-th grade of drive element of the grid
The next stage gate drive signal gn+1 of the drive element of the grid output of difference one-level, wherein, n is integer, and 0≤n≤n-1.
In the gate driver circuit of the present invention and display device, first stablizes unit (the 4th switch element m4 and the 5th switch
Element m5) and second stablize unit (the tenth switch element m10) and formed by switch element, and the first clock signal clka is every
Control end that secondary saltus step all stablizes unit by the 6th switch element m6 to first (the 4th control end of the 4th switch element m4 and
5th control end of the 5th switch element m5) charge it is ensured that first stablizes the stability of the voltage of the control end of unit, thus
Improve the stability of gate drive signal, and every grade of drive element of the grid only by first switch element to the tenth switch element
M1～m10 is constituted, and is conducive to the design of narrow frame, low cost and small power consumption.
The above, be only presently preferred embodiments of the present invention, not the present invention is made with any pro forma restriction, though
So the present invention is disclosed above with preferred embodiment, but is not limited to the present invention, any is familiar with this professional technology people
Member, in the range of without departing from technical solution of the present invention, when the technology contents of available the disclosure above make a little change or modification
For the Equivalent embodiments of equivalent variations, as long as being without departing from technical solution of the present invention content, according to the technical spirit pair of the present invention
Any simple modification, equivalent variations and modification that above example is made, all still fall within the range of technical solution of the present invention.
Claims (10)
1. a kind of gate driver circuit, including multiple drive element of the grid, wherein every grade drive element of the grid is used for driving respectively
On display floater, a corresponding gate line is it is characterised in that described every grade of drive element of the grid includes:
First switch element, including the first path terminal, the first control end, alternate path end, described first path terminal receives first
Pulse signal, described first control end receives the first transmission signal, and described alternate path end is the outfan of this grade of transmission signal；
Second switch element, including third path end, the second control end, fourth passage end, described third path end receives first
Clock signal, described second control end is connected with the described alternate path end of described first switch element, and passes through the first electric capacity
It is connected with described fourth passage end, described fourth passage end is the outfan of every grade of drive element of the grid；
3rd switch element, including fifth passage end, the 3rd control end, clematis stem terminal, described fifth passage end and described the
The described alternate path end of one switch element is connected, and described 3rd control end receives the second transmission signal, and clematis stem terminal receives
Second pulse signal；
4th switch element, including the 7th path terminal, the 4th control end, the 8th path terminal, described 7th path terminal and described the
The described fourth passage end of two switch elements is connected, and described 8th path terminal receives low reference voltage；
5th switch element, including the 9th path terminal, the 5th control end, the tenth path terminal, described 9th path terminal and described the
Described second control end of two switch elements is connected, the 4th control end phase of described 5th control end and described 4th switch element
Even, described tenth path terminal receives described low reference voltage；
6th switch element, including the 11st path terminal, the 6th control end, the 12nd path terminal, described 11st path termination
Receive described first clock signal, described 6th control end is connected with described 11st path terminal, the 12nd path terminal and described the
Described 5th control end of five switch elements is connected；
7th switch element, including the tenth threeway terminal, the 7th control end, the 14th path terminal, described tenth threeway terminal and
Described 7th control end is all connected with described 5th control end of described 5th switch element, and described 14th path terminal receives institute
State low reference voltage；
8th switch element, including the 15th path terminal, the 8th control end, the tenth clematis stem terminal, described 15th path terminal with
Described 5th control end of described 5th switch element is connected, and described the of described 8th control end and described second switch element
Two control ends are connected, and described tenth clematis stem terminal receives described low reference voltage；
9th switch element, including the 17th path terminal, the 9th control end, the 18th path terminal, described 17th path terminal with
Described 5th control end of described 5th switch element is connected, described 9th control end reception second clock signal, and the described tenth
Eight path terminal receive described low reference voltage；And
Tenth switch element, including the 19th path terminal, the tenth control end, the 20th path terminal, described 19th path terminal with
The described fourth passage end of described second switch element is connected, and described tenth control end receives described second clock signal, described
20th path terminal receives described low reference voltage.
2. gate driver circuit as claimed in claim 1 is it is characterised in that described first electric capacity is described second switch element
Described fourth passage end and described second control end between parasitic capacitance.
3. gate driver circuit as claimed in claim 1 it is characterised in that described second switch element described second control
It is provided with separate storage electric capacity, described first electric capacity is the described of described second switch element between end and described fourth passage end
Parasitic capacitance between fourth passage end and described second control end and described separate storage electric capacity sum.
4. gate driver circuit as claimed in claim 1 is it is characterised in that described first the opening of n-th grade of drive element of the grid
The described first transmission signal closing the described first control end reception of element is to differ two-stage upwards with n-th grade of drive element of the grid
Drive element of the grid output upper two-stage transmission signal, wherein, n is integer, and n >=3.
If 5. gate driver circuit as claimed in claim 1 is it is characterised in that described gate driver circuit includes n level grid
Driver element, then described the second of the described 3rd control end reception of described 3rd switch element of n-th grade of drive element of the grid
Transmission signal is the lower two-stage transmission signal of the drive element of the grid output differing downwards two-stage with n-th grade of drive element of the grid, n
≤n-2.
6. gate driver circuit as claimed in claim 1 is it is characterised in that described first the opening of n-th grade of drive element of the grid
Described first pulse signal closing the described first path terminal reception of element is to differ one-level upwards with n-th grade of drive element of the grid
Drive element of the grid output upper level gate drive signal, wherein, n is integer, and n >=2.
If 7. gate driver circuit as claimed in claim 1 is it is characterised in that described gate driver circuit includes n level grid
Driver element, then described the second of the described clematis stem terminal reception of described 3rd switch element of n-th grade of drive element of the grid
Pulse signal is the next stage raster data model letter of the drive element of the grid output differing downwards one-level with n-th grade of drive element of the grid
Number, wherein, n is integer, and 0≤n≤n-1.
8. gate driver circuit as claimed in claim 1 is it is characterised in that described first clock signal and described second clock
Signal is inversion signal.
9. gate driver circuit as claimed in claim 1 it is characterised in that described 6th switch element breadth length ratio be more than or
Breadth length ratio equal to described 7th switch element.
10. a kind of display device is it is characterised in that include gate driver circuit as claimed in any one of claims 1 to 9 wherein.
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| CN105118456B (en) * | 2015-08-31 | 2017-11-03 | 昆山龙腾光电有限公司 | A kind of gate driving circuit and the display device with the gate driving circuit |
| CN105185341B (en) * | 2015-10-09 | 2017-12-15 | 昆山龙腾光电有限公司 | A kind of gate driving circuit and use its display device |
| CN105390086B (en) * | 2015-12-17 | 2018-03-02 | 武汉华星光电技术有限公司 | Gate driving circuit and the display using gate driving circuit |
| CN105355187B (en) * | 2015-12-22 | 2018-03-06 | 武汉华星光电技术有限公司 | GOA circuits based on LTPS semiconductor thin-film transistors |
| CN106601201B (en) * | 2016-12-09 | 2019-06-11 | 昆山龙腾光电有限公司 | Gate driving circuit |
| CN106782366B (en) * | 2016-12-15 | 2018-09-25 | 武汉华星光电技术有限公司 | A kind of gate driving circuit and its driving method, display device |
| CN106782365B (en) * | 2016-12-15 | 2019-05-03 | 武汉华星光电技术有限公司 | A kind of gate driving circuit and driving method, display device |
| TWI614757B (en) * | 2017-07-06 | 2018-02-11 | 友達光電股份有限公司 | Shift register |
| CN107689219A (en) * | 2017-09-12 | 2018-02-13 | 昆山龙腾光电有限公司 | Gate driving circuit and its display device |
| CN108447448B (en) * | 2018-01-19 | 2020-10-30 | 昆山国显光电有限公司 | Scanning drive circuit, scanning driver and display device |
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| CN102800292A (en) * | 2012-08-21 | 2012-11-28 | 昆山龙腾光电有限公司 | Gate driving circuit |
| CN102945651A (en) * | 2012-10-31 | 2013-02-27 | 京东方科技集团股份有限公司 | Shift register, grid driving circuit and display device |
| CN103151013A (en) * | 2013-03-07 | 2013-06-12 | 昆山龙腾光电有限公司 | Gate drive circuit |
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| KR100698239B1 (en) * | 2000-08-30 | 2007-03-21 | 엘지.필립스 엘시디 주식회사 | Shift Register Circuit |
| JP4501048B2 (en) * | 2000-12-28 | 2010-07-14 | カシオ計算機株式会社 | Shift register circuit, drive control method thereof, display drive device, and read drive device |
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| CN102800292A (en) * | 2012-08-21 | 2012-11-28 | 昆山龙腾光电有限公司 | Gate driving circuit |
| CN102945651A (en) * | 2012-10-31 | 2013-02-27 | 京东方科技集团股份有限公司 | Shift register, grid driving circuit and display device |
| CN103151013A (en) * | 2013-03-07 | 2013-06-12 | 昆山龙腾光电有限公司 | Gate drive circuit |
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Address after: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee after: InfoVision Optoelectronics(Kunshan)Co.,Ltd. Address before: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee before: INFOVISION OPTOELECTRONICS (KUNSHAN) Co.,Ltd. |