CN104715095A

CN104715095A - Graphical clock quality detecting and analyzing method

Info

Publication number: CN104715095A
Application number: CN201310689859.3A
Authority: CN
Inventors: 汪燕芳; 董森华; 刘毅; 牛飞飞
Original assignee: Beijing CEC Huada Electronic Design Co Ltd
Current assignee: Beijing Empyrean Technology Co Ltd
Priority date: 2013-12-17
Filing date: 2013-12-17
Publication date: 2015-06-17
Anticipated expiration: 2033-12-17
Also published as: CN104715095B

Abstract

As a clock system structure of a large-scale integrated circuit becomes more complex day by day, and how to fast find the key problem affecting the clock quality in the clock designing and synthesizing processes and shorten the clock designing and synthesizing convergence period becomes a focus problem which the clock industry pays close attention to. According to the graphical clock quality detecting and analyzing method, problems existing in current clock design are fast detected through a simple key, a detection result is displayed through a graphical window, and therefore the complexity of analyzing the problems by design engineers is greatly reduced; in a detailed result analyzing window, characteristic structures of the existing problems are displayed graphically, and an error structure definition, the influence on a whole clock system and how to optimize the error structure are briefly explained; generation of a character report corresponding to the detection result is supported, and therefore communication between the front-end design engineers and the rear-end design engineers is greatly facilitated.

Description

A kind of graphical clock quality detects the method analyzed

Technical field

Graphical clock quality determination method is the existing problems in a kind of automatic detection clock circuit of eda tool in Clock Design, clock combined process, and graphic software platform affects the key feature structure of clock quality, and provides the method for prioritization scheme.The invention belongs to EDA design field.

Background technology

Along with the expansion of integrated circuit (IC) design scale and the increasingly sophisticated of technique, require more and more higher to clock signal control circuit, back-end physical design has to depend on EDA(electric design automation) instrument auxiliary.Clock signal controls the work of all lock units in circuit, and along with hypervelocity, low-power consumption, high performance integrated circuit development, the scale of clock circuit and complexity are also increasing, and in Clock Design and clock combined process, convergent cycle is more and more longer.How to ensure the correctness of Clock System Design, improve the Performance And Reliability of clock system, shorten convergent cycle and become design bottleneck problem.

A usual timing topology comprises clock defining point, combinatorial logic unit (such as gate controlled clock unit), lock unit (such as flip-flop element) etc.Carry out data-signal transmission by combinatorial logic unit between lock unit, carry out latches data when effective jumping edge or the significant level of clock signal.

When clock system is more and more huger, clock-driven lock unit gets more and more, and mutual sequential relationship and clock relation of interdependence also become increasingly complex, and the factor affecting clock control system quality also gets more and more.The difficulty that deviser analyzed and found out design defect in Clock Design process is also increasing.How simply read clock structure and mutual relationship, how to give prominence to the design feature expressing clock, how to find out fast in present clock design and affect clock control system quality critical problem place, shorten the comprehensive convergent cycle of Clock Design, all become the focal issue that industry is paid close attention to.Current existing instrument cannot carry out effectively clock system, the analysis of system, finds out key issue structure, and represents in-problem circuit structure by patterned way, proposes prioritization scheme.

Therefore we have proposed a kind of method here: graphical clock quality detects the method analyzed, its clear displaying present clock system architecture, there is provided one-touch express-analysis for deviser and find design defect, and sort according to problem severity, so that quick solution problem, thus improve the quality of clock tree synthesis, ensure that the timing closure of chip.

Summary of the invention

The present invention proposes a kind of method of one-touch automatic detection clock system quality, the key structure that may affect clock control quality existed in this method automatic analysis present clock system, use a window, a button can detect analysis fast, finds out key issue place; And these problems are represented by patterned way, the comprehensive graphic structure from local to entirety is provided.

Basic thought: for a complicated clock system, in Clock Design and clock combined process, various problem can be there is.Existing eda tool provides a variety of analysis reports of clock system, but is difficult in deviser from numerous analysis report, learn the key issue that present clock system exists.Therefore we propose a kind of method of one-touch automatic detection analysis timing topology, provide clear user interface simple to operate, can detect fast and show its subject matter existed in a window.

Fig. 1 is the entrance automatically detected, and only needs a button just can find out the various problems existed in Clock Design.Simple and clear interface, solves the difficulty that deviser does not know from what analyzing to search problem.Concrete analysis result such as Fig. 2 shows, and sorts according to the significance level affected clock quality, makes more easily to find bottleneck key issue.In each type error entry, concrete problem can be checked in detail, analyze its concrete structure, which kind of impact be caused on timing topology and proposes prioritization scheme.Fig. 3 shows the analysis result of a certain class problem, and wherein left side tree lists all this kind of problems existed in current design; The right the first half figure shows the clock syndeton chosen; The latter half respectively on the definition of current structure, on the impact of whole timing topology and how to revise and optimize this structure and give brief description and guidance (as shown in Fig. 5).

In order to better understand analysis result, we provide feature structure schematic diagram in order to explain current structure, as shown in Fig. 4.In order to allow deviser definitely this problem at the particular location of whole clock system, be supported in the structure that in clock figure module, highlighted display is current.Carry out Search and Orientation for the ease of the clock system structure in complexity, the highlighted Presentation Function of check result of keyword query and validity, reliability also supported by window.As shown in Figure 7, which classification mistake all right configuration detection option of user, such as, detect, detect which clock etc.

Except graphical analysis result, this testing result can also be preserved with word report form, as shown in Figure 6.This also greatly facilitates the communication between Front-end Design slip-stick artist and rear end design engineer.

Accompanying drawing explanation

Fig. 1 automatic checkout system main window

Fig. 2 testing result sorts according to quality influence significance level

Fig. 3 detailed results analysis window

A kind of wrong structure of Fig. 4 graphic definition

Fig. 5 is to the brief description of wrong structure

Fig. 6 testing result word is reported

Fig. 7 configuration detection option window

concrete implementation step:

Illustrate that graphical clock quality detects the method analyzed in conjunction with a concrete example, operating process step is as follows:

1) circuit unit library file is prepared, the circuit meshwork list file of record annexation, the file of definition clock and delay constraint;

2) eda tool is opened, display clock detection system main window as shown in Figure 1, wherein comprised three main merit functional areas: Diagnosis/ Schematic/ detects button automatically;

3) click detection button automatically to start to detect present clock system, result is such as shown in Fig. 2;

4) the result button of concrete a certain class mistake or warning is clicked, the interpretation of result window that display Fig. 3 is detailed;

5) at interpretation of result window, the figure Shape definition that Demo button shows such problem of Fig. 4 is clicked;

6) at the right lower quadrant of interpretation of result window, respectively on the definition of current problem, brief description has been made on clock system impact and corresponding prioritization scheme, as shown in Figure 5;

This testing result is preserved with word report form, as shown in Figure 6.

Claims

1. graphical clock quality detects the method analyzed, and the principal character relating to EDA design tool is:

(1) institute in clock system is automatically detected by a button wrong;

(2) sort according to erroneous effects significance level in a window, analyze all problems existed in present clock design;

(3) in detailed results analysis window, the similar mistake in finding present clock to design, and with the feature structure of patterned way display mistake;

(4) in detailed results analysis window, graphic definition illustrates wrong structure, sets forth the impact of this structure on clock system, and provides optimal solution;

(5) report of corresponding word is produced to analysis result.

2. there is the combination of feature (1), (2), (3).

3. there is the combination of feature (3), (4).

4. there is the combination of feature (1), (3), (4), (5).