CN104702228A - Amplifying system and method with output regulation - Google Patents

Amplifying system and method with output regulation Download PDF

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Publication number
CN104702228A
CN104702228A CN201510114573.1A CN201510114573A CN104702228A CN 104702228 A CN104702228 A CN 104702228A CN 201510114573 A CN201510114573 A CN 201510114573A CN 104702228 A CN104702228 A CN 104702228A
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signal
input signal
output
ramp
input
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CN201510114573.1A
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CN104702228B (en
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袁廷志
陈子斌
方烈义
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On Bright Electronics Shanghai Co Ltd
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On Bright Electronics Shanghai Co Ltd
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Priority to CN201510114573.1A priority Critical patent/CN104702228B/en
Priority to US14/678,136 priority patent/US9685919B2/en
Priority to TW104117212A priority patent/TWI581560B/en
Publication of CN104702228A publication Critical patent/CN104702228A/en
Priority to US15/418,313 priority patent/US10505507B2/en
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Publication of CN104702228B publication Critical patent/CN104702228B/en
Priority to US16/661,906 priority patent/US10951186B2/en
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/181—Low-frequency amplifiers, e.g. audio preamplifiers
    • H03F3/183—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only
    • H03F3/185—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H03F3/2171—Class D power amplifiers; Switching amplifiers with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H03F3/2175—Class D power amplifiers; Switching amplifiers using analogue-digital or digital-analogue conversion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/20—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F2203/21—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F2203/211—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H03F2203/21106—An input signal being distributed in parallel over the inputs of a plurality of power amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/20—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F2203/21—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F2203/211—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H03F2203/21112—A filter circuit being added at the input of a power amplifier stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/20—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F2203/21—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F2203/211—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H03F2203/21145—Output signals are combined by switching a plurality of paralleled power amplifiers to a common output

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Multimedia (AREA)
  • Amplifiers (AREA)

Abstract

The invention provides an amplifying system and method with output regulation. The system and method are used for amplifying multiple input signals so as to generate multiple output signals. The system comprises a first channel configured to receive the first input signal and the second input signal and generate the first output signal and the second output signal based on the first input signal and the second input signal at least partially; and a second channel configured to receive the third input signal and the fourth input signal and generate the third output signal and the fourth output signal based on the third input signal and the fourth input signal at least partially. The first differential signal is equal to the first input signal minus the second input signal. The second differential signal is equal to the third input signal minus the fourth input signal. The first output signal corresponds to the first phase.

Description

There is amplification system and the method for Drazin inverse
Technical field
Some embodiment of the present invention relates to integrated circuit.More specifically, some embodiments of the present invention provide the system and method for Drazin inverse.Only exemplarily, some embodiments of the present invention are applied to amplification system.But it should be understood that the present invention has the scope of application widely.
Background technology
Fig. 1 shows and uses the conventional diagram of the simplification with the amplification system of the class-D amplifier of a channel.Amplification system 100 comprises: modulator 102, output stage 104, low pass filter 106 and output loading 116.Modulator 102 comprises: oscillator 108, comparator 110 and loop filter 112.Such as, output loading 116 is loud speakers.In another example, modulator 102, output stage 104 and low pass filter 106 are included in class-D amplifier.In another example, low pass filter 106 comprises one or more inductor and/or one or more capacitor.In another example, low pass filter 106 comprises one or more pearl core (bead core) and/or one or more capacitor.
Loop filter 112 receives input audio signal 118 and output signal 120 (such as, pulse-width signal), and the signal 122 through filtering is outputted to comparator 110.Such as, input audio signal 118 comprises pair of input signals.Oscillator 108 generated clock signal 126 (CLK) and ramp signal 124 (RAMP), ramp signal 124 is received by comparator 110.Comparator 110 exports the comparison signal 128 of instruction ramp signal 124 and the comparison between the signal 122 of filtering.Output stage 104 receives comparison signal 128 and generating output signal 120 (PWM OUT).Output signal 120 is converted to audio signal 130 to drive load 116 by low pass filter 106.As shown in Figure 1, the single channel comprising modulator 102 and output stage 104 is achieved.Multiple channel can be used to audio frequency and amplify application.
In one embodiment, the error signal between input signal 118 and the feedback signal be associated with output signal 120 is amplified by loop filter 112.Such as, loop filter 112 is included in low-frequency range and has very high-gain (such as, being greater than the high-gain of 1000) and the low pass filter at high-frequency range with very low gain (such as, being far smaller than the low gain of 1).In another example, if signal comprises low frequency component and high fdrequency component, then loop filter 112 amplifies low frequency component by high-gain, and amplifies high fdrequency component with low gain (such as, being far smaller than the low gain of 1).In another example, if high fdrequency component is close to the switching frequency of amplification system 100, then loop filter 112 makes high fdrequency component weaken.In one embodiment, loop filter 112 comprises one or more analogue integrator level.
Fig. 2 is the conventional diagram of simplification of the amplification system with multiple channel.Amplification system 200 comprises multiple channel 202 1..., 202 n..., 202 n, wherein N>=2 and 1≤n≤N.First channel 202 1comprise: loop filter 204 1, comparator 206 1with 208 1, logic controller 210 1, driven unit 212 1with 214 1, transistor 216 1, 218 1, 220 1with 222 1, and low pass filter 224 1.Logic controller 210 1comprise one or more buffer.Such as, low pass filter 224 1comprise one or more inductor and/or one or more capacitor.In another example, low pass filter 224 1comprise one or more pearl core and/or one or more capacitor.Other channels have the assembly similar with the first channel.As shown in Figure 2, these channels 202 1..., 202 n..., 202 nshare common ramp signal 228 and generating output signal (such as, 234 1..., 234 n..., 234 nand/or 236 1..., 236 n..., 236 n), make audio signal be supplied to output loading 222 1..., 222 n..., 222 n(such as, loud speaker).
In one embodiment, loop filter 204 1error signal between input differential signal and the feedback differential signal be associated with output difference sub-signal is amplified.Input differential signal represents input signal 230 1with 232 1between difference, and output difference sub-signal represents output signal 234 1with 236 1between difference.Such as, loop filter 204 1be low pass filter, and it have very high-gain (such as, being greater than the high-gain of 1000) and have very low gain (such as, being far smaller than the low gain of 1) at high-frequency range in low-frequency range.In another example, if signal comprises low frequency component and high fdrequency component, then loop filter 204 1amplify low frequency component by high-gain, and amplify high fdrequency component with low gain (such as, being far smaller than the low gain of 1).In another example, if high fdrequency component is close to the switching frequency of amplification system 200, then loop filter 204 1high fdrequency component is weakened.In one embodiment, loop filter 204 1comprise one or more analogue integrator level.In certain embodiments, the loop filter in other channels and loop filter 204 1identical.
Fig. 3 is the conventional diagram of simplification of the amplification system comprising two channels.Amplification system 1700 comprises two channels 1702 1with 1702 2.First channel 1702 1comprise: loop filter 1704 1, comparator 1706 1with 1708 1, logic controller 1710 1, driven unit 1712 1with 1714 1, transistor 1716 1, 1718 1, 1720 1with 1722 1, and low pass filter 1724 1.Logic controller 1710 1comprise one or more buffer.Such as, low pass filter 1724 1comprise one or more inductor and/or one or more capacitor.In another example, low pass filter 1724 1comprise one or more pearl core and/or one or more capacitor.Second channel 1702 2there is the assembly similar with the first channel.As shown in Figure 3, these two channels 1702 1with 1702 2share common ramp signal 1728 (RAMP) and generating output signal (such as, 1734 1, 1734 2and/or 1736 1, 1736 2), make audio signal be supplied to output loading 1722 1with 1722 2(such as, loud speaker).
Such as, loop filter 1704 1error signal between input differential signal and the feedback differential signal be associated with output difference sub-signal is amplified.Input differential signal represents input signal 1730 1with 1732 1between difference, and output difference sub-signal represents output signal 1734 1with 1736 1between difference.Such as, loop filter 1704 1be low pass filter, and it have very high-gain (such as, being greater than the high-gain of 1000) and have very low gain (such as, being far smaller than the low gain of 1) at high-frequency range in low-frequency range.In another example, if signal comprises low frequency component and high fdrequency component, then loop filter 1704 1amplify low frequency component by high-gain, and amplify high fdrequency component with low gain (such as, being far smaller than the low gain of 1).In another example, if high fdrequency component is close to the switching frequency of amplification system 1700, then loop filter 1704 1high fdrequency component is weakened.In one embodiment, loop filter 1704 1comprise one or more analogue integrator level.In certain embodiments, loop filter 1704 2with loop filter 1704 1identical.
Fig. 4 (a) is when channel 1702 1with 1702 2the conventional sequential chart of simplification of the amplification system 1700 of input differential signal when being equal to 0 volt.Waveform 2802 is by channel 1702 1input differential signal be expressed as the function of time, waveform 2804 will output signal 1736 1be expressed as the function of time, waveform 2806 will output signal 1734 1be expressed as the function of time, waveform 2808 is by channel 1702 2input differential signal be expressed as the function of time, waveform 2810 will output signal 1736 2be expressed as the function of time, and waveform 2812 will output signal 1734 2be expressed as the function of time.Such as, channel 1702 1with 1702 2input differential signal be equal to 0 volt and show input signal 1730 1with 1732 1identical, and input signal 1730 2with 1732 2identical.
Fig. 4 (b) is when channel 1702 1with 1702 2input differential signal identical and all higher than the conventional sequential chart of simplification of the amplification system 1700 when 0 volt.Waveform 2820 is by channel 1702 1input differential signal be expressed as the function of time, waveform 2822 will output signal 1736 1be expressed as the function of time, waveform 2824 will output signal 1734 1be expressed as the function of time, waveform 2826 is by channel 1702 2input differential signal be expressed as the function of time, waveform 2828 will output signal 1736 2be expressed as the function of time, and waveform 2829 will output signal 1734 2be expressed as the function of time.Such as, channel 1702 1input differential signal show input signal 1730 higher than 0 volt 1higher than input signal 1732 1.In another example, channel 1702 2input differential signal show input signal 1730 higher than 0 volt 2higher than input signal 1732 2.
Fig. 4 (c) is when channel 1702 1with 1702 2input differential signal identical and all lower than the conventional sequential chart of simplification of the amplification system 1700 when 0 volt.Waveform 2830 is by channel 1702 1input differential signal be expressed as the function of time, waveform 2832 will output signal 1736 1be expressed as the function of time, waveform 2834 will output signal 1734 1be expressed as the function of time, waveform 2836 is by channel 1702 2input differential signal be expressed as the function of time, waveform 2838 will output signal 1736 2be expressed as the function of time, waveform 2840 will output signal 1734 2be expressed as the function of time.Such as, channel 1702 1input differential signal show input signal 1730 lower than 0 volt 1lower than input signal 1732 1.In another example, channel 1702 2input differential signal show input signal 1730 lower than 0 volt 2lower than input signal 1732 2.
As shown in Fig. 4 (a), Fig. 4 (b) and/or Fig. 4 (c), in response to for channel 1702 1with 1702 2identical input differential signal, output signal 1734 1with 1734 2there is roughly the same phase place, and output signal 1736 1with 1736 2there is roughly the same phase place.
Amplification system 100,200 and 1700 often has some drawback.Therefore be starved of and improve such amplification system.
Summary of the invention
Some embodiment of the present invention relates to integrated circuit.More specifically, some embodiments of the present invention provide the system and method for Drazin inverse.Only exemplarily, some embodiments of the present invention are applied to amplification system.But it should be understood that the present invention has the scope of application widely.
According to an embodiment, a kind ofly to comprise with the system generating multiple output signal for amplifying multiple input signal: the first channel, second channel and the 3rd channel.First channel is configured to receive one or more first input signal, process the information that is associated with this one or more first input signal and the first ramp signal, and at least generate one or more first based on the information be associated with this one or more first input signal and the first ramp signal and output signal.Second channel is configured to receive one or more second input signal, process the information that is associated with this one or more second input signal and the second ramp signal, and at least generate one or more second based on the information be associated with this one or more second input signal and the second ramp signal and output signal.3rd channel is configured to receive one or more 3rd input signal, process the information be associated with this one or more 3rd input signal and the 3rd ramp signal, and at least generate one or more 3rd output signal based on the information be associated with this one or more 3rd input signal and the 3rd ramp signal.First ramp signal corresponds to first phase.Second ramp signal corresponds to second phase.First phase is different from second phase.
According to another embodiment, a kind ofly to comprise with the system generating multiple output signal for amplifying multiple input signal: the first channel and second channel.First channel is configured to receive one or more first input signal, process the information that is associated with this one or more first input signal and the first ramp signal, and at least generate one or more first based on the information be associated with this one or more first input signal and the first ramp signal and output signal.Second channel is configured to receive one or more second input signal, process the information that is associated with this one or more second input signal and the second ramp signal, and at least generate one or more second based on the information be associated with this one or more second input signal and the second ramp signal and output signal.First ramp signal corresponds to first phase.Second ramp signal corresponds to second phase.Difference between first phase and second phase equals 180 degree.
According to another embodiment, a kind ofly to comprise with the system generating multiple output signal for amplifying multiple input signal: the first channel and second channel.First channel comprises first ring path filter, the first signal processing component and the first output precision, and be configured to receive one or more first input signal, process the information that is associated with this one or more first input signal and ramp signal, and at least generate one or more first based on the information be associated with this one or more first input signal and ramp signal and output signal.Second channel comprises the second loop filter, secondary signal processing components and the second output precision, and be configured to receive one or more second input signal, process the information that is associated with this one or more second input signal and ramp signal, and at least generate one or more second based on the information be associated with this one or more second input signal and ramp signal and output signal.First ring path filter is configured to process the information that is associated with one or more first input signal, and at least generates one or more first through the signal of filtering based on the information be associated with one or more first input signal.First signal processing component is configured to process and the one or more first information joined through the signal correction of filtering, and at least generates one or more first treated signal based on the information joined through the signal correction of filtering with one or more first.First output precision is configured to process the information joined with one or more first treated signal correction, and at least generates one or more first based on the information joined with one or more first treated signal correction and output signal.Second loop filter is configured to process the information that is associated with one or more second input signal, and at least generates one or more second through the signal of filtering based on the information be associated with one or more second input signal.Secondary signal processing components is configured to process and the one or more second information joined through the signal correction of filtering, and at least generates one or more second treated signal based on the information joined through the signal correction of filtering with one or more second.Second output precision is configured to process the information joined with one or more second treated signal correction, and at least generates one or more second based on the information joined with one or more second treated signal correction and output signal.One or more first treated signal is associated with first phase.One or more second treated signal is associated with second phase.Difference between first phase and second phase equals 180 degree.
In one embodiment, a kind ofly to comprise with the system generating multiple output signal for amplifying multiple input signal: the first channel and second channel.First channel comprises first ring path filter and one or more first comparator, and be configured to receive one or more first input signal, process the information that is associated with this one or more first input signal and ramp signal, and at least generate one or more first based on the information be associated with this one or more first input signal and ramp signal and output signal.Second channel comprises the second loop filter and one or more second comparator, and be configured to receive one or more second input signal, process the information that is associated with this one or more second input signal and ramp signal, and at least generate one or more second based on the information be associated with this one or more second input signal and ramp signal and output signal.First ring path filter is configured to process the information that is associated with one or more first input signal, and at least generates one or more first through the signal of filtering based on the information be associated with one or more first input signal.One or more first comparator comprises one or more first end and one or more second end, and be configured in first end reception one or more first through the signal of filtering and at the second termination receipts ramp signal, and at least generate one or more first comparison signal based on the information be associated through signal and the ramp signal of filtering with first, and export this one or more first comparison signal to generate one or more first output signal.Second loop filter is configured to process the information that is associated with one or more second input signal, and at least generates one or more second through the signal of filtering based on the information be associated with one or more second input signal.One or more second comparator comprises one or more 3rd end and one or more 4th end, and be configured in the 3rd termination receipts one or more second through the signal of filtering and at the 4th termination receipts ramp signal, and at least generate one or more second comparison signal based on the information be associated through signal and the ramp signal of filtering with second, and export this one or more second comparison signal to generate one or more second output signal.One or more second end comprises one or more end of oppisite phase, and one or more 4th end comprises one or more non-oppisite phase end, or one or more second end comprises one or more non-oppisite phase end, and one or more 4th end comprises one or more end of oppisite phase.
In another embodiment, a kind ofly to comprise with the system generating multiple output signal for amplifying multiple input signal: oscillator assembly, it is configured to generate the ramp signal be associated with ramp frequency; Loop filter components, it is configured to receive one or more input signal and at least generate one or more signal through filtering based on the information be associated with this one or more input signal; And comparator component, it is configured to receive this one or more signal through filtering and ramp signal, and at least generates one or more comparison signal based on the information be associated with this one or more signal through filtering and ramp signal.Oscillator assembly is also configured to: periodic variation ramp frequency, makes the one or more changes produced in each shake cycle corresponding to chattering frequency in ramp frequency, and exports the ramp signal be associated with the ramp frequency through changing.Chattering frequency is greater than the upper limit of predetermined audio frequency range.
In another embodiment, a kind ofly to comprise with the system generating multiple output signal for amplifying multiple input signal: oscillator assembly, it is configured to generate the ramp signal be associated with ramp frequency, and this ramp frequency is corresponding to one or more ramp cycle; Loop filter components, it is configured to receive one or more input signal and at least generate one or more signal through filtering based on the information be associated with this one or more input signal; And comparator component, it is configured to receive this one or more signal through filtering and ramp signal, and at least generates one or more comparison signal based on the information be associated with this one or more signal through filtering and ramp signal.Oscillator assembly is also configured to: at the end of the first ramp cycle, change charging current or discharging current, makes the second duration of ensuing second ramp cycle of the first duration of the first ramp cycle and the first ramp cycle different.First duration and the second duration correspond to the different values of ramp frequency.
According to an embodiment, a kind ofly to comprise with the method generating multiple output signal for amplifying multiple input signal: receive one or more first input signal; Process the information be associated with this one or more first input signal and the first ramp signal; And at least generate one or more first based on the information be associated with this one or more first input signal and the first ramp signal and output signal.The method also comprises: receive one or more second input signal; Process the information be associated with this one or more second input signal and the second ramp signal; And at least generate one or more second based on the information be associated with this one or more second input signal and the second ramp signal and output signal.In addition, the method comprises: receive one or more 3rd input signal; Process the information be associated with this one or more 3rd input signal and the 3rd ramp signal; And at least generate one or more 3rd output signal based on the information be associated with this one or more 3rd input signal and the 3rd ramp signal.First ramp signal corresponds to first phase.Second ramp signal corresponds to second phase.First phase is different from second phase.
According to another embodiment, a kind ofly to comprise with the method generating multiple output signal for amplifying multiple input signal: receive one or more first input signal; Process the information be associated with this one or more first input signal and the first ramp signal; And at least generate one or more first based on the information be associated with this one or more first input signal and the first ramp signal and output signal.The method also comprises: receive one or more second input signal; Process the information be associated with this one or more second input signal and the second ramp signal; And at least generate one or more second based on the information be associated with this one or more second input signal and the second ramp signal and output signal.First ramp signal corresponds to first phase.Second ramp signal corresponds to second phase.Difference between first phase and second phase equals 180 degree.
According to another embodiment, a kind ofly to comprise with the method generating multiple output signal for amplifying multiple input signal: receive one or more first input letter by the first channel comprising first ring path filter, the first signal processing component and the first output precision; Process the information be associated with this one or more first input signal and ramp signal; And at least generate one or more first based on the information be associated with this one or more first input signal and ramp signal and output signal.The method also comprises: receive one or more second input signal by the second channel comprising the second loop filter, secondary signal processing components and the second output precision; Process the information be associated with this one or more second input signal and ramp signal; And at least generate one or more second based on the information be associated with this one or more second input signal and ramp signal and output signal.Process the information be associated with one or more first input signal and ramp signal to comprise: the information be associated with one or more first input signal by the process of first ring path filter; At least generate one or more first through the signal of filtering based on the information be associated with one or more first input signal; By the first signal processing component process and the one or more first information joined through the signal correction of filtering; And at least generate one or more first treated signal based on the information joined through the signal correction of filtering with one or more first.At least generate one or more first based on the information be associated with one or more first input signal and ramp signal to output signal and comprise: the information joined by the first output precision process and one or more first treated signal correction, and at least generate one or more first based on the information joined with one or more first treated signal correction and output signal.Process the information be associated with one or more second input signal and ramp signal to comprise: the information be associated with one or more second input signal by the second loop filter process; At least generate one or more second through the signal of filtering based on the information be associated with one or more second input signal; By secondary signal processing modules process and the one or more second information joined through the signal correction of filtering; And at least generate one or more second treated signal based on the information joined through the signal correction of filtering with one or more second.At least generate one or more second based on the information be associated with one or more second input signal and ramp signal to output signal and comprise: the information joined by the second output precision process and one or more second treated signal correction, and at least generate one or more second based on the information joined with one or more second treated signal correction and output signal.One or more first treated signal is associated with first phase.One or more second treated signal is associated with second phase, and the difference between first phase and second phase equals 180 degree.
In one embodiment, a kind ofly to comprise with the method generating multiple output signal for amplifying multiple input signal: receive one or more first input signal by the first channel comprising first ring path filter and one or more first comparator; Process the information be associated with this one or more first input signal and ramp signal; And at least generate one or more first based on the information be associated with this one or more first input signal and ramp signal and output signal.The method also comprises: receive one or more second input signal by the second channel comprising the second loop filter and one or more second comparator; Process the information be associated with this one or more second input signal and ramp signal; And at least generate one or more second based on the information be associated with this one or more second input signal and ramp signal and output signal.Process the information that is associated with one or more first input signal and ramp signal to comprise: the information be associated with one or more first input signal in the process of first ring path filter, and at least generate one or more first through the signal of filtering based on the information be associated with one or more first input signal.At least generate one or more first based on the information be associated with one or more first input signal and ramp signal to output signal and comprise: receive one or more first through the signal of filtering by one or more first ends of one or more first comparator; Ramp signal is received by one or more second terminations of one or more first comparator; At least generate one or more first comparison signal based on the information be associated through signal and the ramp signal of filtering with first; Export this one or more first comparison signal; And at least generate one or more first based on the information be associated with this one or more first comparison signal and output signal.Process the information that is associated with one or more second input signal and ramp signal to comprise: the information be associated with one or more second input signal by the second loop filter process, and at least generate one or more second through the signal of filtering based on the information be associated with one or more second input signal.At least generate one or more second based on the information be associated with one or more second input signal and ramp signal to output signal and comprise: receive one or more second through the signal of filtering by one or more 3rd terminations of one or more second comparator; Ramp signal is received by one or more 4th terminations of one or more second comparator; At least generate one or more second comparison signal based on the information be associated through signal and the ramp signal of filtering with second; Export this one or more second comparison signal; And at least generate one or more second based on the information be associated with this one or more second comparison signal and output signal.One or more second end comprises one or more end of oppisite phase, and one or more 4th end comprises one or more non-oppisite phase end, or one or more second end comprises one or more non-oppisite phase end, and one or more 4th end comprises one or more end of oppisite phase.
In another embodiment, a kind ofly to comprise with the method generating multiple output signal for amplifying multiple input signal: generate the ramp signal be associated with ramp frequency; Receive one or more input signal; And process the information be associated with this one or more input signal.The method also comprises: at least generate one or more signal through filtering based on the information be associated with this one or more input signal; Receive this one or more signal through filtering and ramp signal; Process the information be associated with this one or more signal through filtering and ramp signal; And at least generate one or more comparison signal based on the information be associated with this one or more signal through filtering and ramp signal.Generate the ramp signal be associated with ramp frequency to comprise: periodic variation ramp frequency, make the one or more changes produced in each shake cycle corresponding to chattering frequency in ramp frequency, and export the ramp signal be associated with the ramp frequency through changing.Chattering frequency is greater than the upper limit of predetermined audio frequency range.
In another embodiment, a kind ofly to comprise with the method generating multiple output signal for amplifying multiple input signal: generate the ramp signal be associated with ramp frequency, this ramp frequency is corresponding to one or more ramp cycle; Receive one or more input signal; And process the information be associated with this one or more input signal.The method also comprises: at least generate one or more signal through filtering based on the information be associated with this one or more input signal; Receive this one or more signal through filtering and ramp signal; And at least generate one or more comparison signal based on the information be associated with this one or more signal through filtering and ramp signal.Generate the ramp signal be associated with ramp frequency to comprise: at the end of the first ramp cycle, change charging current or discharging current, make the second duration of ensuing second ramp cycle of the first duration of the first ramp cycle and the first ramp cycle different.First duration and the second duration correspond to the different values of ramp frequency.
According to an embodiment, comprise with the system generating multiple output signal for amplifying multiple input signal: first channel, it is configured to reception first input signal and the second input signal and generates the first output signal and second based on the first input signal and the second input signal at least partly output signal; And second channel, it is configured to reception the 3rd input signal and the 4th input signal and generates the 3rd output signal and the 4th output signal based on the 3rd input signal and the 4th input signal at least partly.First differential signal equals the first input signal and deducts the second input signal.Second differential signal equals the 3rd input signal and deducts the 4th input signal.First output signal corresponds to first phase.Second output signal corresponds to second phase.3rd output signal corresponds to third phase.4th output signal corresponds to the 4th phase place.First-phase potential difference equals first phase and deducts third phase.Second-phase potential difference equals second phase and deducts the 4th phase place.First differential signal is identical with the second differential signal.First-phase potential difference is not equal to 0.Second-phase potential difference is not equal to 0.First-phase potential difference is identical with second-phase potential difference.
According to another embodiment, a kind ofly to comprise with the system generating multiple output signal for amplifying multiple input signal: the first channel, it is configured to receive one or more first input signal, and generates one or more first output signal based on this one or more first input signal at least partly; And second channel, it is configured to receive one or more second input signal, and generates one or more second output signal based on this one or more second input signal at least partly.The first differential signal be associated with one or more first input signal equals the second differential signal be associated with one or more second input signal.One or more first output signal corresponds to one or more first phase.One or more second output signal corresponds to one or more second phase.Each of one or more differences between one or more first phase and corresponding one or more second phase is equal to 180 °.
According to another embodiment, comprise with the system generating multiple output signal for amplifying multiple input signal: first channel, it is configured to reception first input signal and the second input signal and generates the first output signal and second based on the first input signal and the second input signal at least partly output signal; And second channel, it is configured to reception the 3rd input signal and the 4th input signal and generates the 3rd output signal and the 4th output signal based on the 3rd input signal and the 4th input signal at least partly.First differential signal equals the first input signal and deducts the second input signal.Second differential signal equals the 3rd input signal and deducts the 4th input signal.When the first output signal and the second output signal are all corresponding to the first logic level, when the 3rd output signal and the 4th output signal are all corresponding to the second logic level, the second logic level is different from the first logic level.
In one embodiment, a kind ofly to comprise with the method generating multiple output signal for amplifying multiple input signal: receive the first input signal and the second input signal; The first output signal and the second output signal is generated at least partly based on the first input signal and the second input signal; Receive the 3rd input signal and the 4th input signal; And generate the 3rd output signal and the 4th output signal based on the 3rd input signal and the 4th input signal at least partly.First differential signal equals the first input signal and deducts the second input signal.Second differential signal equals the 3rd input signal and deducts the 4th input signal.First output signal corresponds to first phase.Second output signal corresponds to second phase.3rd output signal corresponds to third phase.4th output signal corresponds to the 4th phase place.First-phase potential difference equals first phase and deducts third phase.Second-phase potential difference equals second phase and deducts the 4th phase place.First differential signal is identical with the second differential signal.First-phase potential difference is not equal to 0.Second-phase potential difference is not equal to 0.First-phase potential difference is identical with second-phase potential difference.
In another embodiment, a kind ofly to comprise with the method generating multiple output signal for amplifying multiple input signal: receive one or more first input signal; One or more first output signal is generated at least partly based on this one or more first input signal; Receive one or more second input signal; And generate one or more second output signal based on this one or more second input signal at least partly.The first differential signal be associated with one or more first input signal equals the second differential signal be associated with one or more second input signal.One or more first output signal corresponds to one or more first phase.One or more second output signal corresponds to one or more second phase.Each of one or more differences between one or more first phase and corresponding one or more second phase is equal to 180 °.
In another embodiment, a kind ofly to comprise with the method generating multiple output signal for amplifying multiple input signal: receive the first input signal and the second input signal; The first output signal and the second output signal is generated at least partly based on the first input signal and the second input signal; Receive the 3rd input signal and the 4th input signal; The 3rd output signal and the 4th output signal is generated at least partly based on the 3rd input signal and the 4th input signal.First differential signal equals the first input signal and deducts the second input signal.Second differential signal equals the 3rd input signal and deducts the 4th input signal.When the first output signal and the second output signal are all corresponding to the first logic level, when the 3rd output signal and the 4th output signal are all corresponding to the second logic level, the second logic level is different from the first logic level.
Based on embodiment, one or more beneficial effect can be realized.These beneficial effects of the present invention and various additional object, feature and advantage can be understood all sidedly with reference to following specific descriptions and accompanying drawing.
Accompanying drawing explanation
Fig. 1 shows and uses the conventional diagram of the simplification with the amplification system of the class-D amplifier of a channel.
Fig. 2 is the conventional diagram of simplification of the amplification system with multiple channel.
Fig. 3 is the conventional diagram of simplification of the amplification system with two channels.
Fig. 4 (a) is the conventional sequential chart of simplification of the amplification system shown in Fig. 3 when the input differential signal of two channels is equal to 0 volt.
Fig. 4 (b) is when the input differential signal of two channels is identical and all higher than the conventional sequential chart of simplification of the amplification system shown in Fig. 3 when 0 volt.
Fig. 4 (c) is when the input differential signal of two channels is identical and all lower than the conventional sequential chart of simplification of the amplification system shown in Fig. 3 when 0 volt.
Fig. 5 is the reduced graph of the amplification system according to an embodiment of the invention with multiple channel.
Fig. 6 is the simplified timing diagram of the amplification system according to an embodiment of the invention shown in Fig. 5.
Fig. 7 (a) is according to embodiments of the invention, shows the reduced graph of the amplification system with two channels.
Fig. 7 (b) is according to another embodiment of the present invention, shows the reduced graph of the amplification system with two channels.
Fig. 7 (c) is according to still another embodiment of the invention, shows the reduced graph of the amplification system with two channels.
Fig. 8 is the reduced graph of amplification system according to an embodiment of the invention.
Fig. 9 is according to embodiments of the invention, as the amplification system shown in Fig. 8 a part, the simplified timing diagram of the oscillator with dither cycle.
Figure 10 (a) is according to one embodiment of present invention, show as the amplification system shown in Fig. 8 a part, the reduced graph of some assembly of the oscillator with dither cycle.
Figure 10 (b) is according to one embodiment of present invention, as amplification system a part, the simplified timing diagram of oscillator as shown in Figure 10 (a).
Figure 10 (c) is according to another embodiment of the present invention, show as the amplification system shown in Fig. 8 a part, the reduced graph of some assembly of the oscillator with dither cycle.
Figure 11 is according to one embodiment of present invention, comprise the oscillator with dither cycle and receive one or more input signal, the simplified timing diagram of amplification system as shown in Figure 8.
Figure 12 is according to another embodiment of the present invention, shows the simplification spectrogram of the dither cycle of the oscillator of the part as the amplification system shown in Fig. 8 and the combination of pseudo-random dither.
Figure 13 is according to one embodiment of present invention, when input signal is 0, comprise the oscillator of the combination with dither cycle and pseudo-random dither, the simplification spectrogram of amplification system as shown in Figure 8.
Figure 14 (a) is according to one embodiment of present invention, show as the amplification system shown in Fig. 8 a part, the reduced graph of some assembly of the oscillator of the combination with dither cycle and pseudo-random dither.
Figure 14 (b) is according to another embodiment of the present invention, show as the amplification system shown in Fig. 8 a part, the reduced graph of some assembly of the oscillator of the combination with dither cycle and pseudo-random dither.
Figure 15 is the reduced graph with the amplification system of two channels according to an embodiment of the invention.
Figure 16 is according to one embodiment of present invention, when the input differential signal of two channels is equal to 0 volt, and the simplified timing diagram of amplification system as shown in figure 15.
Figure 17 (a) is according to some embodiments of the present invention, the reduced graph of a part for this channel when input differential signal shown when a channel equals 0 volt, and Figure 17 (b) is according to some embodiments of the present invention, the reduced graph of a part for this channel when input differential signal shown when one other channel equals 0 volt.
Figure 18 is according to one embodiment of present invention, when the input differential signal of two channels identical and all higher than 0 volt time, the simplified timing diagram of amplification system as shown in figure 15.
Figure 19 (a)-Figure 22 (b) is according to some embodiments of the present invention, show input differential signal when two channels identical and all higher than 0 volt time, during Different periods, the reduced graph of a part for two channels as shown in figure 15.
Figure 23 is according to one embodiment of present invention, when the input differential signal of two channels identical and all lower than 0 volt time, the simplified timing diagram of amplification system as shown in figure 15.
Figure 24 (a)-Figure 27 (b) is according to some embodiments of the present invention, show input differential signal when two channels identical and all lower than 0 volt time, during Different periods, the reduced graph of a part for two channels as shown in figure 15.
Embodiment
Some embodiment of the present invention relates to integrated circuit.More specifically, some embodiments of the present invention provide the system and method for Drazin inverse.Only exemplarily, some embodiments of the present invention are applied to amplification system.But it should be understood that the present invention has the scope of application widely.
With reference to figure 2, because multiple channel receives common ramp signal, therefore output signal (such as, 234 1..., 234 n..., 234 nand/or 236 1..., 236 n..., 236 n) identical frequency can be had and there is identical phase place.That is, all power stages can be switched in the roughly the same time and turn off, and this often causes large fluctuation to the power supply being applied to amplification system 200.
Fig. 5 is the reduced graph of the amplification system according to an embodiment of the invention with multiple channel.This figure is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.Amplification system 300 comprises multiple channel 302 1..., 302 n..., 302 n, wherein N>=2 and 1≤n≤N.
Exemplarily, the first channel 302 1comprise: loop filter 304 1, comparator 306 1with 308 1, logic controller 310 1, driven unit 312 1with 314 1, transistor 316 1, 318 1, 320 1with 322 1, and low pass filter 324 1.According to some embodiment, other channels have the assembly similar with the first channel.Such as, transistor 316 1, 318 1, 320 1with 322 1it is N-channel transistor.Exemplarily, logic controller 310 1comprise one or more buffer.In another example, low pass filter 324 1comprise one or more inductor and/or one or more capacitor.In another example, low pass filter 324 1comprise one or more pearl core and/or one or more capacitor.In one embodiment, loop filter 304 1error signal between input differential signal and the feedback differential signal be associated with output difference sub-signal is amplified.Input differential signal represents input signal 332 1with 330 1between difference, and output difference sub-signal represents output signal 334 1with 336 1between difference.Such as, loop filter 304 1be included in low-frequency range and there is very high-gain (such as, being greater than the high-gain of 1000) and the low pass filter at high-frequency range with very low gain (such as, being far smaller than the low gain of 1).In another example, if signal comprises low frequency component and high fdrequency component, then loop filter 304 1amplify low frequency component by high-gain, and amplify high fdrequency component with low gain (such as, being far smaller than the low gain of 1).In another example, if high fdrequency component is close to the switching frequency of amplification system 300, then loop filter 304 1high fdrequency component is weakened.In one embodiment, loop filter 304 1comprise one or more analogue integrator level.
According to some embodiments, the ramp signal (such as, 328 received by different channels 1..., 328 n) there is identical frequency but different phase places.In one embodiment, the phase shift between the ramp signal received by different channels is equal.Exemplarily, the first channel 302 1receive ramp signal 328 1(VRAMP1) for the treatment of input signal 330 1with 332 1.In another embodiment, second channel 302 2(not shown in Fig. 5) receives ramp signal 328 2, and ramp signal 328 2with ramp signal 328 1between phase shift be by the 3rd channel 302 3the ramp signal 328 that (not shown in Fig. 5) receives 3with ramp signal 328 1between phase shift be and by last channel 302 nthe ramp signal 328 received n(VRAMPN) with ramp signal 328 1between phase shift be in another embodiment, the phase shift between the ramp signal received by different channels is different.Exemplarily, the first channel 302 1with second channel 302 2between phase shift and second channel 302 2with the 3rd channel 302 3between phase shift different.
Fig. 6 is the simplified timing diagram of amplification system 300 according to an embodiment of the invention.This figure is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.Waveform 402 1by ramp signal 328 1be expressed as the function of time, waveform 402 2by ramp signal 328 2be expressed as the function of time, waveform 402 3by ramp signal 328 3be expressed as the function of time, and waveform 402 nby ramp signal 328 nbe expressed as the function of time.As shown in Figure 6, according to some embodiment, ramp signal 328 1with ramp signal 328 2between phase shift be ramp signal 328 2with ramp signal 328 3between phase shift be and ramp signal 328 1with ramp signal 328 nbetween phase shift be such as, phase shift equal or be not equal to phase shift
Fig. 7 (a) is according to embodiments of the invention, shows the reduced graph of the amplification system with two channels.This figure is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.Amplification system 500 comprises: loop filter 502 and 504, comparator 506,508,510 and 512, logic controller 514 and 516, driven unit 518,520,522 and 524, transistor 526,528,530,532,534,536,538 and 540, and low pass filter 542 and 544.Such as, amplification system 500 is amplification systems 300 that N equals 2.
In one embodiment, loop filter 502, comparator 506 and 508, logic controller 514, driven unit 518 and 520, transistor 526,528,530 and 532, and low pass filter 542 is included in the first channel.In another embodiment, loop filter 504, comparator 510 and 512, logic controller 516, driven unit 522 and 524, transistor 534,536,538 and 540, and low pass filter 544 is included in second channel.Logic controller 514 comprises two buffers 550 and 552, and logic controller 516 comprises two buffers 554 and 556.In certain embodiments, transistor 526,528,530,532,534,536,538 and 540 is N-channel transistor, such as, and n channel metal oxide semiconductor field effect transistor (MOSFET).In certain embodiments, transistor 526,530,534 and 538 is p channel transistor (such as, P channel mosfet), and transistor 528,532,536 and 540 is N-channel transistor (such as, N-channel MOS FET).Exemplarily, each of low pass filter 542 and 544 comprises one or more inductor and/or one or more capacitor.In another example, each of low pass filter 542 and 544 comprises one or more pearl core and/or one or more capacitor.
In another example, loop filter 502, comparator 506 and 508, logic controller 514, driven unit 518 and 520, transistor 526,528,530 and 532, and low pass filter 542 respectively with loop filter 304 1, comparator 306 1with 308 1, logic controller 310 1, driven unit 312 1with 314 1, transistor 316 1, 318 1, 320 1with 322 1, and low pass filter 324 1identical.In another example, loop filter 504, comparator 510 and 512, logic controller 516, driven unit 522 and 524, transistor 534,536,538 and 540, and low pass filter 544 respectively with loop filter 304 1, comparator 306 1with 308 1, logic controller 310 1, driven unit 312 1with 314 1, transistor 316 1, 318 1, 320 1with 322 1, and low pass filter 324 1identical.
According to an embodiment, first channel receives input signal 560 and 562 and ramp signal 568 (RAMP1), and generating output signal 572 and 574 is to provide one or more audio signal 580 to output loading 546 (such as, loud speaker).Especially, such as, loop filter 502 receives input signal 560 and 562, and generates the signal 584 and 586 through filtering, and the signal 584 and 586 through filtering is received by comparator 506 and 508 respectively.Exemplarily, comparator 506 and 508 also receives ramp signal 568 and generates comparison signal 588 and 590 respectively.Signal 596 and 598 is outputted to driven unit 518 and 520 by logic controller 514 respectively.Such as, loop filter 502 receives the output signal 572 and 574 as feedback.In one example, if comparison signal 588 is in logic high, then signal 596 is in logic high, and if comparison signal 588 is in logic low, then signal 596 is in logic low.In another example, if comparison signal 590 is in logic high, then signal 598 is in logic high, and if comparison signal 590 is in logic low, then signal 598 is in logic low.
According to another embodiment, second channel receives input signal 564 and 566 and ramp signal 570 (RAMP2), and generating output signal 576 and 578 is to provide one or more audio signal 582 to output loading 548 (such as, loud speaker).Especially, such as, loop filter 504 receives input signal 564 and 566, and generates the signal 588 and 590 through filtering, and the signal 588 and 590 through filtering is received by comparator 510 and 512 respectively.Exemplarily, comparator 510 and 512 also receives ramp signal 570 and generates comparison signal 592 and 594 respectively.Signal 597 and 599 is outputted to driven unit 522 and 524 by logic controller 516 respectively.Such as, loop filter 504 receives the output signal 576 and 578 as feedback.In one example, if comparison signal 592 is in logic high, then signal 597 is in logic high, and if comparison signal 592 is in logic low, then signal 597 is in logic low.In another example, if comparison signal 594 is in logic high, then signal 599 is in logic high, and if comparison signal 594 is in logic low, then signal 599 is in logic low.
Exemplarily, ramp signal 568 and 570 has identical frequency, and the phase shift between ramp signal 568 and ramp signal 570 is π (such as, 180 °).That is, ramp signal 568 is anti-phase with ramp signal 570.
In one embodiment, the error signal between input differential signal and the feedback differential signal be associated with output difference sub-signal is amplified by loop filter 502.Input differential signal represents the difference between input signal 560 and 562, and output difference sub-signal represents the difference between output signal 572 and 574.Such as, loop filter 502 is low pass filters, and it has very high-gain (such as, being greater than the high-gain of 1000) and have very low gain (such as, being far smaller than the low gain of 1) at high-frequency range in low-frequency range.In another example, if signal comprises low frequency component and high fdrequency component, then loop filter 502 amplifies low frequency component by high-gain, and amplifies high fdrequency component with low gain (such as, being far smaller than the low gain of 1).In another example, if high fdrequency component is close to the switching frequency of amplification system 500, then loop filter 502 makes high fdrequency component weaken.In one embodiment, loop filter 502 comprises one or more analogue integrator level.In certain embodiments, loop filter 504 is identical with loop filter 502.
Fig. 7 (b) is according to another embodiment of the present invention, shows the reduced graph of the amplification system with two channels.This figure is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.Amplification system 600 comprises: loop filter 602 and 604, comparator 606,608,610 and 612, logic controller 614 and 616, driven unit 618,620,622 and 624, transistor 626,628,630,632,634,636,638 and 640, and low pass filter 642 and 644.
In one embodiment, loop filter 602, comparator 606 and 608, logic controller 614, driven unit 618 and 620, transistor 626,628,630 and 632, and low pass filter 642 is included in the first channel.In another embodiment, loop filter 604, comparator 610 and 612, logic controller 616, driven unit 622 and 624, transistor 634,636,638 and 640, and low pass filter 644 is included in second channel.Logic controller 614 comprises two buffers 650 and 652, and logic controller 616 comprises two not gates 654 and 656.In certain embodiments, transistor 626,628,630,632,634,636,638 and 640 is N-channel transistor, such as, and N-channel MOS FET.In certain embodiments, transistor 626,630,634 and 638 is p channel transistor (such as, P channel mosfet), and transistor 628,632,636 and 640 is N-channel transistor (such as, N-channel MOS FET).Exemplarily, each of low pass filter 642 and 644 comprises one or more inductor and/or one or more capacitor.In another example, each of low pass filter 642 and 644 comprises one or more pearl core and/or one or more capacitor.In another example, loop filter 602, comparator 606 and 608, logic controller 614, driven unit 618 and 620, transistor 626,628,630 and 632, and low pass filter 642 respectively with loop filter 304 1, comparator 306 1with 308 1, logic controller 310 1, driven unit 312 1with 314 1, transistor 316 1, 318 1, 320 1with 322 1, and low pass filter 324 1identical.In another example, loop filter 604, comparator 610 and 612 respectively with loop filter 3041, comparator 306 1with 308 1identical.
According to an embodiment, first channel receives input signal 660 and 662 and ramp signal 668 (RAMP), and generating output signal 672 and 674 is to provide one or more audio signal 680 to output loading 646 (such as, loud speaker).Especially, such as, loop filter 602 receives input signal 660 and 662 and the output signal 672 and 674 as feedback, and generates the signal 684 and 686 through filtering, and the signal 684 and 686 through filtering is received by comparator 606 and 608 respectively.Exemplarily, comparator 606 and 608 also receives ramp signal 668 and generates comparison signal 688 and 690 respectively.Signal 696 and 698 is outputted to driven unit 618 and 620 by logic controller 614 respectively.Such as, if comparison signal 688 is in logic high, then signal 696 is in logic high, and if comparison signal 688 is in logic low, then signal 696 is in logic low.In another example, if comparison signal 690 is in logic high, then signal 698 is in logic high, and if comparison signal 690 is in logic low, then signal 698 is in logic low.In certain embodiments, logic controller 614 is removed, and signal 688 is identical with 698 with signal 696 respectively with 690.Such as, each of comparator 606,608,610 and 612 receives ramp signal 668 at non-oppisite phase end (such as, "+" end).In another example, each of comparator 606,608,610 and 612 receives ramp signal 668 at end of oppisite phase (such as, "-" end).
According to another embodiment, second channel receives input signal 664 and 666 and ramp signal 668, and generating output signal 676 and 678 is to provide one or more audio signal 682 to output loading 648 (such as, loud speaker).Especially, such as, loop filter 604 receives input signal 664 and 666 and the output signal 676 and 678 as feedback, and generates the signal 688 and 690 through filtering, and the signal 688 and 690 through filtering is received by comparator 610 and 612 respectively.Exemplarily, comparator 610 and 612 also receives ramp signal 668 and generates comparison signal 692 and 694 respectively.Signal 697 and 699 is outputted to driven unit 622 and 624 by logic controller 616 respectively.Such as, if comparison signal 692 is in logic high, then signal 697 is in logic low, and if comparison signal 692 is in logic low, then signal 697 is in logic high.In another example, if comparison signal 694 is in logic high, then signal 599 is in logic low, and if comparison signal 694 is in logic low, then signal 699 is in logic high.In another example, comparator 606 is at end of oppisite phase (such as, "-" end) Received signal strength 684; Comparator 608 is at end of oppisite phase (such as, "-" end) Received signal strength 686; Comparator 610 is at end of oppisite phase (such as, "-" end) Received signal strength 688; And comparator 612 is at end of oppisite phase (such as, "-" end) Received signal strength 690.
In one embodiment, the error signal between input differential signal and the feedback differential signal be associated with output difference sub-signal is amplified by loop filter 602.Input differential signal represents the difference between input signal 660 and 662, and output difference sub-signal represents the difference between output signal 672 and 674.Such as, loop filter 602 is low pass filters, and it has very high-gain (such as, being greater than the high-gain of 1000) and have very low gain (such as, being far smaller than the low gain of 1) at high-frequency range in low-frequency range.In another example, if signal comprises low frequency component and high fdrequency component, then loop filter 602 amplifies low frequency component by high-gain, and amplifies high fdrequency component with low gain (such as, being far smaller than the low gain of 1).In another example, if high fdrequency component is close to the switching frequency of amplification system 600, then loop filter 602 makes high fdrequency component weaken.In one embodiment, loop filter 602 comprises one or more analogue integrator level.In certain embodiments, loop filter 604 is identical with loop filter 602.
Fig. 7 (c) is according to still another embodiment of the invention, shows the reduced graph of the amplification system with two channels.This figure is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.Amplification system 1600 comprises: loop filter 1602 and 1604, comparator 1606,1608,1610 and 1612, logic controller 1614 and 1616, driven unit 1618,1620,1622 and 1624, transistor 1626,1628,1630,1632,1634,1636,1638 and 1640, and low pass filter 1642 and 1644.
In one embodiment, loop filter 1602, comparator 1606 and 1608, logic controller 1614, driven unit 1618 and 1620, transistor 1626,1628,1630 and 1632, and low pass filter 1642 is included in the first channel.In another embodiment, loop filter 1604, comparator 1610 and 1612, logic controller 1616, driven unit 1622 and 1624, transistor 1634,1636,1638 and 1640, and low pass filter 1644 is included in second channel.Logic controller 1614 comprises two buffers 1650 and 1652, and logic controller 1616 comprises two buffers 1654 and 1656.In certain embodiments, transistor 1626,1628,1630,1632,1634,1636,1638 and 1640 is N-channel transistor, such as, and N-channel MOS FET.In certain embodiments, transistor 1626,1630,1634 and 1638 is p channel transistor (such as, P channel mosfet), and transistor 1628,1632,1636 and 1640 is N-channel transistor (such as, N-channel MOS FET).Exemplarily, each of low pass filter 1642 and 1644 comprises one or more inductor and/or one or more capacitor.In another example, each of low pass filter 1642 and 1644 comprises one or more pearl core and/or one or more capacitor.In another example, loop filter 1602, comparator 1606 and 1608, logic controller 1614, driven unit 1618 and 1620, transistor 1626,1628,1630 and 1632, and low pass filter 1642 respectively with loop filter 304 1, comparator 306 1with 308 1, logic controller 310 1, driven unit 312 1with 314 1, transistor 316 1, 318 1, 320 1with 322 1, and low pass filter 324 1identical.In another example, loop filter 1604, comparator 1610 and 1612 respectively with loop filter 304 1, comparator 306 1with 308 1identical.
According to an embodiment, first channel receives input signal 1660 and 1662 and ramp signal 1668 (RAMP), and generating output signal 1672 and 1674 is to provide one or more audio signal 1680 to output loading 1646 (such as, loud speaker).Especially, such as, loop filter 1602 receives input signal 1660 and 1662 and the output signal 1672 and 1674 as feedback, and generates the signal 1684 and 1686 through filtering, and the signal 1684 and 1686 through filtering is received by comparator 1606 and 1608 respectively.Exemplarily, comparator 1606 and 1608 also receives ramp signal 1668 and generates comparison signal 1688 and 1690 respectively.Signal 1696 and 1698 is outputted to driven unit 1618 and 1620 by logic controller 1614 respectively.Such as, if comparison signal 1688 is in logic high, then signal 1696 is in logic high, and if comparison signal 1688 is in logic low, then signal 1696 is in logic low.In another example, if comparison signal 1690 is in logic high, then signal 1698 is in logic high, and if comparison signal 1690 is in logic low, then signal 1698 is in logic low.In certain embodiments, logic controller 1614 is removed, and signal 1688 is identical with 1698 with signal 1696 respectively with 1690.In certain embodiments, logic controller 1616 is removed, and signal 1692 is identical with 1699 with signal 1697 respectively with 1694.Such as, each of comparator 1610 and 1612 receives ramp signal 1668 at non-oppisite phase end (such as, "+" holds), and each of comparator 1606 and 1608 receives ramp signal 1668 at end of oppisite phase (such as, "-" end).
According to another embodiment, second channel receives input signal 1664 and 1666 and ramp signal 1668, and generating output signal 1676 and 1678 is to provide one or more audio signal 1682 to output loading 1648 (such as, loud speaker).Especially, such as, loop filter 1604 receives input signal 1664 and 1666 and the output signal 1676 and 1678 as feedback, and generates the signal 1688 and 1690 through filtering, and the signal 1688 and 1690 through filtering is received by comparator 1610 and 1612 respectively.Exemplarily, comparator 1610 and 1612 also receives ramp signal 1668 and generates comparison signal 1692 and 1694 respectively.In another example, signal 1697 and 1699 is outputted to driven unit 1622 and 1624 by logic controller 1616 respectively.In another example, comparator 1606 is at non-oppisite phase end (such as, "+" end) Received signal strength 1684; Comparator 1608 is at non-oppisite phase end (such as, "+" end) Received signal strength 1686; Comparator 1610 is at end of oppisite phase (such as, "-" end) Received signal strength 1688; And comparator 1612 is at end of oppisite phase (such as, "-" end) Received signal strength 1690.
In one embodiment, the error signal between input differential signal and the feedback differential signal be associated with output difference sub-signal is amplified by loop filter 1602.Input differential signal represents the difference between input signal 1660 and 1662, and output difference sub-signal represents the difference between output signal 1672 and 1674.Such as, loop filter 1602 is low pass filters, and it has very high-gain (such as, being greater than the high-gain of 1000) and have very low gain (such as, being far smaller than the low gain of 1) at high-frequency range in low-frequency range.In another example, if signal comprises low frequency component and high fdrequency component, then loop filter 1602 amplifies low frequency component by high-gain, and amplifies high fdrequency component with low gain (such as, being far smaller than the low gain of 1).In another example, if high fdrequency component is close to the switching frequency of amplification system 1600, then loop filter 1602 makes high fdrequency component weaken.In one embodiment, loop filter 1602 comprises one or more analogue integrator level.In certain embodiments, loop filter 1604 is identical with loop filter 1602.
Also here emphasize further as mentioned above, Fig. 5, Fig. 7 (a), Fig. 7 (b) and Fig. 7 (c) are only examples, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.Such as, the phase shift between ramp signal 568 and 570 is not equal to π.In another example, channel 302 1..., 302 neach comprise respective oscillator, be respectively used to generate ramp signal 328 1..., 328 n.In another example, channel 302 1..., 302 nshare common oscillator, this oscillator generates ramp signal 328 1..., 328 n.In another example, each of the channel of two shown in Fig. 7 (a) comprises respective oscillator, is respectively used to generate ramp signal 568 and 570.In another example, the oscillator that the Channel Sharing of two shown in Fig. 7 (a) is common, this oscillator generates ramp signal 568 and 570.
Turn back with reference to figure 2, amplification system 200 often relates to high switching frequency, and to solve electromagnetic interference problem may be important.
Fig. 8 is the reduced graph of amplification system according to an embodiment of the invention.This figure is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.Amplification system 800 comprises: modulator 802, output stage 804, low pass filter 806 and output loading 816.Modulator 802 comprises: loop filter 812, oscillator 808, comparator 810.Such as, output loading 816 is loud speakers.In another example, low pass filter 806 comprises one or more inductor and/or one or more capacitor.In another example, low pass filter 806 comprises one or more pearl core and/or one or more capacitor.In another example, modulator 802, output stage 804 and low pass filter 806 are included in class-D amplifier.
According to an embodiment, loop filter 812 receives input audio signal 818, and the signal 822 through filtering is outputted to comparator 810.Such as, input audio signal 818 comprises pair of input signals.In another example, oscillator 808 generated clock signal 826 and ramp signal 824.Exemplarily, comparator 810 receives ramp signal 824, and comparison signal 828 is supplied to output stage 804, output stage 804 generating output signal 820.In one example, loop filter 812 receives the output signal 820 as feedback.Such as, output signal 820 is converted to audio signal 830 to drive load 816 by low pass filter 806.As shown in Figure 8, according to some embodiment, modulator 802, output stage 804 and low pass filter 806 can be included in a channel of multichannel amplification system.Such as, output signal 820 and comprise one or more signal.In another example, the difference between 820 expressions, two signals is outputed signal.
According to another embodiment, oscillator 808 is configured to provide dither cycle to the frequency of oscillation of clock signal 826 and/or the ramp frequency of ramp signal 824.Such as, the frequency of oscillation of clock signal 826 and/or the ramp frequency of ramp signal 824 change in particular range in response to dither cycle.In another example, the frequency (such as, repetition rate) of dither cycle is greater than the upper limit of audio frequency range (such as, about 20Hz is to about 20KHz).In another example, the frequency of oscillation of clock signal 826 equals the ramp frequency of ramp signal 824.
According to another embodiment, oscillator 808 is configured to the combination providing dither cycle and pseudo-random dither to the frequency of oscillation of clock signal 826 and/or the ramp frequency of ramp signal 824.Such as, the frequency of oscillation of clock signal 826 and/or the ramp frequency of ramp signal 824 in response to dither cycle and pseudo-random dither combination and change in particular range.In another example, the frequency (such as, repetition rate) of pseudo-random dither is less than the lower limit of audio frequency range (such as, about 20Hz is to about 20KHz).
According to another embodiment, ramp signal 824 is associated with one or more ramp cycle, and this ramp cycle is relevant with the ramp frequency of ramp signal 824.Such as, oscillator 808 is configured to ramp signal 824 in adjustment first ramp cycle to affect the slope of ramp signal 824 in next ramp cycle and/or the duration of next ramp cycle.Especially, in certain embodiments, oscillator 808 is configured to change the upward slope slope that is associated with ramp signal 824 and/or descending slope (such as, in a periodic manner or in a pseudo-random fashion).According to some embodiment, the amplification system 800 shown in Fig. 8 can realize improving this one or more channel further in the one or more channels shown in Fig. 3, Fig. 7 (a) and/or Fig. 7 (b).Such as, the combination of dither cycle or dither cycle and pseudo-random dither is provided to one or more channels of the amplification system realizing being similar to amplification system 800.
In one embodiment, the error signal between input signal 818 and the feedback signal be associated with output signal 820 is amplified by loop filter 812.Such as, loop filter 812 is included in low-frequency range and has very high-gain (such as, being greater than the high-gain of 1000) and the low pass filter at high-frequency range with very low gain (such as, being far smaller than the low gain of 1).In another example, if signal comprises low frequency component and high fdrequency component, then loop filter 812 amplifies low frequency component by high-gain, and amplifies high fdrequency component with low gain (such as, being far smaller than the low gain of 1).In another example, if high fdrequency component is close to the switching frequency of amplification system 800, then loop filter 812 makes high fdrequency component weaken.In one embodiment, loop filter 812 comprises one or more analogue integrator level.
Fig. 9 is according to embodiments of the invention, as the simplified timing diagram of the oscillator 808 with dither cycle of a part for amplification system 800.This figure is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.The frequency of oscillation be associated with clock signal 826 and/or the ramp frequency that is associated with the ramp signal 824 of oscillator 808 are expressed as the function of time by waveform 702.Start from t 0and end at t 8shake cycle T 0be shown in Fig. 9.Such as, t 0≤ t 1≤ t 2≤ t 3≤ t 4≤ t 5≤ t 6≤ t 7≤ t 8.
According to an embodiment, multiple frequency step appears at shake cycle T 0in, wherein each frequency step corresponds to specific frequency of oscillation value or specific ramp frequency value.Such as, at t 0with t 1between, frequency of oscillation or ramp frequency have value f 1.Exemplarily, at t 1with t 2between, frequency of oscillation or ramp frequency are increased to another value f 2, then at t 3with t 4between be increased to value f 3.According to some embodiment, at t 4with t 5between, frequency of oscillation or ramp frequency reach shake cycle T 0interior peak value f 4.Exemplarily, at t 5with t 8between, the value of frequency of oscillation or ramp frequency reduces, until shake cycle T 0last, then next shake cycle starts.Such as, frequency values f 1, f 2, f 3, f 4, f 5, f 6and f 7during again appearing at next shake cycle.In another example, the repetition rate (such as, the repetition of jitter sequences) of frequency jitter is inversely proportional to shake cycle T 0.In another example, repetition rate is greater than the upper limit of audio frequency range (such as, about 20Hz is to about 20KHz) in size.Exemplarily, according to some embodiments, the frequency of audio signal 830 is not affected by the frequency jitter shown in Fig. 9.
Figure 10 (a) is according to one embodiment of present invention, shows the reduced graph of some assembly of the oscillator 808 with dither cycle of the part as amplification system 800.This figure is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.Oscillator 808 comprises: jitter sequences generator 902, current source 904 and 906, switch 908 and 910, trsanscondutance amplifier 912, capacitor 916, comparator 914 and 918, NAND gate 920 and 922 and buffer 924.
According to an embodiment, jitter sequences generator 902 receive clock signal 826, and generate signal 930 to trigger the change of the charging current 932 relevant with current source 904 and/or the discharging current 934 relevant with current source 906.Such as, switch 908 is disconnected in response to charging signals 926 or closes, and switch 910 is disconnected in response to discharge signal 928 or close.In one example, if charging signals 926 is in logic high, then discharge signal 928 is in logic low, and if charging signals 926 is in logic low, then discharge signal 928 is in logic high.In another example, clock signal 826 changes between logic high and logic low, is similar to discharge signal 928.Such as, clock signal 826 was associated with one or more cycles of oscillation of the frequency of oscillation corresponding to clock signal 826.In another example, ramp signal 824 is associated with one or more ramp cycle of the ramp frequency corresponding to ramp signal 824.In another example, switch periods equals ramp cycle on the duration.In another example, switch periods and ramp cycle start from synchronization and end at synchronization.In another example, in ramp cycle, ramp signal 824 increased in a period of time in ramp cycle on value, and reduced on value in another a period of time in ramp cycle.
According to another embodiment, jitter sequences generator 902 detects the rising edge of clock signal 826, and generates signal 930 to change charging current 932 and/or discharging current 934, with the ramp frequency shake of the frequency and/or ramp signal 824 that make clock signal 826.Such as, the change of the frequency of oscillation of clock signal 826 and/or the ramp frequency of ramp signal 824 is decided by the value of charging current 932 and/or discharging current 934.In another example, at the rising edge place of clock signal 826, ramp signal 824 reaches the peak value in ramp cycle.In another example, charging current 932 equals discharging current 934 on value.In another example, electric current 932 is equal on value with electric current 934.In another example, for giving the charge cycle of capacitor 916 charging based on ramp signal 824 and reference signal 998 (such as, V rEF+) between relatively decide.In another example, for giving the discharge cycle of capacitor 916 electric discharge based on ramp signal 824 and reference signal 996 (such as, V rEF-) between relatively decide.
Figure 10 (b) is according to one embodiment of present invention, as the simplified timing diagram of the oscillator 808 as shown in Figure 10 (a) of a part for amplification system 800.This figure is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.Clock signal 826 (such as, CLK) is expressed as the function of time by waveform 1006, and waveform 1008 is by ramp signal 824 (such as, V rAMP) be expressed as the function of time.Such as, t 9≤ t 10≤ t 11≤ t 12≤ t 13.
According to an embodiment, as shown in Figure 10 (b), at the first ramp cycle (such as, T n) period, ramp signal 824 from value 1018 (such as, at t 9) be reduced to value 1020 (such as, at t 10), be then increased to value 1022 (such as, at t 11).Such as, at ramp cycle (such as, T n) period, charging current 932 and/or discharging current 934 remain on the first value in particular range (scope such as, between maximum magnitude and minimum value).According to some embodiments, at t 11, the second ramp cycle (such as, T n+1) start, and rising edge 1028 appears in clock signal 826.Such as, jitter sequences generator 902 outputs signal 930 to change charging current 932 and/or discharging current 934, with the ramp frequency shake of the frequency of oscillation and/or ramp signal 824 that make clock signal 826.In another example, in response to the change of charging current 932 and/or discharging current 934, the second ramp cycle (such as, T n+1) in the slope of ramp signal 824 become and the first ramp cycle (such as, T n) in the slope of ramp signal 824 different.In another example, in response to the change of charging current 932 and/or discharging current 934, the second ramp cycle (such as, T n+1) duration become and the first ramp cycle (such as, T n) duration different.In certain embodiments, the change of the slope (such as, upward slope slope and/or descending slope) of ramp signal 824 causes the ramp frequency that is associated with ramp signal 824 and/or the change of frequency of oscillation be associated with clock signal 826.
According to another embodiment, at the second ramp cycle (such as, T n+1) period, ramp signal 824 from value 1022 (such as, at t 11) be reduced to value 1024 (such as, at t 12), be then increased to value 1026 (such as, at t 13).Such as, at the second ramp cycle (such as, T n+1) period, remain on the second value in charging current 932 and/or the scope between discharging current 934 maximum magnitude and minimum value.In another example, the second value is different from the first value.According to some embodiments, at t 13, the 3rd ramp cycle (such as, T n+2) start, and another rising edge 1030 appears in clock signal 826.Such as, jitter sequences generator 902 changes signal 930 to change charging current 932 and/or discharging current 934, with the ramp frequency shake of the frequency of oscillation and/or ramp signal 824 that make clock signal 826.In another example, in response to the change of charging current 932 and/or discharging current 934, the 3rd ramp cycle (such as, T n+2) in the slope of ramp signal 824 become and the second ramp cycle (such as, T n+1) in the slope of ramp signal 824 different.In another example, in response to the change of charging current 932 and/or discharging current 934, the 3rd ramp cycle (such as, T n+2) duration become and the second ramp cycle (such as, T n+1) duration different.In certain embodiments, the change of the slope (such as, upward slope slope and/or descending slope) of ramp signal 824 causes the ramp frequency that is associated with ramp signal 824 and/or the change of frequency of oscillation be associated with clock signal 826.Such as, the value 1018,1022 and 1026 of ramp signal 824 and reference signal 998 (such as, V rEF+) relevant, and the value 1020 and 1024 of ramp signal 824 and reference signal 996 (such as, V rEF-) relevant.
Figure 10 (c) is according to another embodiment of the present invention, shows the reduced graph of some assembly of the oscillator 808 with dither cycle of the part as amplification system 800.This figure is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.Oscillator 808 comprises: current controlled oscillator assembly 1410, encoder 1406, current D-A conveter (DAC) 1408 and counter assembly 1404.Such as, counter assembly 1404, encoder 1406, current DAC 1408 are included in jitter sequences generator 902.In another example, current DAC (such as, current DAC 1408) is included in current source 904 and/or current source 906.In another example, current controlled oscillator assembly 1410 comprises: current source 904 and 906, switch 908 and 910, capacitor 916, amplifier 912, comparator 914 and 918, NAND gate 920 and 922 and buffer 928.
According to an embodiment, counter assembly 1404 receive clock signal 826 also generates signal 1412, and signal 1412 is encoded by encoder 1406.Exemplarily, encoded signal 1414 is received by DAC 1408, and DAC 1408 is by current signal 1416 (such as, I dac2) output to current controlled oscillator assembly 1410.In another example, received current signal 1402 (such as, I gone back by current controlled oscillator assembly 1410 0) and clock signal 826 and ramp signal 824.As shown in Figure 10 (c), counter assembly 1404 changes signal 1412 in response to clock signal 826, with the ramp frequency shake of the frequency of oscillation and/or ramp signal 824 that make clock signal 826.Such as, clock signal 826 is associated with one or more switch periods of the frequency of oscillation corresponding to clock signal 826.In another example, ramp signal 824 is associated with one or more ramp cycle of the ramp frequency corresponding to ramp signal 824.In another example, switch periods equals ramp cycle on the duration.In another example, switch periods and ramp cycle start from synchronization and end at synchronization.In another example, current signal 1402 is fixing.
According to another embodiment, in the beginning of the first switch periods, counter assembly 1404 generates the signal 1412 being in the first value, and is in the first value in response to signal 1412, and current DAC 1408 generates the electric current 1416 being in the first value.Such as, the frequency of oscillation of clock signal 826 and/or the ramp frequency of ramp signal 824 are shaken in response to electric current 1416 is in the first value.In another example, in the beginning in the first switch periods second switch cycle subsequently, counter assembly 1404 generates the signal 1412 being in the second value, and is in the second value in response to signal 1412, and current DAC 1408 generates the electric current 1416 being in the second value.In another example, the frequency of oscillation of clock signal 826 and/or the ramp frequency of ramp signal 824 are shaken again in response to electric current 1416 is in the second value.
According to another embodiment, the ramp frequency of ramp signal 824 is determined as follows:
f = β I 0 + I dac 2 (formula 1)
Wherein β represents constant, I 0represent direct current signal 1402, and I dac2represent signal 1416.
According to some embodiment, if I dac2< < I 0, then the ramp frequency of ramp signal 824 is determined as follows:
f = &beta; I 0 ( 1 - I dac 2 I 0 ) (formula 2)
Based on formula 2, the ramp frequency of ramp signal 824 is modulated by current signal 1416.Such as, charging current 932 and discharging current 934 meet following formula:
I charge=I discharge=I 0+ I dac2(formula 3)
According to another embodiment, receive if do not have input signal to be exaggerated system 800, then the modulation period be associated with output signal 820 (such as, PWM) is determined as follows:
T i , PWM = 1 4 &times; T i - 1 , RAMP + 3 4 &times; T i , RAMP (formula 4)
Wherein T i, PWMrepresent and the current-modulation cycle that output signal 820 is associated, T i-1, RAMPrepresent a upper ramp cycle, and T i, RAMPrepresent current ramp cycle.
According to another embodiment, if amplification system 800 receives one or more input signal, then the duty ratio outputing signal 820 changes, and is determined as follows the modulation period be associated with output signal 820:
T i , PWM = 1 &alpha; &times; T i - 1 , RAMP + &alpha; - 1 &alpha; &times; T i , RAMP (formula 5)
Wherein α represents the positive number be associated with input signal.According to some embodiments, based on formula 5, if α changes with the increase of input signal, then the duty ratio outputing signal 820 increases, and occurs the more multi-frequency value of output signal 820.
Figure 11 is according to one embodiment of present invention, comprises the oscillator 808 with dither cycle and receives the simplified timing diagram of the amplification system 800 of input signal 818.This figure is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.The value of the modulating frequency that the signal 820 (such as, PWM) with amplification system 800 is associated by waveform 1102 is expressed as the function of time.Such as, amplification system 800 comprises the oscillator 808 with dither cycle as shown in Fig. 9, Figure 10 (a), Figure 10 (b) and/or Figure 10 (c).
As shown in figure 11, there are two shake cycle T land T m.According to an embodiment, multiple frequency step appears at shake cycle T land T meach in, wherein each frequency step correspond to particular switch frequency values.But in certain embodiments, shake cycle T lfrequency values with shake cycle T mfrequency values different, and further, appear at shake cycle T 1and T min frequency values different from the frequency values in other shake cycles, as shown in figure 11.According to some embodiments, compared with Fig. 9, by changing charging current 932 and discharging current 934, along with passage of time, there is more multi-frequency value due to the shake of ramp signal 824.
Also here emphasize further as mentioned above, Fig. 9, Figure 10 (a), Figure 10 (b), Figure 10 (c) and Figure 11 are only examples, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.In certain embodiments, jitter sequences generator 902 is outside at oscillator 808.In certain embodiments, counter assembly 1404, encoder 1406 and current DAC 1408 are outside at oscillator 808.Such as, although Fig. 9 and Figure 11 shows dither cycle, dither cycle can be combined with pseudo-random dither, as shown in figure 12.
Figure 12 is according to another embodiment of the present invention, shows the simplification spectrogram of the dither cycle of oscillator 808 as a part for amplification system 800 and the combination of pseudo-random dither.This figure is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.
According to an embodiment, audio frequency range is at frequency values f c1(such as, about 20Hz) and frequency values f c2between (such as, about 20kHz), and the frequency of oscillation of clock signal 826 (such as, f osc) on value, be greater than the upper limit of audio frequency range.Exemplarily, frequency (such as, the f be associated with the dither cycle shown in Fig. 9 and/or Figure 11 j1) on value, be greater than the upper limit of audio frequency range.In another example, frequency (such as, the f be associated with pseudo-random dither j2) on value, be less than the lower limit of audio frequency range.According to some embodiment, the frequency component of audio signal 830 is not affected by dither cycle and/or pseudo-random dither.According to another embodiment, if the frequency values quantity of dither cycle is N j1and the frequency values quantity of pseudo-random dither is N j2, then when without any input signal, the frequency values quantity be associated with output signal 820 is determined as follows:
N total=N j1× N j2(formula 6)
Wherein N totalrepresent and the frequency values quantity that output signal 820 is associated.Such as, if N j1=7 and N j2=16, then N total=112.According to some embodiment, if amplification system 800 receives input signal, then there will be more multi-frequency value, as shown in figure 12.
Figure 13 is according to one embodiment of present invention, shows when input signal 818 is 0, comprises the simplification spectrogram of the amplification system 800 of the oscillator 808 of the combination with dither cycle and pseudo-random dither.This figure is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.The value that signal 820 (such as, PWM) with amplification system 800 is associated is expressed as the function of frequency by waveform 1202.
Figure 14 (a) is according to one embodiment of present invention, shows the reduced graph of some assembly of the oscillator 808 with the combination of dither cycle and pseudo-random dither of the part as amplification system 800.This figure is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.Oscillator 808 comprises: jitter sequences generator 1502, current source 1504 and 1506, switch 1508 and 1510, trsanscondutance amplifier 1512, capacitor 1516, comparator 1514 and 1518, NAND gate 1520 and 1522 and buffer 1524.
According to an embodiment, jitter sequences generator 1502 receive clock signal 826, and generate the change that signal 1530 triggers the charging current 1532 relevant with current source 1504 and/or the discharging current 1534 relevant with current source 1506, to provide the combination of dither cycle and pseudo-random dither to the frequency of oscillation of clock signal 826 and/or the ramp frequency of ramp signal 824.Such as, switch 1508 is disconnected in response to charging signals 1526 or closes, and switch 1510 is disconnected in response to discharge signal 1528 or close.In one example, if charging signals 1526 is in logic high, then discharge signal 1528 is in logic low, and if charging signals 1526 is in logic low, then discharge signal 1528 is in logic high.In another example, clock signal 826 changes between logic high and logic low, is similar to discharge signal 1528.
Figure 14 (b) is according to another embodiment of the present invention, shows the reduced graph of some assembly of the oscillator 808 with the combination of dither cycle and pseudo-random dither of the part as amplification system 800.This figure is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.Oscillator 808 comprises: current controlled oscillator assembly 1302, linear feedback shift register (LFSR) assembly 1304, encoder component 1306 and 1312, current D-A conveter (DAC) 1308 and 1314 and counter assembly 1310.Such as, counter assembly 1310, encoder component 1312, current DAC 1314, LFSR 1304, encoder component 1306 and current DAC 1308 are included in jitter sequences generator 1502.In another example, current DAC (such as, current DAC 1308 or current DAC 1314) is included in current source 1504 and/or current source 1506.In another example, current controlled oscillator assembly 1302 comprises: current source 1504 and 1506, switch 1508 and 1510, capacitor 1516, amplifier 1512, comparator 1514 and 1518, NAND gate 1520 and 1522 and buffer 1528.
According to an embodiment, the LFSR assembly 1304 receive clock signal 826 realized for pseudo-random dither also generates signal 1322, and signal 1322 is encoded by encoder component 1306.Such as, encoded signal 1324 is received by DAC 1308, and DAC 1308 is by current signal 1318 (such as, I dac1) output to current controlled oscillator assembly 1302.In another example, the counter assembly 1310 receive clock signal 826 realized for dither cycle also generates signal 1326, and signal 1326 is encoded by encoder 1312.Exemplarily, encoded signal 1328 is received by DAC1314, and DAC 1314 is by current signal 1320 (such as, I dac2) output to current controlled oscillator assembly 1302.In another example, received current signal 1316 (such as, I gone back by current controlled oscillator assembly 1302 0) and clock signal 826 and ramp signal 824.In another example, current signal 1316 is fixing.
According to another embodiment, the ramp frequency of ramp signal 824 is determined as follows:
f = &beta; I 0 + I dac 1 + I dac 2 (formula 7)
Wherein β represents constant, I 0represent signal 1316, I dac1represent signal 1318, and I dac2represent signal 1320.
According to some embodiment, if I dac1+ I dac2< < I 0, then the ramp frequency of ramp signal 824 is determined as follows:
f = &beta; I 0 ( 1 - I dac 1 + I dac 2 I 0 ) (formula 8)
Based on formula 8, the ramp frequency of ramp signal 824 is modulated by current signal 1318 and 1320.Such as, charging current 932 and discharging current 934 meet following formula:
| I charge|=| I discharge|=| I 0+ I dac1+ dac2| (formula 9)
Also here emphasize further as mentioned above, Figure 14 (a) and Figure 14 (b) is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.In certain embodiments, jitter sequences generator 1502 is outside at oscillator 808.In certain embodiments, counter assembly 1504, encoder 1506 and current DAC 1508 are outside at oscillator 808.
Figure 15 is the reduced graph comprising the amplification system of two channels according to an embodiment of the invention.This figure is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.
Amplification system 1800 comprises two channels 1802 1with 1802 2.First channel 1802 1comprise: loop filter 1804 1, comparator 1806 1with 1808 1, logic controller 1810 1, driven unit 1812 1with 1814 1, transistor 1816 1, 1818 1, 1820 1with 1822 1, phase control assembly 1819 1, and low pass filter 1824 1.Second channel 1802 2comprise: loop filter 1804 2, comparator 1806 2with 1808 2, logic controller 1810 2, driven unit 1812 2with 1814 2, transistor 1816 2, 1818 2, 1820 2with 1822 2, phase control assembly 1819 2, and low pass filter 1824 2.Such as, logic controller 1810 1with 1810 2each comprise one or more buffer.Exemplarily, low pass filter 1824 1with 1824 2each comprise one or more inductor and/or one or more capacitor.In another example, low pass filter 1824 1with 1824 2each comprise one or more pearl core and/or one or more capacitor.
According to some embodiments, as shown in figure 15, two channels 1802 1with 1802 2share common ramp signal 1828.Such as, channel 1802 1generating output signal 1834 1with 1836 1, and channel 1802 2generating output signal 1834 2with 1836 2, make audio signal be supplied to output loading 1826 1with 1826 2(such as, loud speaker).Exemplarily, loop filter 1804 1error signal between input differential signal and the feedback differential signal be associated with output difference sub-signal is amplified.In another example, input differential signal represents input signal 1830 1with 1832 1between difference, and output difference sub-signal represents output signal 1834 1with 1836 1between difference.In another example, loop filter 1804 1be low pass filter, and it have very high-gain (such as, being greater than the high-gain of 1000) and have very low gain (such as, being far smaller than the low gain of 1) at high-frequency range in low-frequency range.In another example, if signal comprises low frequency component and high fdrequency component, then loop filter 1804 1amplify low frequency component by high-gain, and amplify high fdrequency component with low gain (such as, being far smaller than the low gain of 1).In another example, if high fdrequency component is close to the switching frequency of amplification system 1800, then loop filter 1804 1high fdrequency component is weakened.In one embodiment, loop filter 1804 1comprise one or more analogue integrator level.In certain embodiments, loop filter 1804 2with loop filter 1804 1identical.
According to an embodiment, comparison signal 1807 1with 1809 1respectively by comparator 1806 1with 1808 1generate.Such as, phase control assembly 1819 1adjustment comparison signal 1807 1with 1809 1phase place to change output signal 1834 1with 1836 1phase place.Exemplarily, comparison signal 1807 2with 1809 2respectively by comparator 1806 2with 1808 2generate.In another example, phase control assembly 1819 2adjustment comparison signal 1807 2with 1809 2phase place to change output signal 1834 2with 1836 2phase place.According to some embodiments, in response to for channel 1802 1with 1802 2identical input differential signal, these two channels 1802 1with 1802 2output signal (such as, 1834 1, 1834 2, 1836 1, 1836 2) phase place by phase control assembly 1819 1with 1819 2adjust.Such as, 1834 are outputed signal 1with 1834 2between there is phase shift.In another example, 1836 are outputed signal 1with 1836 2between there is phase shift.
Figure 16 is according to one embodiment of present invention, when channel 1802 1with 1802 2the simplified timing diagram of the amplification system 1800 of input differential signal when being equal to 0 volt.This figure is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.Waveform 1902 is by channel 1802 1input differential signal (such as, INN1-INP1) be expressed as the function of time, waveform 1904 will output signal 1836 1(such as, OUTN1) is expressed as the function of time, and waveform 1906 will output signal 1834 1(such as, OUTP1) is expressed as the function of time, and waveform 1908 is by channel 1802 2input differential signal (such as, INN2-INP2) be expressed as the function of time, waveform 1910 will output signal 1836 2(such as, OUTN2) is expressed as the function of time, and waveform 1912 will output signal 1834 2(such as, OUTP2) is expressed as the function of time.Such as, channel 1802 1with 1802 2input differential signal be equal to 0 volt and show input signal 1830 1with 1832 1identical, and input signal 1830 2with 1832 2identical.
According to some embodiments of the present invention, Figure 17 (a) shows when channel 1802 1the channel 1802 of input differential signal when equaling 0 volt 1the reduced graph of a part, and Figure 17 (b) shows when channel 1802 2the channel 1802 of input differential signal when equaling 0 volt 2the reduced graph of a part.This figure is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.Such as, Figure 17 (a) also comprises low pass filter 1824 1, and Figure 17 (b) also comprises low pass filter 1824 2.
According to some embodiments, as shown in figure 16, if channel 1802 1with 1802 2input differential signal be equal to 0 volt, then output signal 1834 1, 1836 1, 1834 2with 1836 2duty ratio approximate 50%.Such as, 1834 are outputed signal 1phase place with output signal 1834 2phase place between difference approximate 180 °.Exemplarily, 1836 are outputed signal 1phase place with output signal 1836 2phase place between difference approximate 180 °.
According to some embodiments, as shown in Figure 17 (a), Figure 17 (b) and Figure 16, at period t 1period, channel 1802 1transistor 1820 1with 1816 1be switched on, and channel 1802 2transistor 1822 2with 1818 2be switched on.Such as, at period t 1period, output signal 1836 1be in logic high (such as, as shown in waveform 1904), and output signal 1834 1be in logic high (such as, as shown in waveform 1906).In another example, at period t 1period, output signal 1836 2be in logic low (such as, as shown in waveform 1910), and output signal 1834 2be in logic low (such as, as shown in waveform 1912).
According to an embodiment, at subsequent period t 2period, channel 1802 1transistor 1822 1with 1818 1be switched on, and channel 1802 2transistor 1820 2with 1816 2be switched on.Such as, at period t 2period, output signal 1836 1be in logic low (such as, as shown in waveform 1904), and output signal 1834 1be in logic low (such as, as shown in waveform 1906).In another example, at period t 2period, output signal 1836 2be in logic high (such as, as shown in waveform 1910), and output signal 1834 2be in logic high (such as, as shown in waveform 1912).In certain embodiments, due to channel 1802 1output signal 1834 1with 1836 1identical, so there is no electric current and flow through output loading 1826 1(such as, loud speaker).In certain embodiments, due to channel 1802 2output signal 1834 2with 1836 2identical, so there is no electric current and flow through output loading 1826 2(such as, loud speaker).
Figure 18 is according to one embodiment of present invention, when channel 1802 1with 1802 2input differential signal identical and all higher than the simplified timing diagram of the amplification system 1800 when 0 volt.This figure is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.Waveform 2002 is by channel 1802 1input differential signal be expressed as the function of time, waveform 2004 will output signal 1836 1be expressed as the function of time, waveform 2006 will output signal 1834 1be expressed as the function of time, waveform 2008 is by channel 1802 2input differential signal be expressed as the function of time, waveform 2010 will output signal 1836 2be expressed as the function of time, and waveform 2012 will output signal 1834 2be expressed as the function of time.Such as, channel 1802 1input differential signal show input signal 1830 higher than 0 volt 1higher than input signal 1832 1.In another example, channel 1802 2input differential signal show input signal 1830 higher than 0 volt 2higher than input signal 1832 2.
According to some embodiments, as shown in figure 18, if channel 1802 1with 1802 2input differential signal identical and all higher than 0 volt, then output signal 1834 1with 1834 2duty ratio be less than 50%, 1836 1with 1836 2duty ratio be greater than 50%.Such as, 1834 are outputed signal 1phase place with output signal 1834 2phase place between difference approximate angle phi.Exemplarily, 1836 are outputed signal 1phase place with output signal 1836 2phase place between difference approximate angle phi.In certain embodiments, if channel 1802 1with 1802 2input differential signal identical and all higher than 0 volt, phase difference equals 180 °.
According to some embodiments of the present invention, Figure 19 (a) shows when channel 1802 1input differential signal higher than 0 volt time, at period t 3period channel 1802 1the reduced graph of a part, and Figure 19 (b) shows when channel 1802 2input differential signal higher than 0 volt time, at period t 3period channel 1802 2the reduced graph of a part.This figure is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.Such as, Figure 19 (a) also comprises low pass filter 1824 1, and Figure 19 (b) also comprises low pass filter 1824 2.
According to some embodiments, as shown in Figure 18, Figure 19 (a) and Figure 19 (b), at period t 3period, channel 1802 1transistor 1820 1with 1818 1be switched on, and channel 1802 2transistor 1820 2with 1818 2be switched on.Such as, at period t 3period, output signal 1836 1be in logic high (such as, as shown in waveform 2004), and output signal 1834 1be in logic low (such as, as shown in waveform 2006).In another example, at period t 3period, output signal 1836 2be in logic high (such as, as shown in waveform 2010), and output signal 1834 2be in logic low (such as, as shown in waveform 2012).In another example, at channel 1802 1in, electric current 2098 1flow through transistor 1820 1, output loading 1826 1(such as, loud speaker) and transistor 1818 1.In another example, at channel 1802 2in, electric current 2098 2flow through transistor 1820 2, output loading 1826 2(such as, loud speaker) and transistor 1818 2.
According to some embodiments of the present invention, Figure 20 (a) shows when channel 1802 1input differential signal higher than 0 volt time, at period t 4period channel 1802 1the reduced graph of a part, and Figure 20 (b) shows when channel 1802 2input differential signal higher than 0 volt time, at period t 4period channel 1802 2the reduced graph of a part.This figure is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.Such as, Figure 20 (a) also comprises low pass filter 1824 1, and Figure 20 (b) also comprises low pass filter 1824 2.
According to some embodiments, as shown in Figure 18, Figure 20 (a) and Figure 20 (b), at period t 4period, channel 1802 1transistor 1820 1with 1816 1be switched on, and channel 1802 2transistor 1822 2with 1818 2be switched on.Such as, at period t 4period, output signal 1836 1be in logic high (such as, as shown in waveform 2004), and output signal 1834 1be in logic high (such as, as shown in waveform 2006).In another example, at period t 4period, output signal 1836 2be in logic low (such as, as shown in waveform 2010), and output signal 1834 2be in logic low (such as, as shown in waveform 2012).In another example, due to output loading 1826 1inductance characteristic, electric current 2096 1flow through channel 1802 1in transistor 1820 1, output loading 1826 1(such as, loud speaker) and transistor 1816 1.In another example, due to output loading 1826 2inductance characteristic, electric current 2096 2flow through channel 1802 2in transistor 1822 2, output loading 1826 2(such as, loud speaker) and transistor 1818 2.
According to some embodiments of the present invention, Figure 21 (a) shows when channel 1802 1input differential signal higher than 0 volt time, at period t 5period channel 1802 1the reduced graph of a part, and Figure 21 (b) shows when channel 1802 2input differential signal higher than 0 volt time, at period t 5period channel 1802 2the reduced graph of a part.This figure is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.Such as, Figure 21 (a) also comprises low pass filter 1824 1, and Figure 21 (b) also comprises low pass filter 1824 2.
According to some embodiments, as shown in Figure 18, Figure 21 (a) and Figure 21 (b), at period t 5period, channel 1802 1transistor 1820 1with 1818 1be switched on, and channel 1802 2transistor 1820 2with 1818 2be switched on.Such as, at period t 5period, output signal 1836 1be in logic high (such as, as shown in waveform 2004), and output signal 1834 1be in logic low (such as, as shown in waveform 2006).In another example, at period t 5period, output signal 1836 2be in logic high (such as, as shown in waveform 2010), and output signal 1834 2be in logic low (such as, as shown in waveform 2012).In another example, at channel 1802 1in, electric current 2094 1flow through transistor 1820 1, output loading 1826 1(such as, loud speaker) and transistor 1818 1.In another example, at channel 1802 2in, electric current 2094 2flow through transistor 1820 2, output loading 1826 2(such as, loud speaker) and transistor 1818 2.
According to some embodiments of the present invention, Figure 22 (a) shows when channel 1802 1input differential signal higher than 0 volt time, at period t 6period channel 1802 1the reduced graph of a part, and Figure 22 (b) shows when channel 1802 2input differential signal higher than 0 volt time, at period t 6period channel 1802 2the reduced graph of a part.This figure is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.Such as, Figure 22 (a) also comprises low pass filter 1824 1, and Figure 22 (b) also comprises low pass filter 1824 2.
According to some embodiments, as shown in Figure 18, Figure 22 (a) and Figure 22 (b), at period t 6period, channel 1802 1transistor 1822 1with 1818 1be switched on, and channel 1802 2transistor 1820 2with 1816 2be switched on.Such as, at period t 6period, output signal 1836 1be in logic low (such as, as shown in waveform 2004), and output signal 1834 1be in logic low (such as, as shown in waveform 2006).In another example, at period t 6period, output signal 1836 2be in logic high (such as, as shown in waveform 2010), and output signal 1834 2be in logic high (such as, as shown in waveform 2012).In another example, due to output loading 1826 1inductance characteristic, electric current 2092 1flow through channel 1802 1in transistor 1822 1, output loading 1826 1(such as, loud speaker) and transistor 1818 1.In another example, due to output loading 1826 2inductance characteristic, electric current 2092 2flow through channel 1802 2in transistor 1820 2, output loading 1826 2(such as, loud speaker) and transistor 1816 2.
Figure 23 is according to one embodiment of present invention, when channel 1802 1with 1802 2input differential signal identical and all lower than the simplified timing diagram of the amplification system 1800 when 0 volt.This figure is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.Waveform 2102 is by channel 1802 1input differential signal be expressed as the function of time, waveform 2104 will output signal 1836 1be expressed as the function of time, waveform 2106 will output signal 1834 1be expressed as the function of time, waveform 2108 is by channel 1802 2input differential signal be expressed as the function of time, waveform 2110 will output signal 1836 2be expressed as the function of time, and waveform 2112 will output signal 1834 2be expressed as the function of time.Such as, channel 1802 1input differential signal show input signal 1830 lower than 0 volt 1lower than input signal 1832 1.In another example, channel 1802 2input differential signal show input signal 1830 lower than 0 volt 2lower than input signal 1832 2.
According to some embodiments, as shown in figure 23, if channel 1802 1with 1802 2input differential signal identical and all lower than 0 volt, then output signal 1834 1with 1834 2duty ratio be greater than 50%, 1836 1with 1836 2duty ratio be less than 50%.Such as, 1834 are outputed signal 1phase place with output signal 1834 2phase place between difference approximate angle phi '.Exemplarily, 1836 are outputed signal 1phase place with output signal 1836 2phase place between difference approximate angle phi '.In certain embodiments, if channel 1802 1with 1802 2input differential signal identical and all lower than 0 volt, phase difference ' equal 180 °.
According to some embodiments of the present invention, Figure 24 (a) shows when channel 1802 1input differential signal lower than 0 volt time, at period t 7period channel 1802 1the reduced graph of a part, and Figure 24 (b) shows when channel 1802 2input differential signal lower than 0 volt time, at period t 7period channel 1802 2the reduced graph of a part.This figure is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.Such as, Figure 24 (a) also comprises low pass filter 1824 1, and Figure 24 (b) also comprises low pass filter 1824 2.
According to some embodiments, as shown in Figure 23, Figure 24 (a) and Figure 24 (b), at period t 7period, channel 1802 1transistor 1822 1with 1816 1be switched on, and channel 1802 2transistor 1822 2with 1816 2be switched on.Such as, at period t 7period, output signal 1836 1be in logic low (such as, as shown in waveform 2104), and output signal 1834 1be in logic high (such as, as shown in waveform 2106).In another example, at period t 7period, output signal 1836 2be in logic low (such as, as shown in waveform 2110), and output signal 1834 2be in logic high (such as, as shown in waveform 2112).In another example, at channel 1802 1in, electric current 2198 1flow through transistor 1816 1, output loading 1826 1(such as, loud speaker) and transistor 1822 1.In another example, at channel 1802 2in, electric current 2198 2flow through transistor 1816 2, output loading 1826 2(such as, loud speaker) and transistor 1822 2.
According to some embodiments of the present invention, Figure 25 (a) shows when channel 1802 1input differential signal lower than 0 volt time, at period t 8period channel 1802 1the reduced graph of a part, and Figure 25 (b) shows when channel 1802 2input differential signal lower than 0 volt time, at period t 8period channel 1802 2the reduced graph of a part.This figure is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.Such as, Figure 25 (a) also comprises low pass filter 1824 1, and Figure 25 (b) also comprises low pass filter 1824 2.
According to some embodiments, as shown in Figure 23, Figure 25 (a) and Figure 25 (b), at period t 8period, channel 1802 1transistor 1820 1with 1816 1be switched on, and channel 1802 2transistor 1822 2with 1818 2be switched on.Such as, at period t 8period, output signal 1836 1be in logic high (such as, as shown in waveform 2104), and output signal 1834 1be in logic high (such as, as shown in waveform 2106).In another example, at period t 8period, output signal 1836 2be in logic low (such as, as shown in waveform 2110), and output signal 1834 2be in logic low (such as, as shown in waveform 2112).In another example, due to output loading 1826 1inductance characteristic, electric current 2196 1flow through channel 1802 1in transistor 1816 1, output loading 1826 1(such as, loud speaker) and transistor 1820 1.In another example, due to output loading 1826 2inductance characteristic, electric current 2196 2flow through channel 1802 2in transistor 1818 2, output loading 1826 2(such as, loud speaker) and transistor 1822 2.
According to some embodiments of the present invention, Figure 26 (a) shows when channel 1802 1input differential signal lower than 0 volt time, at period t 9period channel 1802 1the reduced graph of a part, and Figure 26 (b) shows when channel 1802 2input differential signal lower than 0 volt time, at period t 9period channel 1802 2the reduced graph of a part.This figure is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.Such as, Figure 26 (a) also comprises low pass filter 1824 1, and Figure 26 (b) also comprises low pass filter 1824 2.
According to some embodiments, as shown in Figure 23, Figure 26 (a) and Figure 26 (b), at period t 9period, channel 1802 1transistor 1822 1with 1816 1be switched on, and channel 1802 2transistor 1822 2with 1816 2be switched on.Such as, at period t 9period, output signal 1836 1be in logic low (such as, as shown in waveform 2104), and output signal 1834 1be in logic high (such as, as shown in waveform 2106).In another example, at period t 9period, output signal 1836 2be in logic low (such as, as shown in waveform 2110), and output signal 1834 2be in logic high (such as, as shown in waveform 2112).In another example, at channel 1802 1in, electric current 2194 1flow through transistor 1816 1, output loading 1826 1(such as, loud speaker) and transistor 1822 1.In another example, at channel 1802 2in, electric current 2194 2flow through transistor 1816 2, output loading 1826 2(such as, loud speaker) and transistor 1822 2.
According to some embodiments of the present invention, Figure 27 (a) shows when channel 1802 1input differential signal lower than 0 volt time, at period t 10period channel 1802 1the reduced graph of a part, and Figure 27 (b) shows when channel 1802 2input differential signal lower than 0 volt time, at period t 10period channel 1802 2the reduced graph of a part.This figure is only example, and it exceedingly should not limit the scope of claim.Those of ordinary skill in the art will recognize many changes, substitutions and modifications.Such as, Figure 27 (a) also comprises low pass filter 1824 1, and Figure 27 (b) also comprises low pass filter 1824 2.
According to some embodiments, as shown in Figure 23, Figure 27 (a) and Figure 27 (b), at period t 10period, channel 1802 1transistor 1822 1with 1818 1be switched on, and channel 1802 2transistor 1820 2with 1816 2be switched on.Such as, at period t 10period, output signal 1836 1be in logic low (such as, as shown in waveform 2104), and output signal 1834 1be in logic low (such as, as shown in waveform 2106).In another example, at period t 10period, output signal 1836 2be in logic high (such as, as shown in waveform 2110), and output signal 1834 2be in logic high (such as, as shown in waveform 2112).In another example, due to output loading 1826 1inductance characteristic, electric current 2192 1flow through channel 1802 1in transistor 1818 1, output loading 1826 1(such as, loud speaker) and transistor 1822 1.In another example, due to output loading 1826 2inductance characteristic, electric current 2192 2flow through channel 1802 2in transistor 1816 2, output loading 1826 2(such as, loud speaker) and transistor 1820 2.
According to an embodiment, a kind ofly to comprise with the system generating multiple output signal for amplifying multiple input signal: the first channel, second channel and the 3rd channel.First channel is configured to receive one or more first input signal, process the information that is associated with this one or more first input signal and the first ramp signal, and at least generate one or more first based on the information be associated with this one or more first input signal and the first ramp signal and output signal.Second channel is configured to receive one or more second input signal, process the information that is associated with this one or more second input signal and the second ramp signal, and at least generate one or more second based on the information be associated with this one or more second input signal and the second ramp signal and output signal.3rd channel is configured to receive one or more 3rd input signal, process the information be associated with this one or more 3rd input signal and the 3rd ramp signal, and at least generate one or more 3rd output signal based on the information be associated with this one or more 3rd input signal and the 3rd ramp signal.First ramp signal corresponds to first phase.Second ramp signal corresponds to second phase.First phase is different from second phase.Such as, this system at least realizes according to Fig. 5 and/or Fig. 6.
According to another embodiment, a kind ofly to comprise with the system generating multiple output signal for amplifying multiple input signal: the first channel and second channel.First channel is configured to receive one or more first input signal, process the information that is associated with this one or more first input signal and the first ramp signal, and at least generate one or more first based on the information be associated with this one or more first input signal and the first ramp signal and output signal.Second channel is configured to receive one or more second input signal, process the information that is associated with this one or more second input signal and the second ramp signal, and at least generate one or more second based on the information be associated with this one or more second input signal and the second ramp signal and output signal.First ramp signal corresponds to first phase.Second ramp signal corresponds to second phase.Difference between first phase and second phase equals 180 degree.Such as, this system at least realizes according to Fig. 7 (a).
According to another embodiment, a kind ofly to comprise with the system generating multiple output signal for amplifying multiple input signal: the first channel and second channel.First channel comprises first ring path filter, the first signal processing component and the first output precision, and be configured to receive one or more first input signal, process the information that is associated with this one or more first input signal and ramp signal, and at least generate one or more first based on the information be associated with this one or more first input signal and ramp signal and output signal.Second channel comprises the second loop filter, secondary signal processing components and the second output precision, and be configured to receive one or more second input signal, process the information that is associated with this one or more second input signal and ramp signal, and at least generate one or more second based on the information be associated with this one or more second input signal and ramp signal and output signal.First ring path filter is configured to process the information that is associated with one or more first input signal, and at least generates one or more first through the signal of filtering based on the information be associated with one or more first input signal.First signal processing component is configured to process and the one or more first information joined through the signal correction of filtering, and at least generates one or more first treated signal based on the information joined through the signal correction of filtering with one or more first.First output precision is configured to process the information joined with one or more first treated signal correction, and at least generates one or more first based on the information joined with one or more first treated signal correction and output signal.Second loop filter is configured to process the information that is associated with one or more second input signal, and at least generates one or more second through the signal of filtering based on the information be associated with one or more second input signal.Secondary signal processing components is configured to process and the one or more second information joined through the signal correction of filtering, and at least generates one or more second treated signal based on the information joined through the signal correction of filtering with one or more second.Second output precision is configured to process the information joined with one or more second treated signal correction, and at least generates one or more second based on the information joined with one or more second treated signal correction and output signal.One or more first treated signal is associated with first phase.One or more second treated signal is associated with second phase.Difference between first phase and second phase equals 180 degree.Such as, this system at least realizes according to Fig. 7 (b).
In one embodiment, a kind ofly to comprise with the system generating multiple output signal for amplifying multiple input signal: the first channel and second channel.First channel comprises first ring path filter and one or more first comparator, and be configured to receive one or more first input signal, process the information that is associated with this one or more first input signal and ramp signal, and at least generate one or more first based on the information be associated with this one or more first input signal and ramp signal and output signal.Second channel comprises the second loop filter and one or more second comparator, and be configured to receive one or more second input signal, process the information that is associated with this one or more second input signal and ramp signal, and at least generate one or more second based on the information be associated with this one or more second input signal and ramp signal and output signal.First ring path filter is configured to process the information that is associated with one or more first input signal, and at least generates one or more first through the signal of filtering based on the information be associated with one or more first input signal.One or more first comparator comprises one or more first end and one or more second end, and be configured in first end reception one or more first through the signal of filtering and at the second termination receipts ramp signal, and at least generate one or more first comparison signal based on the information be associated through signal and the ramp signal of filtering with first, and export this one or more first comparison signal to generate one or more first output signal.Second loop filter is configured to process the information that is associated with one or more second input signal, and at least generates one or more second through the signal of filtering based on the information be associated with one or more second input signal.One or more second comparator comprises one or more 3rd end and one or more 4th end, and be configured in the 3rd termination receipts one or more second through the signal of filtering and at the 4th termination receipts ramp signal, and at least generate one or more second comparison signal based on the information be associated through signal and the ramp signal of filtering with second, and export this one or more second comparison signal to generate one or more second output signal.One or more second end comprises one or more end of oppisite phase, and one or more 4th end comprises one or more non-oppisite phase end, or one or more second end comprises one or more non-oppisite phase end, and one or more 4th end comprises one or more end of oppisite phase.Such as, this system at least realizes according to Fig. 7 (c).
In another embodiment, a kind ofly to comprise with the system generating multiple output signal for amplifying multiple input signal: oscillator assembly, it is configured to generate the ramp signal be associated with ramp frequency; Loop filter components, it is configured to receive one or more input signal and at least generate one or more signal through filtering based on the information be associated with this one or more input signal; And comparator component, it is configured to receive this one or more signal through filtering and ramp signal, and at least generates one or more comparison signal based on the information be associated with this one or more signal through filtering and ramp signal.Oscillator assembly is also configured to: periodic variation ramp frequency, makes the one or more changes produced in each shake cycle corresponding to chattering frequency in ramp frequency, and exports the ramp signal be associated with the ramp frequency through changing.Chattering frequency is greater than the upper limit of predetermined audio frequency range.Such as, this system at least realizes according to Fig. 8, Fig. 9, Figure 10 (a), Figure 10 (b), Figure 10 (c) and/or Figure 11.
In another embodiment, a kind ofly to comprise with the system generating multiple output signal for amplifying multiple input signal: oscillator assembly, it is configured to generate the ramp signal be associated with ramp frequency, and this ramp frequency is corresponding to one or more ramp cycle; Loop filter components, it is configured to receive one or more input signal and at least generate one or more signal through filtering based on the information be associated with this one or more input signal; And comparator component, it is configured to receive this one or more signal through filtering and ramp signal, and at least generates one or more comparison signal based on the information be associated with this one or more signal through filtering and ramp signal.Oscillator assembly is also configured to: at the end of the first ramp cycle, change charging current or discharging current, makes the second duration of ensuing second ramp cycle of the first duration of the first ramp cycle and the first ramp cycle different.First duration and the second duration correspond to the different values of ramp frequency.Such as, this system at least realizes according to Fig. 8, Fig. 9, Figure 10 (a), Figure 10 (b), Figure 10 (c), Figure 11, Figure 12, Figure 13, Figure 14 (a) and/or Figure 14 (b).
According to an embodiment, a kind ofly to comprise with the method generating multiple output signal for amplifying multiple input signal: receive one or more first input signal; Process the information be associated with this one or more first input signal and the first ramp signal; And at least generate one or more first based on the information be associated with this one or more first input signal and the first ramp signal and output signal.The method also comprises: receive one or more second input signal; Process the information be associated with this one or more second input signal and the second ramp signal; And at least generate one or more second based on the information be associated with this one or more second input signal and the second ramp signal and output signal.In addition, the method comprises: receive one or more 3rd input signal; Process the information be associated with this one or more 3rd input signal and the 3rd ramp signal; And at least generate one or more 3rd output signal based on the information be associated with this one or more 3rd input signal and the 3rd ramp signal.First ramp signal corresponds to first phase.Second ramp signal corresponds to second phase.First phase is different from second phase.Such as, the method at least realizes according to Fig. 5 and/or Fig. 6.
According to another embodiment, a kind ofly to comprise with the method generating multiple output signal for amplifying multiple input signal: receive one or more first input signal; Process the information be associated with this one or more first input signal and the first ramp signal; And at least generate one or more first based on the information be associated with this one or more first input signal and the first ramp signal and output signal.The method also comprises: receive one or more second input signal; Process the information be associated with this one or more second input signal and the second ramp signal; And at least generate one or more second based on the information be associated with this one or more second input signal and the second ramp signal and output signal.First ramp signal corresponds to first phase.Second ramp signal corresponds to second phase.Difference between first phase and second phase equals 180 degree.Such as, the method at least realizes according to Fig. 7 (a).
According to another embodiment, a kind ofly to comprise with the method generating multiple output signal for amplifying multiple input signal: receive one or more first input letter by the first channel comprising first ring path filter, the first signal processing component and the first output precision; Process the information be associated with this one or more first input signal and ramp signal; And at least generate one or more first based on the information be associated with this one or more first input signal and ramp signal and output signal.The method also comprises: receive one or more second input signal by the second channel comprising the second loop filter, secondary signal processing components and the second output precision; Process the information be associated with this one or more second input signal and ramp signal; And at least generate one or more second based on the information be associated with this one or more second input signal and ramp signal and output signal.Process the information be associated with one or more first input signal and ramp signal to comprise: the information be associated with one or more first input signal by the process of first ring path filter; At least generate one or more first through the signal of filtering based on the information be associated with one or more first input signal; By the first signal processing component process and the one or more first information joined through the signal correction of filtering; And at least generate one or more first treated signal based on the information joined through the signal correction of filtering with one or more first.At least generate one or more first based on the information be associated with one or more first input signal and ramp signal to output signal and comprise: the information joined by the first output precision process and one or more first treated signal correction, and at least generate one or more first based on the information joined with one or more first treated signal correction and output signal.Process the information be associated with one or more second input signal and ramp signal to comprise: the information be associated with one or more second input signal by the second loop filter process; At least generate one or more second through the signal of filtering based on the information be associated with one or more second input signal; By secondary signal processing modules process and the one or more second information joined through the signal correction of filtering; And at least generate one or more second treated signal based on the information joined through the signal correction of filtering with one or more second.At least generate one or more second based on the information be associated with one or more second input signal and ramp signal to output signal and comprise: the information joined by the second output precision process and one or more second treated signal correction, and at least generate one or more second based on the information joined with one or more second treated signal correction and output signal.One or more first treated signal is associated with first phase.One or more second treated signal is associated with second phase, and the difference between first phase and second phase equals 180 degree.Such as, the method at least realizes according to Fig. 7 (b).
In one embodiment, a kind ofly to comprise with the method generating multiple output signal for amplifying multiple input signal: receive one or more first input signal by the first channel comprising first ring path filter and one or more first comparator; Process the information be associated with this one or more first input signal and ramp signal; And at least generate one or more first based on the information be associated with this one or more first input signal and ramp signal and output signal.The method also comprises: receive one or more second input signal by the second channel comprising the second loop filter and one or more second comparator; Process the information be associated with this one or more second input signal and ramp signal; And at least generate one or more second based on the information be associated with this one or more second input signal and ramp signal and output signal.Process the information that is associated with one or more first input signal and ramp signal to comprise: the information be associated with one or more first input signal in the process of first ring path filter, and at least generate one or more first through the signal of filtering based on the information be associated with one or more first input signal.At least generate one or more first based on the information be associated with one or more first input signal and ramp signal to output signal and comprise: receive one or more first through the signal of filtering by one or more first ends of one or more first comparator; Ramp signal is received by one or more second terminations of one or more first comparator; At least generate one or more first comparison signal based on the information be associated through signal and the ramp signal of filtering with first; Export this one or more first comparison signal; And at least generate one or more first based on the information be associated with this one or more first comparison signal and output signal.Process the information that is associated with one or more second input signal and ramp signal to comprise: the information be associated with one or more second input signal by the second loop filter process, and at least generate one or more second through the signal of filtering based on the information be associated with one or more second input signal.At least generate one or more second based on the information be associated with one or more second input signal and ramp signal to output signal and comprise: receive one or more second through the signal of filtering by one or more 3rd terminations of one or more second comparator; Ramp signal is received by one or more 4th terminations of one or more second comparator; At least generate one or more second comparison signal based on the information be associated through signal and the ramp signal of filtering with second; Export this one or more second comparison signal; And at least generate one or more second based on the information be associated with this one or more second comparison signal and output signal.One or more second end comprises one or more end of oppisite phase, and one or more 4th end comprises one or more non-oppisite phase end, or one or more second end comprises one or more non-oppisite phase end, and one or more 4th end comprises one or more end of oppisite phase.Such as, the method at least realizes according to Fig. 7 (c).
In another embodiment, a kind ofly to comprise with the method generating multiple output signal for amplifying multiple input signal: generate the ramp signal be associated with ramp frequency; Receive one or more input signal; And process the information be associated with this one or more input signal.The method also comprises: at least generate one or more signal through filtering based on the information be associated with this one or more input signal; Receive this one or more signal through filtering and ramp signal; Process the information be associated with this one or more signal through filtering and ramp signal; And at least generate one or more comparison signal based on the information be associated with this one or more signal through filtering and ramp signal.Generate the ramp signal be associated with ramp frequency to comprise: periodic variation ramp frequency, make the one or more changes produced in each shake cycle corresponding to chattering frequency in ramp frequency, and export the ramp signal be associated with the ramp frequency through changing.Chattering frequency is greater than the upper limit of predetermined audio frequency range.Such as, the method at least realizes according to Fig. 8, Fig. 9, Figure 10 (a), Figure 10 (b), Figure 10 (c) and/or Figure 11.
In another embodiment, a kind ofly to comprise with the method generating multiple output signal for amplifying multiple input signal: generate the ramp signal be associated with ramp frequency, this ramp frequency is corresponding to one or more ramp cycle; Receive one or more input signal; And process the information be associated with this one or more input signal.The method also comprises: at least generate one or more signal through filtering based on the information be associated with this one or more input signal; Receive this one or more signal through filtering and ramp signal; And at least generate one or more comparison signal based on the information be associated with this one or more signal through filtering and ramp signal.Generate the ramp signal be associated with ramp frequency to comprise: at the end of the first ramp cycle, change charging current or discharging current, make the second duration of ensuing second ramp cycle of the first duration of the first ramp cycle and the first ramp cycle different.First duration and the second duration correspond to the different values of ramp frequency.Such as, the method at least realizes according to Fig. 8, Fig. 9, Figure 10 (a), Figure 10 (b), Figure 10 (c), Figure 11, Figure 12, Figure 13, Figure 14 (a) and/or Figure 14 (b).
According to an embodiment, comprise with the system generating multiple output signal for amplifying multiple input signal: first channel, it is configured to reception first input signal and the second input signal and generates the first output signal and second based on the first input signal and the second input signal at least partly output signal; And second channel, it is configured to reception the 3rd input signal and the 4th input signal and generates the 3rd output signal and the 4th output signal based on the 3rd input signal and the 4th input signal at least partly.First differential signal equals the first input signal and deducts the second input signal.Second differential signal equals the 3rd input signal and deducts the 4th input signal.First output signal corresponds to first phase.Second output signal corresponds to second phase.3rd output signal corresponds to third phase.4th output signal corresponds to the 4th phase place.First-phase potential difference equals first phase and deducts third phase.Second-phase potential difference equals second phase and deducts the 4th phase place.First differential signal is identical with the second differential signal.First-phase potential difference is not equal to 0.Second-phase potential difference is not equal to 0.First-phase potential difference is identical with second-phase potential difference.
According to another embodiment, a kind ofly to comprise with the system generating multiple output signal for amplifying multiple input signal: the first channel, it is configured to receive one or more first input signal, and generates one or more first output signal based on this one or more first input signal at least partly; And second channel, it is configured to receive one or more second input signal, and generates one or more second output signal based on this one or more second input signal at least partly.The first differential signal be associated with one or more first input signal equals the second differential signal be associated with one or more second input signal.One or more first output signal corresponds to one or more first phase.One or more second output signal corresponds to one or more second phase.Each of one or more differences between one or more first phase and corresponding one or more second phase is equal to 180 °.
According to another embodiment, comprise with the system generating multiple output signal for amplifying multiple input signal: first channel, it is configured to reception first input signal and the second input signal and generates the first output signal and second based on the first input signal and the second input signal at least partly output signal; And second channel, it is configured to reception the 3rd input signal and the 4th input signal and generates the 3rd output signal and the 4th output signal based on the 3rd input signal and the 4th input signal at least partly.First differential signal equals the first input signal and deducts the second input signal.Second differential signal equals the 3rd input signal and deducts the 4th input signal.When the first output signal and the second output signal are all corresponding to the first logic level, when the 3rd output signal and the 4th output signal are all corresponding to the second logic level, the second logic level is different from the first logic level.
In one embodiment, a kind ofly to comprise with the method generating multiple output signal for amplifying multiple input signal: receive the first input signal and the second input signal; The first output signal and the second output signal is generated at least partly based on the first input signal and the second input signal; Receive the 3rd input signal and the 4th input signal; And generate the 3rd output signal and the 4th output signal based on the 3rd input signal and the 4th input signal at least partly.First differential signal equals the first input signal and deducts the second input signal.Second differential signal equals the 3rd input signal and deducts the 4th input signal.First output signal corresponds to first phase.Second output signal corresponds to second phase.3rd output signal corresponds to third phase.4th output signal corresponds to the 4th phase place.First-phase potential difference equals first phase and deducts third phase.Second-phase potential difference equals second phase and deducts the 4th phase place.First differential signal is identical with the second differential signal.First-phase potential difference is not equal to 0.Second-phase potential difference is not equal to 0.First-phase potential difference is identical with second-phase potential difference.
In another embodiment, a kind ofly to comprise with the method generating multiple output signal for amplifying multiple input signal: receive one or more first input signal; One or more first output signal is generated at least partly based on this one or more first input signal; Receive one or more second input signal; And generate one or more second output signal based on this one or more second input signal at least partly.The first differential signal be associated with one or more first input signal equals the second differential signal be associated with one or more second input signal.One or more first output signal corresponds to one or more first phase.One or more second output signal corresponds to one or more second phase.Each of one or more differences between one or more first phase and corresponding one or more second phase is equal to 180 °.
In another embodiment, a kind ofly to comprise with the method generating multiple output signal for amplifying multiple input signal: receive the first input signal and the second input signal; The first output signal and the second output signal is generated at least partly based on the first input signal and the second input signal; Receive the 3rd input signal and the 4th input signal; The 3rd output signal and the 4th output signal is generated at least partly based on the 3rd input signal and the 4th input signal.First differential signal equals the first input signal and deducts the second input signal.Second differential signal equals the 3rd input signal and deducts the 4th input signal.When the first output signal and the second output signal are all corresponding to the first logic level, when the 3rd output signal and the 4th output signal are all corresponding to the second logic level, the second logic level is different from the first logic level.
Such as, some or all assemblies of various embodiment of the present invention are each by using one or more combinations of one or more component software, one or more nextport hardware component NextPort and/or software and hardware assembly, realize in combination individually and/or with at least another assembly.In another example, some or all assemblies of various embodiment of the present invention are individually each and/or realize in combination in one or more circuit with at least another assembly, and this one or more circuit is such as one or more analog circuit and/or one or more digital circuit.In another example, various embodiment of the present invention and/or example can be combined.
Although be described specific embodiments of the invention, it should be appreciated by those skilled in the art to there is other embodiment be equal to described embodiment.Therefore, should be understood that, the present invention can't help concrete illustrated embodiment and limits, but is only limited by the scope of claims.

Claims (38)

1., for amplifying multiple input signal to generate a system for multiple output signal, described system comprises:
First channel, described first channel is configured to reception first input signal and the second input signal and generates the first output signal and second based on described first input signal and described second input signal at least partly output signal; And
Second channel, described second channel is configured to reception the 3rd input signal and the 4th input signal and generates the 3rd output signal and the 4th output signal based on described 3rd input signal and described 4th input signal at least partly;
Wherein:
First differential signal equals described first input signal and deducts described second input signal; And
Second differential signal equals described 3rd input signal and deducts described 4th input signal;
Wherein:
Described first output signal corresponds to first phase;
Described second output signal corresponds to second phase;
Described 3rd output signal corresponds to third phase; And
Described 4th output signal corresponds to the 4th phase place;
Wherein:
First-phase potential difference equals described first phase and deducts described third phase; And
Second-phase potential difference equals described second phase and deducts described 4th phase place;
Wherein:
Described first differential signal is identical with described second differential signal;
Described first-phase potential difference is not equal to 0;
Described second-phase potential difference is not equal to 0;
Described first-phase potential difference is identical with described second-phase potential difference.
2. the system as claimed in claim 1, wherein said first channel is also configured to: receive ramp signal; And
Described first output signal and described second output signal is generated at least partly based on described first input signal, described second input signal and described ramp signal.
3. the system as claimed in claim 1, wherein said second channel is also configured to:
Receive ramp signal; And
Described 3rd output signal and described 4th output signal is generated at least partly based on described 3rd input signal, described 4th input signal and described ramp signal.
4. the system as claimed in claim 1, wherein:
Described first-phase potential difference equals 180 °; And
Described second-phase potential difference equals 180 °.
5. the system as claimed in claim 1, wherein said first channel comprises:
First ring path filter, described first ring path filter is configured to receive described first input signal, described second input signal, described first output signal and described second output signal, and at least partly based on described first input signal, described second input signal, described first output signal and described second output signal generation first through the signal and second of filtering through the signal of filtering;
First signal processing component, described first signal processing component is configured to receive described first through the signal, described second of filtering through the signal of filtering and ramp signal, and generates one or more first treated signal through the signal, described second of filtering through the signal of filtering and described ramp signal based on described first at least partly; And
One or more first output precision, described one or more first output precision is configured to receive described one or more first treated signal, and generates described first output signal and described second based on described one or more first treated signal at least partly and output signal.
6. system as claimed in claim 5, wherein said first signal processing component comprises:
First comparator, described first comparator is configured to receive described ramp signal and described first through the signal of filtering, and generates the first comparison signal based on described ramp signal and described first through the signal of filtering at least partly; And
Second comparator, described second comparator is configured to receive described ramp signal and described second through the signal of filtering, and generates the second comparison signal based on described ramp signal and described second through the signal of filtering at least partly.
7. system as claimed in claim 6, wherein said first signal processing component also comprises:
Phase control assembly, described phase control assembly is configured to receive described first comparison signal and described second comparison signal, and generates one or more phase control signal based on described first comparison signal and described second comparison signal at least partly; And
Logic control assembly, described logic control assembly is configured to receive described one or more phase control signal, and generates one or more logic control signal based on described one or more phase control signal at least partly.
8. system as claimed in claim 7, wherein said first signal processing component also comprises:
First actuator assembly, described first actuator assembly is configured to, at least partly based on described one or more logic control signal, one or more first drive singal be outputted to described one or more first output precision; And
Second actuator assembly, described second actuator assembly is configured to, at least partly based on described one or more logic control signal, one or more second drive singal be outputted to described one or more first output precision;
Wherein said one or more first drive singal and described one or more second drive singal are included in described one or more first treated signal.
9. the system as claimed in claim 1, wherein said second channel comprises:
First ring path filter, described first ring path filter is configured to receive described 3rd input signal, described 4th input signal, described 3rd output signal and described 4th output signal, and at least partly based on described 3rd input signal, described 4th input signal, described 3rd output signal and described 4th output signal generation first through the signal and second of filtering through the signal of filtering;
First signal processing component, described first signal processing component is configured to receive described first through the signal, described second of filtering through the signal of filtering and ramp signal, and generates one or more first treated signal through the signal, described second of filtering through the signal of filtering and described ramp signal based on described first at least partly; And
One or more first output precision, described one or more first output precision is configured to receive described one or more first treated signal, and generates described 3rd output signal and the described 4th based on described one or more first treated signal at least partly and output signal.
10. system as claimed in claim 9, wherein said first signal processing component comprises:
First comparator, described first comparator is configured to receive described ramp signal and described first through the signal of filtering, and generates the first comparison signal based on described ramp signal and described first through the signal of filtering at least partly; And
Second comparator, described second comparator is configured to receive described ramp signal and described second through the signal of filtering, and generates the second comparison signal based on described ramp signal and described second through the signal of filtering at least partly.
11. systems as claimed in claim 10, wherein said first signal processing component also comprises:
Phase control assembly, described phase control assembly is configured to receive described first comparison signal and described second comparison signal, and generates one or more phase control signal based on described first comparison signal and described second comparison signal at least partly; And
Logic control assembly, described logic control assembly is configured to receive described one or more phase control signal, and generates one or more logic control signal based on described one or more phase control signal at least partly.
12. systems as claimed in claim 11, wherein said first signal processing component also comprises:
First actuator assembly, described first actuator assembly is configured to, at least partly based on described one or more logic control signal, one or more first drive singal be outputted to described one or more first output precision; And
Second actuator assembly, described second actuator assembly is configured to, at least partly based on described one or more logic control signal, one or more second drive singal be outputted to described one or more first output precision;
Wherein said one or more first drive singal and described one or more second drive singal are included in described one or more first treated signal.
13. 1 kinds for amplifying multiple input signal to generate the system of multiple output signal, described system comprises:
First channel, described first channel is configured to receive one or more first input signal, and generates one or more first output signal based on described one or more first input signal at least partly; And
Second channel, described second channel is configured to receive one or more second input signal, and generates one or more second output signal based on described one or more second input signal at least partly:
Wherein, the first differential signal be associated with described one or more first input signal equals the second differential signal be associated with described one or more second input signal;
Wherein:
Described one or more first output signal corresponds to one or more first phase;
Described one or more second output signal corresponds to one or more second phase; And
Each of one or more differences between described one or more first phase and corresponding one or more second phase is equal to 180 °.
14. systems as claimed in claim 13, wherein said first channel is also configured to:
Receive ramp signal; And
Described one or more first output signal is generated at least partly based on described one or more first input signal and described ramp signal.
15. systems as claimed in claim 13, wherein said second channel is also configured to:
Receive ramp signal; And
Described one or more second output signal is generated at least partly based on described one or more second input signal and described ramp signal.
16. systems as claimed in claim 13, wherein said first channel comprises:
First ring path filter, described first ring path filter is configured to receive described one or more first input signal and described one or more first output signal, and outputs signal the signal of generation one or more first through filtering based on described one or more first input signal and described one or more first at least partly;
First signal processing component, described first signal processing component is configured to receive described one or more first through the signal of filtering and ramp signal, and generates one or more first treated signal based on described one or more first through the signal of filtering and described ramp signal at least partly; And
One or more first output precision, described one or more first output precision is configured to receive described one or more first treated signal, and generates described one or more first output signal based on described one or more first treated signal at least partly.
17. systems as claimed in claim 16, wherein said first signal processing component comprises:
One or more comparator, described one or more comparator is configured to receive described ramp signal and described one or more first through the signal of filtering, and generates one or more comparison signal based on described ramp signal and described one or more first through the signal of filtering at least partly.
18. systems as claimed in claim 17, wherein said first signal processing component also comprises:
Phase control assembly, described phase control assembly is configured to receive described one or more comparison signal, and generates one or more phase control signal based on described one or more comparison signal at least partly; And
Logic control assembly, described logic control assembly is configured to receive described one or more phase control signal, and generates one or more logic control signal based on described one or more phase control signal at least partly.
19. systems as claimed in claim 18, wherein said first signal processing component also comprises:
One or more actuator assembly, described one or more actuator assembly is configured to, at least partly based on described one or more logic control signal, one or more drive singal be outputted to described one or more first output precision;
Wherein said one or more drive singal is included in described one or more first treated signal.
20. systems as claimed in claim 13, wherein said second channel comprises:
First ring path filter, described first ring path filter is configured to receive described one or more second input signal and described one or more second output signal, and outputs signal the signal of generation one or more first through filtering based on described one or more second input signal and described one or more second at least partly;
First signal processing component, described first signal processing component is configured to receive described one or more first through the signal of filtering and ramp signal, and generates one or more first treated signal based on described one or more first through the signal of filtering and described ramp signal at least partly; And
One or more first output precision, described one or more first output precision is configured to receive described one or more first treated signal, and generates described one or more second output signal based on described one or more first treated signal at least partly.
21. systems as claimed in claim 20, wherein said first signal processing component comprises:
One or more comparator, described one or more comparator is configured to receive described ramp signal and described one or more first through the signal of filtering, and generates one or more comparison signal based on described ramp signal and described one or more first through the signal of filtering at least partly.
22. systems as claimed in claim 21, wherein said first signal processing component also comprises:
Phase control assembly, described phase control assembly is configured to receive described one or more comparison signal, and generates one or more phase control signal based on described one or more comparison signal at least partly; And
Logic control assembly, described logic control assembly is configured to receive described one or more phase control signal, and generates one or more logic control signal based on described one or more phase control signal at least partly.
23. the system as claimed in claim 22, wherein said first signal processing component also comprises:
One or more actuator assembly, described one or more actuator assembly is configured to, at least partly based on described one or more logic control signal, one or more drive singal be outputted to described one or more first output precision;
Wherein said one or more drive singal is included in described one or more first treated signal.
24. 1 kinds for amplifying multiple input signal to generate the system of multiple output signal, described system comprises:
First channel, described first channel is configured to reception first input signal and the second input signal and generates the first output signal and second based on described first input signal and described second input signal at least partly output signal; And
Second channel, described second channel is configured to reception the 3rd input signal and the 4th input signal and generates the 3rd output signal and the 4th output signal based on described 3rd input signal and described 4th input signal at least partly;
Wherein:
First differential signal equals described first input signal and deducts described second input signal; And
Second differential signal equals described 3rd input signal and deducts described 4th input signal;
Wherein, when described first output signal and described second output signal are all corresponding to the first logic level, when described 3rd output signal and described 4th output signal are all corresponding to the second logic level, described second logic level is different from described first logic level.
25. systems as claimed in claim 24, wherein said first logic level corresponds to logic low, and described second logic level corresponds to logic high.
26. systems as claimed in claim 24, wherein said first channel is also configured to:
Receive ramp signal; And
Described first output signal and described second output signal is generated at least partly based on described first input signal, described second input signal and described ramp signal.
27. systems as claimed in claim 24, wherein said second channel is also configured to:
Receive ramp signal; And
Described 3rd output signal and described 4th output signal is generated at least partly based on described 3rd input signal, described 4th input signal and described ramp signal.
28. systems as claimed in claim 24, wherein said first channel comprises:
First ring path filter, described first ring path filter is configured to receive described first input signal, described second input signal, described first output signal and described second output signal, and at least partly based on described first input signal, described second input signal, described first output signal and described second output signal generation first through the signal and second of filtering through the signal of filtering;
First signal processing component, described first signal processing component is configured to receive described first through the signal, described second of filtering through the signal of filtering and ramp signal, and generates one or more first treated signal through the signal, described second of filtering through the signal of filtering and described ramp signal based on described first at least partly; And
One or more first output precision, described one or more first output precision is configured to receive described one or more first treated signal, and generates described first output signal and described second based on described one or more first treated signal at least partly and output signal.
29. systems as claimed in claim 28, wherein said first signal processing component comprises:
First comparator, described first comparator is configured to receive described ramp signal and described first through the signal of filtering, and generates the first comparison signal based on described ramp signal and described first through the signal of filtering at least partly; And
Second comparator, described second comparator is configured to receive described ramp signal and described second through the signal of filtering, and generates the second comparison signal based on described ramp signal and described second through the signal of filtering at least partly.
30. systems as claimed in claim 29, wherein said first signal processing component also comprises:
Phase control assembly, described phase control assembly is configured to receive described first comparison signal and described second comparison signal, and generates one or more phase control signal based on described first comparison signal and described second comparison signal at least partly; And
Logic control assembly, described logic control assembly is configured to receive described one or more phase control signal, and generates one or more logic control signal based on described one or more phase control signal at least partly.
31. systems as claimed in claim 30, wherein said first signal processing component also comprises:
First actuator assembly, described first actuator assembly is configured to, at least partly based on described one or more logic control signal, one or more first drive singal be outputted to described one or more first output precision; And
Second actuator assembly, described second actuator assembly is configured to, at least partly based on described one or more logic control signal, one or more second drive singal be outputted to described one or more first output precision;
Wherein said one or more first drive singal and described one or more second drive singal are included in described one or more first treated signal.
32. systems as claimed in claim 24, wherein said second channel comprises:
First ring path filter, described first ring path filter is configured to receive described 3rd input signal, described 4th input signal, described 3rd output signal and described 4th output signal, and at least partly based on described 3rd input signal, described 4th input signal, described 3rd output signal and described 4th output signal generation first through the signal and second of filtering through the signal of filtering;
First signal processing component, described first signal processing component is configured to receive described first through the signal, described second of filtering through the signal of filtering and ramp signal, and generates one or more first treated signal through the signal, described second of filtering through the signal of filtering and described ramp signal based on described first at least partly; And
One or more first output precision, described one or more first output precision is configured to receive described one or more first treated signal, and generates described 3rd output signal and the described 4th based on described one or more first treated signal at least partly and output signal.
33. systems as claimed in claim 32, wherein said first signal processing component comprises:
First comparator, described first comparator is configured to receive described ramp signal and described first through the signal of filtering, and generates the first comparison signal based on described ramp signal and described first through the signal of filtering at least partly; And
Second comparator, described second comparator is configured to receive described ramp signal and described second through the signal of filtering, and generates the second comparison signal based on described ramp signal and described second through the signal of filtering at least partly.
34. systems as claimed in claim 33, wherein said first signal processing component also comprises:
Phase control assembly, described phase control assembly is configured to receive described first comparison signal and described second comparison signal, and generates one or more phase control signal based on described first comparison signal and described second comparison signal at least partly; And
Logic control assembly, described logic control assembly is configured to receive described one or more phase control signal, and generates one or more logic control signal based on described one or more phase control signal at least partly.
35. systems as claimed in claim 34, wherein said first signal processing component also comprises:
First actuator assembly, described first actuator assembly is configured to, at least partly based on described one or more logic control signal, one or more first drive singal be outputted to described one or more first output precision; And
Second actuator assembly, described second actuator assembly is configured to, at least partly based on described one or more logic control signal, one or more second drive singal be outputted to described one or more first output precision;
Wherein said one or more first drive singal and described one or more second drive singal are included in described one or more first treated signal.
36. 1 kinds for amplifying multiple input signal to generate the method for multiple output signal, described method comprises:
Receive the first input signal and the second input signal;
The first output signal and the second output signal is generated at least partly based on described first input signal and described second input signal;
Receive the 3rd input signal and the 4th input signal; And
The 3rd output signal and the 4th output signal is generated at least partly based on described 3rd input signal and described 4th input signal;
Wherein:
First differential signal equals described first input signal and deducts described second input signal; And
Second differential signal equals described 3rd input signal and deducts described 4th input signal;
Wherein:
Described first output signal corresponds to first phase;
Described second output signal corresponds to second phase;
Described 3rd output signal corresponds to third phase; And
Described 4th output signal corresponds to the 4th phase place;
Wherein:
First-phase potential difference equals described first phase and deducts described third phase; And
Second-phase potential difference equals described second phase and deducts described 4th phase place;
Wherein:
Described first differential signal is identical with described second differential signal;
Described first-phase potential difference is not equal to 0;
Described second-phase potential difference is not equal to 0;
Described first-phase potential difference is identical with described second-phase potential difference.
37. 1 kinds for amplifying multiple input signal to generate the method for multiple output signal, described method comprises:
Receive one or more first input signal;
One or more first output signal is generated at least partly based on described one or more first input signal;
Receive one or more second input signal; And
One or more second output signal is generated at least partly based on described one or more second input signal;
Wherein, the first differential signal be associated with described one or more first input signal equals the second differential signal be associated with described one or more second input signal;
Wherein:
Described one or more first output signal corresponds to one or more first phase;
Described one or more second output signal corresponds to one or more second phase; And
Each of one or more differences between described one or more first phase and corresponding one or more second phase is equal to 180 °.
38. 1 kinds for amplifying multiple input signal to generate the method for multiple output signal, described method comprises:
Receive the first input signal and the second input signal;
The first output signal and the second output signal is generated at least partly based on described first input signal and described second input signal;
Receive the 3rd input signal and the 4th input signal;
The 3rd output signal and the 4th output signal is generated at least partly based on described 3rd input signal and described 4th input signal;
Wherein:
First differential signal equals described first input signal and deducts described second input signal; And
Second differential signal equals described 3rd input signal and deducts described 4th input signal;
Wherein, when described first output signal and described second output signal are all corresponding to the first logic level, when described 3rd output signal and described 4th output signal are all corresponding to the second logic level, described second logic level is different from described first logic level.
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TW104117212A TWI581560B (en) 2015-03-16 2015-05-28 A system and a method for amplifying a plurality of input signals and modulating a plurality of output signals
US15/418,313 US10505507B2 (en) 2013-08-21 2017-01-27 Amplification systems and methods with output regulation
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