CN104701368A

CN104701368A - Radiofrequency LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method thereof

Info

Publication number: CN104701368A
Application number: CN201310655616.8A
Authority: CN
Inventors: 钱文生
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2013-12-06
Filing date: 2013-12-06
Publication date: 2015-06-10
Anticipated expiration: 2033-12-06
Also published as: CN104701368B

Abstract

The invention discloses a radiofrequency LDMOS (laterally diffused metal oxide semiconductor) device. Drift regions are uneven doping structures; a first drift region, a third drift region and a second drift region are sequentially arranged between a channel and a drain region; the doping concentration of the first drift region is minimum, the strength of an electric field nearby a channel region and a hot carrier effect can be reduced, and the reliability of the device is improved; the doping concentration of the second drift region is high, and the switch-on resistance of the device can be reduced; and by a contra-doping covering layer formed on the surface of the second drift region, the drift regions can run out effectively, the outputting capacitance of the device is reduced, influences of charge and an interface state of shielding dielectric layer without a Faraday shield layer can be avoided, and the characteristics of the device are stable. The second drift region is a transition region, and the driving current of the device can be increased further and the switch-on resistance of the device can be reduced under the condition that the reliability and the outputting capacitance of the device are not affected. The invention also discloses a manufacturing method of the radiofrequency LDMOS device.

Description

Radio frequency LDMOS device and manufacture method thereof

Technical field

The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of radio frequency LDMOS device; The invention still further relates to a kind of manufacture method of radio frequency LDMOS device.

Background technology

Radio frequency lateral fet (RF LDMOS) is the conventional device being applied to radio-frequency (RF) base station and broadcasting station.High-breakdown-voltage, low source and drain conducting resistance (RDSON) and low source and drain parasitic capacitance (Coss) are the prerequisite device properties of RF LDMOS.In order to reduce the parasitic capacitance between source region and raceway groove, substrate most possibly, usually adopt heavily doped backing material to add lightly doped epitaxial loayer, and utilize the dark contact hole of tungsten to connect source region, raceway groove, epitaxial loayer and substrate.As shown in Figure 1, be the structural representation of existing radio frequency LDMOS device, for N-type device, existing radio frequency LDMOS device comprises: the silicon substrate 101 of the heavy doping of P type and P+ doping, the doping content of silicon substrate 101 is greater than 1e20cm ^-3; The lightly doped silicon epitaxy layer 102 of P type, the doping content of silicon epitaxy layer 102 and thickness depend on the drain terminal operating voltage of device, and drain terminal operating voltage is higher, silicon epitaxy layer 102 adulterate lower, thickness is thicker; N-type drift region 103, is formed in silicon epitaxy layer 102; P type doping channel region 104, channel region 104 and drift region 103 adjacent in the horizontal; Gate dielectric layer 107 and polysilicon gate 108; The source region 105 of N-type heavy doping and N+ doping, drain region 106; In source region 105, the surface of drain region 106 and polysilicon gate 108 is formed with metal silicide 112; Shielding dielectric layer 109 and faraday shield layer 110, on the side covering the drain terminal of polysilicon gate 108 and end face; Dark contact hole 111, be made up of the metal be filled in deep trouth such as tungsten, deep trouth passes source region 105, channel region 104 and silicon epitaxy layer 102 and enters into silicon substrate 101, and source region 105, channel region 104, silicon epitaxy layer 102 and silicon substrate 101 are electrically connected by dark contact hole 111.

When hyperfrequency is applied, the requirement of RDSON and Coss of radio frequency LDMOS device is higher.When wanting RDSON to keep lower, need the doping content improving drift region 103 as far as possible, but when this may cause drain region 106 end to add high pressure, drift region 103 can not fully-depleted and cause puncture voltage to decline.The principal element restricting Coss decline is in addition the junction capacitance of drift region 103 to silicon substrate 101, as drift region 103 concentration improves, also can increase this junction capacitance, be unfavorable for the decline of Coss equally.Therefore, RDSON and Coss two parameters restrict mutually, and existing device architecture can not make both all reduce, so the device property of existing radio frequency LDMOS is difficult to reach excellent properties simultaneously simply by the concentration increasing drift region.

Summary of the invention

Technical problem to be solved by this invention is to provide a kind of radio frequency LDMOS device, can reduce source and drain conducting resistance and the source and drain parasitic capacitance of device simultaneously, increases drive current, improves the radiofrequency characteristics of device.For this reason, the present invention also provides a kind of manufacture method of radio frequency LDMOS device.

For solving the problems of the technologies described above, radio frequency LDMOS device provided by the invention comprises:

The heavily doped silicon substrate of first conduction type.

The silicon epitaxy layer of the first conduction type doping, this silicon epitaxy layer is formed in described surface of silicon.

First drift region, be made up of the second conductive type ion injection region be formed in the selection area of described silicon epitaxy layer, the degree of depth of equal with the top surface of described silicon epitaxy layer, described first drift region of top surface of described first drift region is less than the thickness of described silicon epitaxy layer.

Channel region, be made up of the first conductive type ion injection region be formed in the selection area of described silicon epitaxy layer, first side and the described channel region of described first drift region contact in the horizontal, and the degree of depth of equal with the top surface of described silicon epitaxy layer, the described channel region of top surface of described channel region is less than or equal to the degree of depth of described first drift region.

Polysilicon gate, be formed at above described channel region, described polysilicon gate and described silicon epitaxy zone isolation have gate dielectric layer, and channel region described in described polysilicon gate cover part also extends to above described first drift region, and the described channel region covered by described polysilicon gate is surperficial for the formation of raceway groove.

Source region, is made up of the second conduction type heavily doped region be formed in described channel region, the first side autoregistration of described source region and described polysilicon gate.

Drain region, is made up of the second conduction type heavily doped region be formed in described first drift region, and the second side of described drain region and described polysilicon gate is separated by a lateral separation.

Second drift region, be made up of the second conductive type ion injection region be formed in the subregion of described first drift region, the first side of described second drift region and the first side of described first drift region are separated by a segment distance, the second side of described second drift region and described drain region lateral contact.

Contra-doping cover layer, is formed with the first conduction type doped region forms by being formed at described second surface, drift region.

3rd drift region, be made up of the second conductive type ion injection region be formed in the subregion of described first drift region, first side of described 3rd drift region and the first side of described first drift region are separated by a segment distance, the second side of described 3rd drift region and the first side of described second drift region contact or the second side of described 3rd drift region extend in described second drift region make described 3rd drift region and described second drift region portion overlapping.

The drift region of radio frequency LDMOS device is made up of described first drift region, described second drift region, described 3rd drift region and described contra-doping cover layer.

Shielding dielectric layer, is formed on the side of the second side of described polysilicon gate and end face and on the surface of described drift region.

Faraday shield layer, is formed on described shielding dielectric layer, and described faraday shield layer covers the side of the second side of described polysilicon gate and end face and the second side of described faraday shield layer extends to above described drift region.

Make the region between the first side of described 3rd drift region and the first side of described first drift region be region one, the described drift region in described region one is made up of the subregion of described first drift region; Second side of described polysilicon gate is positioned at directly over described region one, and the second side of described faraday shield layer is positioned at directly over described 3rd drift region or the second side of described faraday shield layer is positioned at directly over described second drift region.

The doping content of described 3rd drift region is greater than the doping content of described first drift region, the doping content of described 3rd drift region is less than the doping content of described second drift region; The doping content of described first drift region is less, and the reliability of less, the described radio frequency LDMOS device of electric field strength in described region one is higher; The doping content of described second drift region is larger, and the source and drain conducting resistance of described radio frequency LDMOS device is less; Described contra-doping cover layer exhausting and reducing the source and drain parasitic capacitance of described radio frequency LDMOS device for increasing described second drift region; Described 3rd drift region is the transitional region between described first drift region and described second drift region.

Further improvement is, the tectal junction depth of described contra-doping is less than 1/5 of the junction depth of described second drift region, and the tectal bulk concentration of described contra-doping is greater than 2 times of the bulk concentration of described second drift region.

Further improvement is, the bulk concentration of described first drift region is 1e16cm ^-3~ 5e16cm ^-3; The bulk concentration of described second drift region is 5e16cm ^-3~ 1e17cm ^-3; The bulk concentration of described 3rd drift region is 2e16cm ^-3~ 6e16cm ^-3.

Further improvement is, described radio frequency LDMOS device is N-type device, and described first conduction type is P type, and described second conduction type is N-type; Or described radio frequency LDMOS device is P type device, and described first conduction type is N-type, and described second conduction type is P type.

For solving the problems of the technologies described above, the manufacture method of radio frequency LDMOS device provided by the invention comprises the steps:

Step one, the heavily doped surface of silicon Epitaxial growth of the first conduction type formed first conduction type doping silicon epitaxy layer.

Step 2, adopt the second conductive type ion injection technology in the selection area of described silicon epitaxy layer, form the first drift region, the selection area forming described first drift region is defined by photoetching process, and the degree of depth of equal with the top surface of described silicon epitaxy layer, described first drift region of top surface of described first drift region is less than the thickness of described silicon epitaxy layer; The position of the first side of described first drift region is the position that the channel region adjoin of described first drift region and follow-up formation touches.

Step 3, employing photoetching process define the forming region of the second drift region, adopt the second conductive type ion injection technology in the forming region of described second drift region, form described second drift region, adopt the second conductive type ion injection technology to form contra-doping cover layer on the surface of described second drift region; Described second drift region is arranged in the subregion of described first drift region and the first side of the first side of described second drift region and described first drift region an is separated by segment distance.

Step 4, employing photoetching process define the forming region of the 3rd drift region, adopt the second conductive type ion injection technology in the forming region of described 3rd drift region, form described 3rd drift region; Described 3rd drift region is arranged in the subregion of described first drift region, first side of described 3rd drift region and the first side of described first drift region are separated by a segment distance, the second side of described 3rd drift region and the first side of described second drift region contact or the second side of described 3rd drift region extend in described second drift region make described 3rd drift region and described second drift region portion overlapping.

The drift region of radio frequency LDMOS device is made up of described first drift region, described second drift region, described 3rd drift region and described contra-doping cover layer; Make the region between the first side of described 3rd drift region and the first side of described first drift region be region one, the described drift region in described region one is made up of the subregion of described first drift region.

Step 5, be formed with the described silicon epitaxy layer superficial growth gate dielectric layer of described drift region.

Step 6, heavy doping is carried out to described polysilicon at described gate dielectric layer surface deposition polysilicon.

Step 7, employing lithographic etch process carry out first time etching to described polysilicon, and this first time etches removes the described polysilicon of source side, and the border after described first time etches is the first side of the polysilicon gate of follow-up formation.

Step 8, in the selection area of described silicon epitaxy layer carry out first conductive type ion inject formed described channel region, the selection area forming described channel region is defined by photoetching process and the first side autoregistration of the selection area of described channel region and described polysilicon gate, described channel region and described first drift region adjacent in the horizontal, the degree of depth of equal with the top surface of described silicon epitaxy layer, the described channel region of top surface of described channel region is less than or equal to the degree of depth of described first drift region.

Step 9, employing lithographic etch process carry out second time etching to described polysilicon and form described polysilicon gate, and described polysilicon gate is as the grid of described radio frequency LDMOS device; Second side of described polysilicon gate extends to above described first drift region and the second side of described polysilicon gate and is positioned at directly over described region one; The described channel region covered by described polysilicon gate is surperficial for the formation of raceway groove.

Step 10, at described silicon substrate front deposition dielectric layer, described shielding dielectric layer covers the described silicon epitaxy layer surface outside the end face of described polysilicon gate and side surface and described polysilicon gate.

Step 11, at described shielding dielectric layer surface deposit faraday shield layer.

Step 12, employing dry etch process etch described faraday shield layer, after etching, described faraday shield layer covers the side of the second side of described polysilicon gate and end face and the second side of described faraday shield layer extends to above described drift region, and the second side of described faraday shield layer is positioned at directly over described 3rd drift region or the second side of described faraday shield layer is positioned at directly over described second drift region.

Step 13, the second conduction type heavy doping ion of carrying out are injected and are formed source region and drain region, the first side autoregistration of described source region and described polysilicon gate; Second side of described drain region and described polysilicon gate is separated by a lateral separation and the second side of described second drift region and described drain region lateral contact.

Step 14, depositing metal silicide annealed alloy, described metal silicide is formed at described source region, described drain region and not by described polycrystalline silicon gate surface that described faraday shield layer covers.

Step 15, carry out deep etching, described deep trouth is through described source region, described channel region and described silicon epitaxy layer and enter into described silicon substrate; In described deep trouth, fill metal form described dark contact hole, described dark contact hole is by described source region, described channel region, described silicon epitaxy layer and the electrical connection of described silicon substrate.

Step 2, at described silicon epitaxy layer superficial growth gate dielectric layer.

Step 3, heavy doping is carried out to described polysilicon at described gate dielectric layer surface deposition polysilicon.

Step 4, employing lithographic etch process carry out first time etching to described polysilicon, and this first time etches removes the described polysilicon of source side, and the border after described first time etches is the first side of the polysilicon gate of follow-up formation.

Step 5, in the selection area of described silicon epitaxy layer carry out first conductive type ion inject formed described channel region, the selection area forming described channel region is defined by photoetching process and the first side autoregistration of the selection area of described channel region and described polysilicon gate; The degree of depth of equal with the top surface of described silicon epitaxy layer, the described channel region of top surface of described channel region is less than the thickness of described silicon epitaxy layer.

Step 6, employing lithographic etch process carry out second time etching to described polysilicon and form described polysilicon gate, and described polysilicon gate is as the grid of described radio frequency LDMOS device; Channel region described in described polysilicon gate cover part, the described channel region covered by described polysilicon gate is surperficial for the formation of raceway groove.

Step 7, adopt the second conductive type ion injection technology in the selection area of described silicon epitaxy layer, form the first drift region, the selection area forming described first drift region is defined by photoetching process and the second side autoregistration of the selection area of described first drift region and described polysilicon gate; The degree of depth of equal with the top surface of described silicon epitaxy layer, described first drift region of top surface of described first drift region is less than the thickness of described silicon epitaxy layer and the degree of depth of described channel region is less than or equal to the degree of depth of described first drift region; First side and the described channel region of described first drift region contact in the horizontal, and the second side of described polysilicon gate extends to above described first drift region.

Step 8, employing photoetching process define the forming region of the second drift region, adopt the second conductive type ion injection technology in the forming region of described second drift region, form described second drift region, adopt the second conductive type ion injection technology to form contra-doping cover layer on the surface of described second drift region; Described second drift region is arranged in the subregion of described first drift region and the first side of the first side of described second drift region and described first drift region an is separated by segment distance.

Step 9, employing photoetching process define the forming region of the 3rd drift region, adopt the second conductive type ion injection technology in the forming region of described 3rd drift region, form described 3rd drift region; Described 3rd drift region is arranged in the subregion of described first drift region, first side of described 3rd drift region and the first side of described first drift region are separated by a segment distance, the second side of described 3rd drift region and the first side of described second drift region contact or the second side of described 3rd drift region extend in described second drift region make described 3rd drift region and described second drift region portion overlapping.

The drift region of radio frequency LDMOS device is made up of described first drift region, described second drift region, described 3rd drift region and described contra-doping cover layer; Make the region between the first side of described 3rd drift region and the first side of described first drift region be region one, the described drift region in described region one is made up of the subregion of described first drift region; Second side of described polysilicon gate is positioned at directly over described region one.

Further improvement is, the second conductive type ion injection technology of described first drift region is that primary ions is injected, and this primary ions is injected and added that furnace anneal advances described first drift region of formation; Or the second conductive type ion injection technology of described first drift region is repeatedly the different ion implantation of Implantation Energy, the ion implanted region that repeatedly degree of depth that formed of ion implantation is different is directly connected to form after described first drift region or ion implanted region furnace anneal that repeatedly degree of depth that formed of ion implantation is different advance and forms described first drift region.

Further improvement is, described radio frequency LDMOS device is N-type device, described first conduction type is P type, described second conduction type is N-type, the Implantation Energy of the N-type ion implantation technology of described first drift region is for being greater than 100KeV, the impurity of described first drift region, described second drift region and described 3rd drift region is phosphorus, and the tectal impurity of described contra-doping is boron; Or, described radio frequency LDMOS device is P type device, described first conduction type is N-type, described second conduction type is P type, the Implantation Energy of the P type ion implantation technology of described first drift region is for being greater than 50KeV, the impurity of described first drift region, described second drift region and described 3rd drift region is boron, and the tectal impurity of described contra-doping is phosphorus.

Device of the present invention adopts the drift region of horizontal non-uniform doping, the doping content of first drift region in raceway groove end drift region and region one is lower, middle drift region i.e. the 3rd drift doping concentration secondly, the drain terminal drift region i.e. doping content of the second drift region is the highest, and there is contra-doping cover layer drain terminal drift region.Because the doping content of drain terminal drift region of the present invention is higher, the doping content that the drift region of device can be made total is higher, thus can reduce the source and drain conducting resistance of device.And the doping content of raceway groove end drift region is set to lower value due to the present invention, the electric field strength at raceway groove end drift region place can be reduced, like this can the hot carrier's effect of device more weak, improve device reliability.In addition, the contra-doping cover layer on surface, drain terminal drift region can help depletion drift region effectively, the exhausting expansion and can reduce source and drain parasitic capacitance, so the present invention can reduce the output capacitance of device of drift region.Middle drift region has higher-doped concentration relative to raceway groove end drift region, can realize, not affecting the electric field strength at raceway groove end drift region place thus increasing further the drive current of device under not affecting the condition of the reliability of device, reducing the conducting resistance of device.In a word, the present invention can reduce source and drain conducting resistance and the source and drain parasitic capacitance of device simultaneously, increases drive current, improves the radiofrequency characteristics of device, makes radio frequency LDMOS device of the present invention can obtain the high-performance of low on-resistance, low output capacitance, high drive current.

Accompanying drawing explanation

Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:

Fig. 1 is the structural representation of existing radio frequency LDMOS device;

Fig. 2 is the structural representation of embodiment of the present invention radio frequency LDMOS device;

Fig. 3 A-Fig. 3 J is the structural representation of radio frequency LDMOS device in each step of the embodiment of the present invention one method.

Embodiment

As shown in Figure 2, be the structural representation of embodiment of the present invention radio frequency LDMOS device; Embodiment of the present invention radio frequency LDMOS device comprises:

The heavily doped silicon substrate 1 of first conduction type.Be preferably, the doping content of described silicon substrate 1 is greater than 1e20cm ^-3.

The silicon epitaxy layer 2 of the first conduction type doping, this silicon epitaxy layer 2 is formed at described silicon substrate 1 on the surface.

First drift region 3, be made up of the second conductive type ion injection region be formed in the selection area of described silicon epitaxy layer 2, the degree of depth of top surface first drift region 3 equal, described with the top surface of described silicon epitaxy layer 2 of described first drift region 3 is less than the thickness of described silicon epitaxy layer 2.

Second conductive type ion injection technology of described first drift region 3 is that primary ions is injected, and this primary ions is injected and added that furnace anneal advances described first drift region 3 of formation; Or the second conductive type ion injection technology of described first drift region 3 is repeatedly the different ion implantation of Implantation Energy, the ion implanted region that repeatedly degree of depth that formed of ion implantation is different is directly connected to form after described first drift region 3 or ion implanted region furnace anneal that repeatedly degree of depth that formed of ion implantation is different advance and forms described first drift region 3.The ion implantation of described first drift region 3 adopts ability ion implantation to realize gradual impurity genesis analysis and darker drift region knot, alleviates the hot carrier's effect of device.The ion implantation of described first drift region 3 can be injected for autoregistration, can be to be injected by the non-self-aligned of lithographic definition.

Channel region 9, be made up of the first conductive type ion injection region be formed in the selection area of described silicon epitaxy layer 2, first side and the described channel region 9 of described first drift region 3 contact in the horizontal, and top surface and the degree of depth of equal, the described channel region 9 of the top surface of described silicon epitaxy layer 2 of described channel region 9 are less than or equal to the degree of depth of described first drift region 3.

Polysilicon gate 8, is formed at above described channel region 9, and between described polysilicon gate 8 and described silicon epitaxy layer 2, isolation has gate dielectric layer 7, and be preferably, the material of gate dielectric layer 5 is silica.Channel region 9 described in described polysilicon gate 8 cover part also extends to above described first drift region 3, and the surface, described channel region 9 covered by described polysilicon gate 8 is for the formation of raceway groove.

Source region 11, is made up of the second conduction type heavily doped region be formed in described channel region 9, the first side autoregistration of described source region 11 and described polysilicon gate 8.

Drain region 10, is made up of the second conduction type heavily doped region be formed in described first drift region 3, and the second side of described drain region 10 and described polysilicon gate 8 is separated by a lateral separation.In described source region 11, the surface of described drain region 10 and described polysilicon gate 8 is all formed with metal silicide 12.

Second drift region 4, be made up of the second conductive type ion injection region be formed in the subregion of described first drift region 3, the first side of described second drift region 4 and the first side of described first drift region 3 are separated by a segment distance, the second side of described second drift region 4 and described drain region 10 lateral contact.

Contra-doping cover layer 5, is formed with the first conduction type doped region forms by being formed at described second surface, drift region 4.The junction depth of described contra-doping cover layer 5 is less than 1/5 of the junction depth of described second drift region 4, and the bulk concentration of described contra-doping cover layer 5 is greater than 2 times of the bulk concentration of described second drift region 4.

3rd drift region 6, be made up of the second conductive type ion injection region be formed in the subregion of described first drift region 3, first side of described 3rd drift region 6 and the first side of described first drift region 3 are separated by a segment distance, the second side of described 3rd drift region 6 and the first side of described second drift region 4 contacts or the second side of described 3rd drift region 6 extend in described second drift region 4 make described 3rd drift region 6 and described second drift region 4 part overlapping.

The drift region of radio frequency LDMOS device is made up of described first drift region 3, described second drift region 4, described 3rd drift region 6 and described contra-doping cover layer 5.

Shielding dielectric layer 13, is formed on the side of the second side of described polysilicon gate 8 and end face and on the surface of described drift region.The described shielding dielectric layer 13 on the end face of described polysilicon gate 8 and described Metal-silicides Contact is positioned in the embodiment of the present invention.Be preferably, the material of described shielding dielectric layer 13 is silica, silicon nitride or silicon oxynitride.

Faraday shield layer 14, is formed on described shielding dielectric layer 13, and described faraday shield layer 14 covers the side of the second side of described polysilicon gate 8 and end face and the second side of described faraday shield layer 14 extends to above described drift region.

Region between the first side making the first side of described 3rd drift region 6 and described first drift region 3 is region one, and the described drift region in described region one is made up of the subregion of described first drift region 3; Second side of described polysilicon gate 8 is positioned at directly over described region one, and the second side of described faraday shield layer 14 is positioned at directly over described 3rd drift region 6 or the second side of described faraday shield layer 14 is positioned at directly over described second drift region 4; Also namely described faraday shield layer 14 can by the described 3rd all or part of covering in drift region 6, and do not covered described second drift region 4 or part covering, the part in described region one is covered by described polysilicon gate 8, part is covered by described faraday shield layer 14.

The doping content that doping content is greater than the doping content of described first drift region 3, the doping content of described 3rd drift region 6 is less than described second drift region 4 of described 3rd drift region 6; Be preferably: the bulk concentration of described first drift region 3 is 1e16cm ^-3~ 5e16cm ^-3; The bulk concentration of described second drift region 4 is 5e16cm ^-3~ 1e17cm ^-3; The bulk concentration of described 3rd drift region 6 is 2e16cm ^-3~ 6e16cm ^-3.The doping content of described first drift region 3 is for regulating the electric field strength in described region one, the doping content of described first drift region 3 is less, the hot carrier's effect in less, the described region one of electric field strength in described region one is less, and the reliability of described radio frequency LDMOS device is higher; The doping content of described second drift region 4 is for regulating the source and drain conducting resistance of described radio frequency LDMOS device, and the doping content of described second drift region 4 is larger, and the source and drain conducting resistance of described radio frequency LDMOS device is less; Described contra-doping cover layer 5 exhausting and reducing the source and drain parasitic capacitance of described radio frequency LDMOS device for increasing described second drift region 4; In addition, the existence of described contra-doping cover layer 5, can also realize not by described faraday shield layer 14 isolation between the drift region that covers and the described shielding dielectric layer 13 at top, electric charge in described shielding dielectric layer 13 and interfacial state can be eliminated on the impact of device, make the characteristic of device more stable.Described 3rd drift region 6 is the transitional region between described first drift region 3 and described second drift region 4, due to the reliability of device determined by the doping content of described first drift region 3, the output capacitance of device determines jointly by described second drift region 4 and described contra-doping cover layer 5, described 3rd drift region 6 can when not affecting the output capacitance of the reliability of device and device, the drive current of further increase device, reduces the conducting resistance of device.

The junction depth of described contra-doping cover layer 5 is less than 1/5 of the junction depth of described second drift region 4, and the bulk concentration of described contra-doping cover layer 5 is greater than 2 times of the bulk concentration of described second drift region 4.

Namely the structure of embodiment of the present invention radio frequency LDMOS device is applicable to N-type device, is also applicable to P type device.When embodiment of the present invention radio frequency LDMOS device is N-type device, described first conduction type is P type, described second conduction type is N-type, the Implantation Energy of the N-type ion implantation technology of described first drift region 3 is for being greater than 100KeV, the impurity of described first drift region 3, described second drift region 4 and described 3rd drift region 6 is phosphorus, and the impurity of described contra-doping cover layer 5 is boron.Or, when embodiment of the present invention radio frequency LDMOS device is P type device, described first conduction type is N-type, described second conduction type is P type, the Implantation Energy of the P type ion implantation technology of described first drift region 3 is for being greater than 50KeV, the impurity of described first drift region 3, described second drift region 4 and described 3rd drift region 6 is boron, and the impurity of described contra-doping cover layer 5 is phosphorus.

As shown in Fig. 3 A to Fig. 3 J, be the structural representation of radio frequency LDMOS device in each step of the embodiment of the present invention one method, for the manufacture of embodiment of the present invention device as shown in Figure 2, the manufacture method of the embodiment of the present invention one radio frequency LDMOS device comprises the steps:

Step one, as shown in Figure 3A, the heavily doped silicon substrate 1 of the first conduction type on the surface epitaxial growth form the silicon epitaxy layer 2 of the first conduction type doping.Be preferably, the doping content of described silicon substrate 1 is greater than 1e20cm ^-3.

Step 2, as shown in Figure 3 B, adopt the second conductive type ion injection technology in the selection area of described silicon epitaxy layer 2, form the first drift region 3, the selection area forming described first drift region 3 is defined by photoetching process, and the degree of depth of top surface first drift region 3 equal, described with the top surface of described silicon epitaxy layer 2 of described first drift region 3 is less than the thickness of described silicon epitaxy layer 2; The position of the first side of described first drift region 3 is the position that the channel region 9 of described first drift region 3 and follow-up formation contacts.

Second conductive type ion injection technology of described first drift region 3 is that primary ions is injected, and this primary ions is injected and added that furnace anneal advances described first drift region 3 of formation; Or the second conductive type ion injection technology of described first drift region 3 is repeatedly the different ion implantation of Implantation Energy, the ion implanted region that repeatedly degree of depth that formed of ion implantation is different is directly connected to form after described first drift region 3 or ion implanted region furnace anneal that repeatedly degree of depth that formed of ion implantation is different advance and forms described first drift region 3.The ion implantation of described first drift region 3 adopts ability ion implantation to realize gradual impurity genesis analysis and darker drift region knot, alleviates the hot carrier's effect of device.

Step 3, as shown in Figure 3 C, photoetching process is adopted to define the forming region of the second drift region 4, adopt the second conductive type ion injection technology in the forming region of described second drift region 4, form described second drift region 4, adopt the second conductive type ion injection technology to form contra-doping cover layer 5 on the surface of described second drift region 4; Described second drift region 4 is arranged in the subregion of described first drift region 3 and the first side of the first side of described second drift region 4 and described first drift region 3 an is separated by segment distance.The tectal junction depth of described contra-doping is less than 1/5 of the junction depth of described second drift region, and the tectal bulk concentration of described contra-doping is greater than 2 times of the bulk concentration of described second drift region.

Step 4, as shown in Figure 3 D, adopts photoetching process to define the forming region of the 3rd drift region 6, adopts the second conductive type ion injection technology in the forming region of described 3rd drift region 6, form described 3rd drift region 6; Described 3rd drift region 6 is arranged in the subregion of described first drift region 3, first side of described 3rd drift region 6 and the first side of described first drift region 3 are separated by a segment distance, the second side of described 3rd drift region 6 and the first side of described second drift region 4 contacts or the second side of described 3rd drift region 6 extend in described second drift region 4 make described 3rd drift region 6 and described second drift region 4 part overlapping.

The drift region of radio frequency LDMOS device is made up of described first drift region 3, described second drift region 4, described 3rd drift region 6 and described contra-doping cover layer 5; Region between the first side making the first side of described 3rd drift region 6 and described first drift region 3 is region one, and the described drift region in described region one is made up of the subregion of described first drift region 3.

The doping content that doping content is greater than the doping content of described first drift region 3, the doping content of described 3rd drift region 6 is less than described second drift region 4 of described 3rd drift region 6; Be preferably, the bulk concentration of described first drift region 3 is 1e16cm ^-3~ 5e16cm ^-3; The bulk concentration of described second drift region 4 is 5e16cm ^-3~ 1e17cm ^-3; The bulk concentration of described 3rd drift region 6 is 2e16cm ^-3~ 6e16cm ^-3.

The doping content of described first drift region 3 is less, and the reliability of less, the described radio frequency LDMOS device of electric field strength in described region one is higher; The doping content of described second drift region 4 is larger, and the source and drain conducting resistance of described radio frequency LDMOS device is less; Described contra-doping cover layer 5 exhausting and reducing the source and drain parasitic capacitance of described radio frequency LDMOS device for increasing described second drift region 4; Described 3rd drift region 6 is the transitional region between described first drift region 3 and described second drift region 4.

Step 5, as shown in FIGURE 3 E, be formed with the described silicon epitaxy layer 2 superficial growth gate dielectric layer 7 of described drift region.Be preferably, described gate dielectric layer 7 is gate oxide.

Step 6, as shown in FIGURE 3 E, carries out heavy doping at described gate dielectric layer 7 surface deposition polysilicon 8 to described polysilicon 8.

Step 7, as shown in FIGURE 3 E, adopts lithographic etch process to carry out first time etching to described polysilicon, this first time etching the described polysilicon of source side is removed, the border after described first time etches is the first side of the polysilicon gate 8 of follow-up formation.

Step 8, as illustrated in Figure 3 F, first conductive type ion that carries out in the selection area of described silicon epitaxy layer 2 injects the described channel region 9 of formation, the selection area forming described channel region 9 is defined by photoetching process and the first side autoregistration of the selection area of described channel region 9 and described polysilicon gate 8, described channel region 9 and described first drift region 3 adjacent in the horizontal, top surface and the degree of depth of equal, the described channel region 9 of the top surface of described silicon epitaxy layer 2 of described channel region 9 are less than or equal to the degree of depth of described first drift region 3.

Step 9, as shown in Figure 3 G, adopt lithographic etch process to carry out the described polysilicon gate 8 of second time etching formation to described polysilicon, described polysilicon gate 8 is as the grid of described radio frequency LDMOS device; Second side of described polysilicon gate 8 extends to above described first drift region 3 and the second side of described polysilicon gate 8 is positioned at directly over described region one; The surface, described channel region 9 covered by described polysilicon gate 8 is for the formation of raceway groove.

As shown in figure 3h, depositing silicide barrier oxide layer, lithographic etch process is adopted the described silicide barrier oxide layer in the region needing to form metal silicide 12 to be removed, depositing metal short annealing forms described metal silicide 12, described metal silicide 12 is positioned at the surface of described polysilicon gate 8 and the source region 9 of follow-up formation and surface, drain region 12.The formation process of metal silicide 12 described above is placed on before follow-up shielding dielectric layer 13 is formed to carry out, and the formation process of described metal silicide 12 also can be placed in follow-up step 14 carries out.

Step 10, as shown in fig. 31, at described silicon substrate 1 front deposition dielectric layer 13, and chemical wet etching is carried out to described shielding dielectric layer 13, after etching, described shielding dielectric layer 13 covers described silicon epitaxy layer 2 surface outside the end face of described polysilicon gate 8 and side surface and described polysilicon gate 8.

Step 11, as shown in figure 3j, at described shielding dielectric layer 13 surface deposition faraday shield layer 14.

Step 12, as shown in figure 3j, dry etch process is adopted to etch described faraday shield layer 14, after etching, described faraday shield layer 14 covers the side of the second side of described polysilicon gate 8 and end face and the second side of described faraday shield layer 14 extends to above described drift region, and the second side of described faraday shield layer 14 is positioned at directly over described 3rd drift region 6, or the second side of described faraday shield layer 14 is positioned at directly over described second drift region 4, also namely described faraday shield layer 14 can by the described 3rd all or part of covering in drift region 6, described second drift region 4 is not covered or part covering, the part in described region one is covered by described polysilicon gate 8, part is covered by described faraday shield layer 14.Second side of faraday shield layer 14 described in Fig. 3 J is positioned at directly over described second drift region 4, also namely described 3rd drift region 6 can all cover by described faraday shield layer 14, described second drift region 4 part covered, the part in described region one is covered by described polysilicon gate 8, part is covered by described faraday shield layer 14.

Step 13, as shown in Figure 2, carries out the second conduction type heavy doping ion and injects and form source region 11 and drain region 10, the first side autoregistration of described source region 11 and described polysilicon gate 8; Second side of described drain region 10 and described polysilicon gate 8 is separated by a lateral separation and the second side of described second drift region 4 and described drain region 10 lateral contact.

Step 14, when not carrying out forming described metal silicide 12 processing step in step 9, can to carry out in this step; Silicide barrier oxide layer is adopted to define the forming region of metal silicide 12, depositing metal silicide 12 annealed alloy, described metal silicide 12 is formed at described source region 11, described drain region 10 and not by described polysilicon gate 8 surface that described faraday shield layer 14 covers.

Step 15, carry out deep etching, described deep trouth is through described source region 11, described channel region 9 and described silicon epitaxy layer 2 and enter into described silicon substrate 1; In described deep trouth, fill metal form described dark contact hole, described source region 11, described channel region 9, described silicon epitaxy layer 2 and described silicon substrate 1 are electrically connected by described dark contact hole.

Namely the structure of the radio frequency LDMOS device manufactured by the embodiment of the present invention one method is applicable to N-type device, is also applicable to P type device.When radio frequency LDMOS device is N-type device, in the embodiment of the present invention one method, described first conduction type is P type, described second conduction type is N-type, the Implantation Energy of the N-type ion implantation technology of described first drift region 3 is for being greater than 100KeV, the impurity of described first drift region 3, described second drift region 4 and described 3rd drift region 6 is phosphorus, and the impurity of described contra-doping cover layer 5 is boron.Or, when radio frequency LDMOS device is P type device, in the embodiment of the present invention one method, described first conduction type is N-type, described second conduction type is P type, the Implantation Energy of the P type ion implantation technology of described first drift region 3 is for being greater than 50KeV, and the impurity of described first drift region 3, described second drift region 4 and described 3rd drift region 6 is boron, and the impurity of described contra-doping cover layer 5 is phosphorus.

The embodiment of the present invention two method is also for the manufacture of embodiment of the present invention device as shown in Figure 2, adopt photoetching process but not self-registered technology forms described first drift region 3 in the embodiment of the present invention one method, and be adopt self-registered technology to form described first drift region 3 in the embodiment of the present invention two method, as shown in Figure 2, the manufacture method of the embodiment of the present invention two radio frequency LDMOS device comprises the steps:

Step one, the heavily doped silicon substrate 1 of the first conduction type on the surface epitaxial growth formed first conduction type doping silicon epitaxy layer 2.Be preferably, the doping content of described silicon substrate 1 is greater than 1e20cm ^-3.

Step 2, at described silicon epitaxy layer 2 superficial growth gate dielectric layer 7.Be preferably, described gate dielectric layer 7 is gate oxide.

Step 3, heavy doping is carried out to described polysilicon 8 at described gate dielectric layer 7 surface deposition polysilicon 8.

Step 4, employing lithographic etch process carry out first time etching to described polysilicon, and this first time etches removes the described polysilicon of source side, and the border after described first time etches is the first side of the polysilicon gate 8 of follow-up formation.

Step 5, in the selection area of described silicon epitaxy layer 2 carry out first conductive type ion inject formed described channel region 9, the selection area forming described channel region 9 is defined by photoetching process and the first side autoregistration of the selection area of described channel region 9 and described polysilicon gate 8; Top surface and the degree of depth of equal, the described channel region 9 of the top surface of described silicon epitaxy layer 2 of described channel region 9 are less than the thickness of described silicon epitaxy layer 2.

Step 6, employing lithographic etch process carry out second time etching to described polysilicon and form described polysilicon gate 8, and described polysilicon gate 8 is as the grid of described radio frequency LDMOS device; Channel region 9 described in described polysilicon gate 8 cover part, the surface, described channel region 9 covered by described polysilicon gate 8 is for the formation of raceway groove.

Step 7, adopt the second conductive type ion injection technology in the selection area of described silicon epitaxy layer 2, form the first drift region 3, the selection area forming described first drift region 3 is defined by photoetching process and the selection area of described first drift region 3 and the second side autoregistration of described polysilicon gate 8; The degree of depth of top surface first drift region 3 equal, described with the top surface of described silicon epitaxy layer 2 of described first drift region 3 is less than the thickness of described silicon epitaxy layer 2 and the degree of depth of described channel region 9 is less than or equal to the degree of depth of described first drift region 3; First side and the described channel region 9 of described first drift region 3 contact in the horizontal, and the second side of described polysilicon gate 8 extends to above described first drift region 3.

Step 8, employing photoetching process define the forming region of the second drift region 4, adopt the second conductive type ion injection technology in the forming region of described second drift region 4, form described second drift region 4, adopt the second conductive type ion injection technology to form contra-doping cover layer 5 on the surface of described second drift region 4; Described second drift region 4 is arranged in the subregion of described first drift region 3 and the first side of the first side of described second drift region 4 and described first drift region 3 an is separated by segment distance.The tectal junction depth of described contra-doping is less than 1/5 of the junction depth of described second drift region, and the tectal bulk concentration of described contra-doping is greater than 2 times of the bulk concentration of described second drift region.

Step 9, employing photoetching process define the forming region of the 3rd drift region 6, adopt the second conductive type ion injection technology in the forming region of described 3rd drift region 6, form described 3rd drift region 6; Described 3rd drift region 6 is arranged in the subregion of described first drift region 3, first side of described 3rd drift region 6 and the first side of described first drift region 3 are separated by a segment distance, the second side of described 3rd drift region 6 and the first side of described second drift region 4 contacts or the second side of described 3rd drift region 6 extend in described second drift region 4 make described 3rd drift region 6 and described second drift region 4 part overlapping.

Depositing silicide barrier oxide layer, lithographic etch process is adopted the described silicide barrier oxide layer in the region needing to form metal silicide 12 to be removed, depositing metal short annealing forms described metal silicide 12, described metal silicide 12 is positioned at the surface of described polysilicon gate 8 and the source region 9 of follow-up formation and surface, drain region 12.The formation process of metal silicide 12 described above is placed on before follow-up shielding dielectric layer 13 is formed to carry out, and the formation process of described metal silicide 12 also can be placed in follow-up step 14 carries out.

Step 10, at described silicon substrate 1 front deposition dielectric layer 13, described shielding dielectric layer 13 covers described silicon epitaxy layer 2 surface outside the end face of described polysilicon gate 8 and side surface and described polysilicon gate 8.

Step 11, at described shielding dielectric layer 13 surface deposition faraday shield layer 14.

Step 12, dry etch process is adopted to etch described faraday shield layer 14, after etching, described faraday shield layer 14 covers the side of the second side of described polysilicon gate 8 and end face and the second side of described faraday shield layer 14 extends to above described drift region, and the second side of described faraday shield layer 14 is positioned at directly over described 3rd drift region 6, or the second side of described faraday shield layer 14 is positioned at directly over described second drift region 4, also namely described faraday shield layer 14 can by the described 3rd all or part of covering in drift region 6, described second drift region 4 is not covered or part covering, the part in described region one is covered by described polysilicon gate 8, part is covered by described faraday shield layer 14.Second side of faraday shield layer 14 described in Fig. 3 J is positioned at directly over described second drift region 4, also namely described 3rd drift region 6 can all cover by described faraday shield layer 14, described second drift region 4 part covered, the part in described region one is covered by described polysilicon gate 8, part is covered by described faraday shield layer 14.

Step 13, the second conduction type heavy doping ion of carrying out are injected and are formed source region 11 and drain region 10, the first side autoregistration of described source region 11 and described polysilicon gate 8; Second side of described drain region 10 and described polysilicon gate 8 is separated by a lateral separation and the second side of described second drift region 4 and described drain region 10 lateral contact.

Namely the structure of the radio frequency LDMOS device manufactured by the embodiment of the present invention two method is applicable to N-type device, is also applicable to P type device.When radio frequency LDMOS device is N-type device, in the embodiment of the present invention two method, described first conduction type is P type, described second conduction type is N-type, the Implantation Energy of the N-type ion implantation technology of described first drift region 3 is for being greater than 100KeV, the impurity of described first drift region 3, described second drift region 4 and described 3rd drift region 6 is phosphorus, and the impurity of described contra-doping cover layer 5 is boron.Or, when radio frequency LDMOS device is P type device, in the embodiment of the present invention two method, described first conduction type is N-type, described second conduction type is P type, the Implantation Energy of the P type ion implantation technology of described first drift region 3 is for being greater than 50KeV, and the impurity of described first drift region 3, described second drift region 4 and described 3rd drift region 6 is boron, and the impurity of described contra-doping cover layer 5 is phosphorus.

Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims

1. a radio frequency LDMOS device, is characterized in that, comprising:

The heavily doped silicon substrate of first conduction type;

The silicon epitaxy layer of the first conduction type doping, this silicon epitaxy layer is formed in described surface of silicon;

First drift region, be made up of the second conductive type ion injection region be formed in the selection area of described silicon epitaxy layer, the degree of depth of equal with the top surface of described silicon epitaxy layer, described first drift region of top surface of described first drift region is less than the thickness of described silicon epitaxy layer;

Channel region, be made up of the first conductive type ion injection region be formed in the selection area of described silicon epitaxy layer, first side and the described channel region of described first drift region contact in the horizontal, and the degree of depth of equal with the top surface of described silicon epitaxy layer, the described channel region of top surface of described channel region is less than or equal to the degree of depth of described first drift region;

Polysilicon gate, be formed at above described channel region, described polysilicon gate and described silicon epitaxy zone isolation have gate dielectric layer, and channel region described in described polysilicon gate cover part also extends to above described first drift region, and the described channel region covered by described polysilicon gate is surperficial for the formation of raceway groove;

Source region, is made up of the second conduction type heavily doped region be formed in described channel region, the first side autoregistration of described source region and described polysilicon gate;

Drain region, is made up of the second conduction type heavily doped region be formed in described first drift region, and the second side of described drain region and described polysilicon gate is separated by a lateral separation;

Second drift region, be made up of the second conductive type ion injection region be formed in the subregion of described first drift region, the first side of described second drift region and the first side of described first drift region are separated by a segment distance, the second side of described second drift region and described drain region lateral contact;

Contra-doping cover layer, is formed with the first conduction type doped region forms by being formed at described second surface, drift region;

3rd drift region, be made up of the second conductive type ion injection region be formed in the subregion of described first drift region, first side of described 3rd drift region and the first side of described first drift region are separated by a segment distance, the second side of described 3rd drift region and the first side of described second drift region contact or the second side of described 3rd drift region extend in described second drift region make described 3rd drift region and described second drift region portion overlapping;

The drift region of radio frequency LDMOS device is made up of described first drift region, described second drift region, described 3rd drift region and described contra-doping cover layer;

Shielding dielectric layer, is formed on the side of the second side of described polysilicon gate and end face and on the surface of described drift region;

Faraday shield layer, is formed on described shielding dielectric layer, and described faraday shield layer covers the side of the second side of described polysilicon gate and end face and the second side of described faraday shield layer extends to above described drift region;

Make the region between the first side of described 3rd drift region and the first side of described first drift region be region one, the described drift region in described region one is made up of the subregion of described first drift region; Second side of described polysilicon gate is positioned at directly over described region one, and the second side of described faraday shield layer is positioned at directly over described 3rd drift region or the second side of described faraday shield layer is positioned at directly over described second drift region;

2. radio frequency LDMOS device as claimed in claim 1, it is characterized in that: the tectal junction depth of described contra-doping is less than 1/5 of the junction depth of described second drift region, the tectal bulk concentration of described contra-doping is greater than 2 times of the bulk concentration of described second drift region.

3. radio frequency LDMOS device as claimed in claim 1, is characterized in that: the bulk concentration of described first drift region is 1e16cm ^-3~ 5e16cm ^-3; The bulk concentration of described second drift region is 5e16cm ^-3~ 1e17cm ^-3; The bulk concentration of described 3rd drift region is 2e16cm ^-3~ 6e16cm ^-3.

4. radio frequency LDMOS device as claimed in claim 1, it is characterized in that: described radio frequency LDMOS device is N-type device, described first conduction type is P type, and described second conduction type is N-type; Or described radio frequency LDMOS device is P type device, and described first conduction type is N-type, and described second conduction type is P type.

5. a manufacture method for radio frequency LDMOS device, is characterized in that, comprises the steps:

Step one, the heavily doped surface of silicon Epitaxial growth of the first conduction type formed first conduction type doping silicon epitaxy layer;

Step 2, adopt the second conductive type ion injection technology in the selection area of described silicon epitaxy layer, form the first drift region, the selection area forming described first drift region is defined by photoetching process, and the degree of depth of equal with the top surface of described silicon epitaxy layer, described first drift region of top surface of described first drift region is less than the thickness of described silicon epitaxy layer; The position of the first side of described first drift region is the position that the channel region adjoin of described first drift region and follow-up formation touches;

Step 3, employing photoetching process define the forming region of the second drift region, adopt the second conductive type ion injection technology in the forming region of described second drift region, form described second drift region, adopt the second conductive type ion injection technology to form contra-doping cover layer on the surface of described second drift region; Described second drift region is arranged in the subregion of described first drift region and the first side of the first side of described second drift region and described first drift region an is separated by segment distance;

Step 4, employing photoetching process define the forming region of the 3rd drift region, adopt the second conductive type ion injection technology in the forming region of described 3rd drift region, form described 3rd drift region; Described 3rd drift region is arranged in the subregion of described first drift region, first side of described 3rd drift region and the first side of described first drift region are separated by a segment distance, the second side of described 3rd drift region and the first side of described second drift region contact or the second side of described 3rd drift region extend in described second drift region make described 3rd drift region and described second drift region portion overlapping;

The drift region of radio frequency LDMOS device is made up of described first drift region, described second drift region, described 3rd drift region and described contra-doping cover layer; Make the region between the first side of described 3rd drift region and the first side of described first drift region be region one, the described drift region in described region one is made up of the subregion of described first drift region;

The doping content of described 3rd drift region is greater than the doping content of described first drift region, the doping content of described 3rd drift region is less than the doping content of described second drift region; The doping content of described first drift region is less, and the reliability of less, the described radio frequency LDMOS device of electric field strength in described region one is higher; The doping content of described second drift region is larger, and the source and drain conducting resistance of described radio frequency LDMOS device is less; Described contra-doping cover layer exhausting and reducing the source and drain parasitic capacitance of described radio frequency LDMOS device for increasing described second drift region; Described 3rd drift region is the transitional region between described first drift region and described second drift region;

Step 5, be formed with the described silicon epitaxy layer superficial growth gate dielectric layer of described drift region;

Step 6, heavy doping is carried out to described polysilicon at described gate dielectric layer surface deposition polysilicon;

Step 7, employing lithographic etch process carry out first time etching to described polysilicon, and this first time etches removes the described polysilicon of source side, and the border after described first time etches is the first side of the polysilicon gate of follow-up formation;

Step 8, in the selection area of described silicon epitaxy layer carry out first conductive type ion inject formed described channel region, the selection area forming described channel region is defined by photoetching process and the first side autoregistration of the selection area of described channel region and described polysilicon gate, described channel region and described first drift region adjacent in the horizontal, the degree of depth of equal with the top surface of described silicon epitaxy layer, the described channel region of top surface of described channel region is less than or equal to the degree of depth of described first drift region;

Step 9, employing lithographic etch process carry out second time etching to described polysilicon and form described polysilicon gate, and described polysilicon gate is as the grid of described radio frequency LDMOS device; Second side of described polysilicon gate extends to above described first drift region and the second side of described polysilicon gate and is positioned at directly over described region one; The described channel region covered by described polysilicon gate is surperficial for the formation of raceway groove;

Step 10, at described silicon substrate front deposition dielectric layer, described shielding dielectric layer covers the described silicon epitaxy layer surface outside the end face of described polysilicon gate and side surface and described polysilicon gate;

Step 11, at described shielding dielectric layer surface deposit faraday shield layer;

Step 12, employing dry etch process etch described faraday shield layer, after etching, described faraday shield layer covers the side of the second side of described polysilicon gate and end face and the second side of described faraday shield layer extends to above described drift region, and the second side of described faraday shield layer is positioned at directly over described 3rd drift region or the second side of described faraday shield layer is positioned at directly over described second drift region;

Step 13, the second conduction type heavy doping ion of carrying out are injected and are formed source region and drain region, the first side autoregistration of described source region and described polysilicon gate; Second side of described drain region and described polysilicon gate is separated by a lateral separation and the second side of described second drift region and described drain region lateral contact;

Step 14, depositing metal silicide annealed alloy, described metal silicide is formed at described source region, described drain region and not by described polycrystalline silicon gate surface that described faraday shield layer covers;

6. a manufacture method for radio frequency LDMOS device, is characterized in that, comprises the steps:

Step 2, at described silicon epitaxy layer superficial growth gate dielectric layer;

Step 3, heavy doping is carried out to described polysilicon at described gate dielectric layer surface deposition polysilicon;

Step 4, employing lithographic etch process carry out first time etching to described polysilicon, and this first time etches removes the described polysilicon of source side, and the border after described first time etches is the first side of the polysilicon gate of follow-up formation;

Step 5, in the selection area of described silicon epitaxy layer carry out first conductive type ion inject formed described channel region, the selection area forming described channel region is defined by photoetching process and the first side autoregistration of the selection area of described channel region and described polysilicon gate; The degree of depth of equal with the top surface of described silicon epitaxy layer, the described channel region of top surface of described channel region is less than the thickness of described silicon epitaxy layer;

Step 6, employing lithographic etch process carry out second time etching to described polysilicon and form described polysilicon gate, and described polysilicon gate is as the grid of described radio frequency LDMOS device; Channel region described in described polysilicon gate cover part, the described channel region covered by described polysilicon gate is surperficial for the formation of raceway groove;

Step 7, adopt the second conductive type ion injection technology in the selection area of described silicon epitaxy layer, form the first drift region, the selection area forming described first drift region is defined by photoetching process and the second side autoregistration of the selection area of described first drift region and described polysilicon gate; The degree of depth of equal with the top surface of described silicon epitaxy layer, described first drift region of top surface of described first drift region is less than the thickness of described silicon epitaxy layer and the degree of depth of described channel region is less than or equal to the degree of depth of described first drift region; First side and the described channel region of described first drift region contact in the horizontal, and the second side of described polysilicon gate extends to above described first drift region;

Step 8, employing photoetching process define the forming region of the second drift region, adopt the second conductive type ion injection technology in the forming region of described second drift region, form described second drift region, adopt the second conductive type ion injection technology to form contra-doping cover layer on the surface of described second drift region; Described second drift region is arranged in the subregion of described first drift region and the first side of the first side of described second drift region and described first drift region an is separated by segment distance;

Step 9, employing photoetching process define the forming region of the 3rd drift region, adopt the second conductive type ion injection technology in the forming region of described 3rd drift region, form described 3rd drift region; Described 3rd drift region is arranged in the subregion of described first drift region, first side of described 3rd drift region and the first side of described first drift region are separated by a segment distance, the second side of described 3rd drift region and the first side of described second drift region contact or the second side of described 3rd drift region extend in described second drift region make described 3rd drift region and described second drift region portion overlapping;

The drift region of radio frequency LDMOS device is made up of described first drift region, described second drift region, described 3rd drift region and described contra-doping cover layer; Make the region between the first side of described 3rd drift region and the first side of described first drift region be region one, the described drift region in described region one is made up of the subregion of described first drift region; Second side of described polysilicon gate is positioned at directly over described region one;

7. method as described in claim 5 or 6, is characterized in that: the tectal junction depth of described contra-doping is less than 1/5 of the junction depth of described second drift region, and the tectal bulk concentration of described contra-doping is greater than 2 times of the bulk concentration of described second drift region.

8. method as described in claim 5 or 6, is characterized in that: the second conductive type ion injection technology of described first drift region is that primary ions is injected, and this primary ions is injected and added that furnace anneal advances described first drift region of formation; Or the second conductive type ion injection technology of described first drift region is repeatedly the different ion implantation of Implantation Energy, the ion implanted region that repeatedly degree of depth that formed of ion implantation is different is directly connected to form after described first drift region or ion implanted region furnace anneal that repeatedly degree of depth that formed of ion implantation is different advance and forms described first drift region.

9. method as described in claim 5 or 6, it is characterized in that: described radio frequency LDMOS device is N-type device, described first conduction type is P type, described second conduction type is N-type, the Implantation Energy of the N-type ion implantation technology of described first drift region is for being greater than 100KeV, the impurity of described first drift region, described second drift region and described 3rd drift region is phosphorus, and the tectal impurity of described contra-doping is boron; Or, described radio frequency LDMOS device is P type device, described first conduction type is N-type, described second conduction type is P type, the Implantation Energy of the P type ion implantation technology of described first drift region is for being greater than 50KeV, the impurity of described first drift region, described second drift region and described 3rd drift region is boron, and the tectal impurity of described contra-doping is phosphorus.

10. method as described in claim 5 or 6, is characterized in that: the bulk concentration of described first drift region is 1e16cm ^-3~ 5e16cm ^-3; The bulk concentration of described second drift region is 5e16cm ^-3~ 1e17cm ^-3; The bulk concentration of described 3rd drift region is 2e16cm ^-3~ 6e16cm ^-3.