CN104701187A - Semiconductor assembly and method of making the same - Google Patents

Semiconductor assembly and method of making the same Download PDF

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Publication number
CN104701187A
CN104701187A CN201410568376.2A CN201410568376A CN104701187A CN 104701187 A CN104701187 A CN 104701187A CN 201410568376 A CN201410568376 A CN 201410568376A CN 104701187 A CN104701187 A CN 104701187A
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CN
China
Prior art keywords
chip
layer
radiating seat
intermediary layer
depression
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410568376.2A
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Chinese (zh)
Inventor
林文强
王家忠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yuqiao Semiconductor Co Ltd
Bridge Semiconductor Corp
Original Assignee
Yuqiao Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US14/449,201 external-priority patent/US20150115433A1/en
Application filed by Yuqiao Semiconductor Co Ltd filed Critical Yuqiao Semiconductor Co Ltd
Publication of CN104701187A publication Critical patent/CN104701187A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The invention relates to a semiconductor assembly with a built-in stopper, and a manufacturing method of the same. Accroding to one better embodiment, the method comprises arraning a semiconductor element onto a diaelectric layer by making a stopper serve as configuration guide member of the semiconductor element; adhering a reinforcement layer to the diaelectric layer; and forming a build-up circuit covering the semiconductor element, the stopper and the reinforcement layer to provide signal routing of the semiconductor element. Therefore, the stopper can accurately limit arrangement positions of the semiconductor element to avoid electrical connection failure between the semiconductor element and the build-up circuit.

Description

Semiconductor device with and preparation method thereof
Technical field
The invention relates to a kind of semiconductor device, espespecially a kind of have the chip that is embedded in radiating seat and be electrically connected to the semiconductor device of a composite base plate, with and preparation method thereof.
Background technology
Merge the electronic installation of mobility, communication and computing technique, challenge the calorifics in semiconductor packaging industry, electricity, external form and reliability.Although proposed multiple embedded with semi-conductor chip in circuit board or the method in moulding compound in document, but still had many performance related defects.For example, by U.S. Patent number the 8th, 742,589,8,735,222,8,679,963 and 8,453, in device disclosed by 323, the heat energy produced due to the chip be embedded into cannot the suitable discharge by heat insulator (as laminated sheet or moulding compound), therefore causes the problem that performance reduces.
In addition, described device utilizes micropore as the electric connection being embedded into chip, and due to chip, (such as, the thermal coefficient of expansion of silicon is about 2.6 × 10 -6k -1) and (such as, the thermal coefficient of expansion of epoxy laminated board is about 15 × 10 to increase tunic layer -6k -1) between thermal coefficient of expansion do not mate, and there is high stress problem in interior connection aspect.When the current densities in chip rises, the heat energy that this chip produces also can rise, thus the problem of significantly variations in temperature can be produced in the operation cycle, and thermal mismatching herein may make chip have the internal pressure of height, finally cause the breaking of chip, layering and plant failure.
In above-mentioned prepared group body structure, another obvious defect is that its chip be embedded into may in encapsulating or displacement in lamination process, and cause micropore metalization incomplete due to chip displacement, as U.S. Patent number the 8th, 501,544 and 7,935, described in 893, it is a further reduction electric connection quality, thus reduces reliability and the yield of prepared group body.
Based on above-mentioned reason, and described other reasons below, need a kind of new device of development at present badly, and under in the micropore not being used in I/O connection pad, connection is embedded into chip, improve the reliability of chip-scale, and restriction uses moulding compound and laminated sheet, with the serious problems avoiding the phenomenon of chip overheating to cause device electrical performance aspect.
Summary of the invention
The present invention develops in view of above situation, main purpose of the present invention is to provide a kind of semiconductor device, wherein a chip is interconnected by the intermediary layer of multiple projection and a low thermal coefficient of expansion (CTE), do not mate and location identification problem between chip and connection wire road to solve thermal coefficient of expansion, thus productive rate and its confidence level of semiconductor device can be improved.
Another object of the present invention is to provide semiconductor device, and its chip is packaged in a radiating seat, the heat energy produced with this chip that effectively sheds, thus can promote signal integrity and its electrical performance of this device.
According to previously described object, the present invention proposes a kind of semiconductor device with chip, radiating seat and a composite base plate, and this composite base plate comprises an inorganic intermediary layer and resin increasing layer circuit.This radiating seat of this chip coated, be to provide this chip one sinking path, (CTE-compensated) inorganic intermediary layer is compensated with this thermal coefficient of expansion be connected in this chip by projection, be to provide the fan-out route of this chip first level, the broken string of connection gasket this chip internal pressure can avoided by this and do not mated by thermal coefficient of expansion and cause.This resin adjacent to this radiating seat and this intermediary layer increases layer circuit, is to provide the fan-out route of the second level, and has the terminal connection pad of a patterned array, to mate the group body wiring board of another level.
The invention provides a kind of preparation method of semiconductor device, its step comprises: provide a chip; One inorganic intermediary layer is provided, this inorganic intermediary layer comprises multiple through hole, a first surface, a second surface, it is in contrast to this first surface, multiple first contact pad, it is on this first surface and multiple second contact pad, it is on this second surface, wherein, this through hole is electrically connected this first contact pad and this second contact pad; This chip is electrically connected in this first contact pad of this inorganic intermediary layer, to provide one chip-interposer element by multiple projection; There is provided a radiating seat, this radiating seat has a depression; Use an adhesive agent this chip one interposer element to be attached on this radiating seat, and this chip inserts in this depression, this inorganic intermediary layer extends laterally beyond this depression; Then form one and increase layer circuit on this second surface of this radiating seat and this inorganic intermediary layer, wherein, this increasing layer circuit is to be electrically connected to this second contact pad of this inorganic intermediary layer by multiple conductive blind holes of this increasing layer circuit.
Use unless otherwise expressly specified or between described step the term of " then " or described step to be must carry out in a specific order, the order of above-mentioned steps there is no the sequence be limited to above, and can change according to required design or resequence.
On the other hand, the present invention is to provide semiconductor equipment, it comprises a chip, an adhesive agent, a radiating seat and comprise an inorganic intermediary layer and a composite base plate increasing layer circuit, wherein, i () this chip is by multiple projection to be electrically connected this chip to the first contact pad on the first surface of this inorganic intermediary layer, and this chip is the depression being arranged in this radiating seat; (ii) this inorganic intermediary layer extends laterally beyond this depression, and this first surface of this inorganic intermediary layer is attached on a flat surfaces of this radiating seat, and this flat surfaces is adjacent to this depression opening and is extended laterally by this depression opening; (iii) this adhesive agent is this chip of contact and this radiating seat and this inorganic intermediary layer and this radiating seat, and between this chip and this radiating seat and between this inorganic intermediary layer and this radiating seat; And (iv) this increasing layer circuit is arranged on a second surface of this radiating seat and this intermediary layer, and this second contact pad be electrically connected to by a conductive blind hole of this increasing layer circuit on this second surface of this inorganic intermediary layer, wherein, this second surface is in contrast to this first surface.
According to the preparation method of semiconductor device of the present invention, there is multiple advantage, for example, this chip-interposer element was first formed before being attached at this radiating seat, firm being connected on this intermediary layer of this chip can be guaranteed, and disconnection problem (disconnection) intrinsic in micropore technique can be avoided.By chip-interposer element, this chip is inserted in this depression and there is advantage especially, the shape of this depression or the degree of depth or the amount for engaging this adhesion layer needed for this chip, not must precision control in special parameter.In addition, two steps forming this composite base plate are that when being of value to deposition increasing layer circuit, this intermediary layer can protect this to be embedded into chip.
Hereinafter, embodiment will be provided to describe enforcement aspect of the present invention in detail.Other advantages of the present invention and effect are by more remarkable by the content disclosed by the present invention.
Accompanying drawing explanation
With reference to annexed drawings, the present invention clearly understands by describing in detail of following preferred embodiment, wherein:
Fig. 1 and 2 is profile and the vertical view of the intermediary layer panel being respectively the embodiment of the present invention 1.
Fig. 3 is the profile being provided with the chip of projection thereon according to the embodiment of the present invention 1.
Fig. 4 and 5 is respectively according to the embodiment of the present invention 1, and chip is as shown in Figure 3 electrically connected to profile and the vertical view of the panel scale group body of the intermediary layer panel shown in Fig. 1 and 2.
Fig. 6 and 7 is respectively according to the embodiment of the present invention 1, the profile of the cut state of panel scale group body as shown in Figures 4 and 5 and vertical view.
Fig. 8 and 9 is respectively according to the embodiment of the present invention 1, corresponds to profile and the vertical view of the chip-interposer element of the cutter unit shown in Fig. 6 and 7.
Figure 10 and 11 is respectively profile according to the radiating seat of the embodiment of the present invention 1 and bottom view.
Figure 12 and 13 is respectively according in the embodiment of the present invention 1, adhesive agent is dispersed to the profile on the radiating seat as shown in Figure 10 and 11 and bottom view.
Figure 14 and 15 is respectively according in the embodiment of the present invention 1, the chip-interposer element shown in Fig. 8 and 9 is attached at the profile on the radiating seat shown in Figure 12 and 13 and bottom view.
Figure 16 and 17 is respectively according in the embodiment of the present invention 1, provides the profile of another adhesive agent in the structure shown in Figure 14 and Figure 15 and bottom view.
Figure 18 and 19 is respectively according in the embodiment of the present invention 1, the cutaway view remove unnecessary adhesive agent in the structure shown in Figure 16 and 17 and bottom view.
Figure 20 is according in the embodiment of the present invention 1, stacked layer is arranged at the structural profile shown in Figure 18.
Figure 21 is according in the embodiment of the present invention 1, arranges the profile of blind hole in the structure shown in Figure 20.
Figure 22 is according in the embodiment of the present invention 1, arranges the profile of wire in the structure shown in Figure 21.
Figure 23 is according in the embodiment of the present invention 1, stacked layer is arranged at the structural profile shown in Figure 22.
Figure 24 is according in the embodiment of the present invention 1, arranges the profile of blind hole in the structure shown in Figure 23.
Figure 25 is according in the embodiment of the present invention 1, arranges wire in the structure shown in Figure 24, to complete the profile of semiconductor device.
Figure 26 is the profile of the radiating seat according to the embodiment of the present invention 2.
Figure 27 is according in the embodiment of the present invention 2, adhesive agent is scattered in the profile in radiating seat as shown in figure 26.
Figure 28 is according in the embodiment of the present invention 2, the chip-interposer element shown in Fig. 8 is attached at the cutaway view on the radiating seat shown in Figure 27.
Figure 29 is according in the embodiment of the present invention 2, another adhesive agent is arranged at the structural cutaway view shown in Figure 28.
Figure 30 is according in the embodiment of the present invention 2, by the profile that adhesive agent remaining in the structure shown in Figure 29 removes.
Figure 31 is according in the embodiment of the present invention 2, stacked layer is arranged at the structural profile shown in Figure 30.
Figure 32 is according in the embodiment of the present invention 2, arranges the profile of blind hole in the structure shown in Figure 31.
Figure 33 is according in the embodiment of the present invention 2, arranges wire in the structure shown in Figure 32, to complete the profile of semiconductor device.
Figure 34 is the profile according to a multilayer board in the embodiment of the present invention 3.
Figure 35 is according in the embodiment of the present invention 3, forms the profile of configuration guiding element in the structure shown in Figure 34.
Figure 36 is according to a profile with the multilayer board of opening in the embodiment of the present invention 3.
Figure 37 is according in the embodiment of the present invention 3, forms the profile of configuration guiding element in the structure shown in Figure 36.
Figure 38 is according in the embodiment of the present invention 3, arranges a depression in the stepped construction shown in Figure 35 to complete the profile of radiating seat.
Figure 39 is according in the embodiment of the present invention 3, and chip-interposer element is attached at the profile on the radiating seat shown in Figure 38.
Figure 40 is according in the embodiment of the present invention 3, arranges a stacked layer in the structural profile shown in Figure 39.
Figure 41 is according in the embodiment of the present invention 3, arranges the profile of blind hole in the structure shown in Figure 40.
Figure 42 is according in the embodiment of the present invention 3, arranges wire in the structure shown in Figure 41 to complete the profile of semiconductor device.
Figure 43 is according in the embodiment of the present invention 4, has the section of structure of configuration guiding element on metallic plate.
Figure 44 is according in the embodiment of the present invention 4, arranges basalis on the metallic plate shown in Figure 43 to complete the profile of radiating seat.
Figure 45 is according in the embodiment of the present invention 4, and chip-interposer element is attached at the profile on the radiating seat shown in Figure 44.
Figure 46 is according in the embodiment of the present invention 4, arranges stacked layer in the structural profile shown in Figure 45.
Figure 47 is according in the embodiment of the present invention 4, arranges the profile of blind hole in the structure shown in Figure 46.
Figure 48 is according in the embodiment of the present invention 4, arranges wire in the structure shown in Figure 47 to complete the profile of semiconductor device.
Embodiment
Hereinafter, embodiment will be provided to describe enforcement aspect of the present invention in detail.Other advantages of the present invention and effect are by more remarkable by the content disclosed by the present invention.It should be noted that described annexed drawings is the accompanying drawing simplified, the component count shown in accompanying drawing, shape and size can be modified according to physical condition, and the configuration of assembly may be more complicated.Also can carry out otherwise practice or application in the present invention, and under not deviating from the condition of spirit that the present invention defines and category, can various change and adjustment be carried out.
Embodiment 1
Fig. 1-2 5 is preparation method's schematic diagrames of the semiconductor device of a preferred embodiment of the present invention, and wherein, this semiconductor device comprises chip, radiating seat and comprises the composite base plate of inorganic intermediary layer and resin increasing layer circuit.
As shown in figure 25, this semiconductor device 110 comprises an inorganic intermediary layer 11 ', chip 13, radiating seat 20 and a resin to increase layer circuit 30.This inorganic intermediary layer 11 ' and this chip 13 are that use first adhesive agent 191 and the second adhesive agent 193 are attached on this radiating seat 20, and wherein this chip 13 is embedded in the depression 211 of this radiating seat 20.This increasing layer circuit 30 covers this inorganic intermediary layer 11 ' and this radiating seat 20 by below, and be electrically connected to the second contact pad 114 of this inorganic intermediary layer 11 ' by the first conductive blind hole 317.
Fig. 1,3,4,6 and 8 implements in aspect according to the present invention one, prepares the generalized section of one chip-interposer element, and Fig. 2,5,7 and 9 be respectively Fig. 1,4, the top view of 6 and 8.
Fig. 1 and 2 is the profile and the vertical view that are respectively an intermediary layer panel 11, it comprises first surface 111, second surface 113, it is in contrast to this first surface 111, first contact pad 112, be on this first surface 111, the second contact pad 114, be on this second surface 113 and through hole 116, it is electrically connected this first contact pad 112 and this second contact pad 114.This intermediary layer panel 11 is made up of the inorganic material of high-tension coefficient, such as silicon, glass, pottery or graphite, and comprise the circuit of a patterning, is the thick spacing being fanned out to this second contact pad 114 by the fine pitch of this first contact pad 112.
Fig. 3 is the generalized section of the chip 13 being provided with projection 15.This chip 13 comprises a non-active face 133 of active surface 131, its be in contrast to this active surface 131 and an I/O connection pad 132 on this active surface 131.This projection 15 is arranged on this I/O connection pad 132 of this chip 13, and can be tin ball, principal column or copper post.
Fig. 4 and 5 is the profile and the top view that are respectively a plate gauge module body, and its chips 13 is electrically connected on this intermediary layer panel 11.Projection 15 can be used and by heat compression, reflow soldering or thermosonication bonding method, chip 13 is electrically connected to the first contact pad 112 of this intermediary layer panel 11.Or this projection 15 can be deposited in this first contact pad 112 of this intermediary layer panel 11 in advance, and then by this projection 15, chip 13 is electrically connected on this intermediary layer panel 11.In addition, filling glue 16 can be provided further to fill the gap between this intermediary layer panel 11 and this chip 13.
Fig. 6 and 7 is respectively the profile and the top view that this panel scale group body are cut into independent monolithic.This panel scale group body is to cut into this single chip-interposer element 10 along line of cut L.
Fig. 8 and 9 is the profile and the top view that are respectively this single chip-interposer element 10.In this figure, this chip-interposer element 10 comprises two chips 13, and it is electrically connected on the intermediary layer 11 ' of cutting.The size of the second contact pad 114 of intermediary layer 11 ' and connection pad spacing, the size and the connection pad spacing that are set to be greater than this chip I/O connection pad 132, this intermediary layer 11 ' can provide the fan-out route of this chip 13 first level, to guarantee that the increasing layer circuit of next level is connected with high yield.In addition, this intermediary layer 11 ', before the structure being connected to next level, also provides the electric connection between adjacent chips 13 in advance.
Figure 10 and 11 is the profile and the bottom view that are respectively the radiating seat 20 with a depression 211.This radiating seat 20 is prepared by forming a depression 211 in a metallic plate 21, and the thickness of this metallic plate 21 can be 0.1mm to 10mm, and can comprise copper, aluminium, stainless steel or its alloy.In this embodiment, the layers of copper of this metallic plate 21 to be a thickness be 2mm.Each depression 211 can be of different sizes and pocket depth.The scope of this pocket depth can be 0.05mm to 1.0mm.In this figure, this depression 211 is 0.26mm (to hold the chip of the 0.2mm with 0.05mm projection).
Figure 12 and 13 is respectively profile and the bottom view that the first adhesive agent 191 is scattered in the radiating seat 20 in depression 211.This first adhesive agent 191 is generally a heat transfer adhesive agent, and is scattered in the bottom of this depression 211.
Figure 14 and 15 uses this first adhesive agent 191 this chip-interposer element 10 to be attached at section of structure on this radiating seat 20 and bottom view.This chip 13 inserts in this depression 211, and this intermediary layer 11 ' is above this depression 211 and keeps at a distance with the peripheral edge of this radiating seat 20.
Figure 16 and 17 is respectively to fill space between this intermediary layer 11 ' and this radiating seat 20 with the second adhesive agent 193, and the section of structure extended in this depression 211 and bottom view.This second adhesive agent 193 is generally an electrical insulating property filler, and disperses the space that enters between this intermediary layer 11 ' and this radiating seat 20, and in this depression 211 remaining space.Therefore, the mechanicalness that this first adhesive agent 191 there is provided between this chip 13 and this radiating seat 20 links and hot link, and the mechanicalness that this second adhesive agent 193 is to provide between this chip 13 and this radiating seat 20 and between this intermediary layer 11 ' and this radiating seat 20 links.
Figure 18 and 19 removes the section of structure of unnecessary adhesive agent from flowing out between this intermediary layer 11 ' and this radiating seat 20 and bottom view.Or, the step removing unnecessary adhesive agent can be omitted, and its unnecessary adhesive agent is the part becoming this increasing layer circuit follow-up.
Figure 20 be from stacked in downward direction/be coated with balance layer 311,1 first insulating barrier 312 and the section of structure of a first metal layer 31 in this intermediary layer 11 ' and this radiating seat 20.This balance layer 311 is from contacting this radiating seat 20 in downward direction, and by this radiating seat 20 downward to extension, and side direction covers, around and homotype is coated in the sidewall of this intermediary layer 11 ', and extend laterally to the peripheral edge of this structure from this intermediary layer 11 '.This first insulating barrier 312 is in contact in downward direction and covers this second surface 113 and this balance layer 311 of this intermediary layer 11 ', and is extended laterally by this second surface 113 of this intermediary layer 11 ' and this balance layer 311.This first metal layer 31 is by lower contact and covers this first insulating barrier 312.In this figure, this balance layer 311 has the thickness of 0.2mm, and it is the thickness close to this intermediary layer 11 '; And this first insulating barrier 312 has the thickness of 50 microns usually.This balance layer 311 and this first insulating barrier 312 can be made up of epoxy resin, glass-epoxy resin, polyimides etc.In the present embodiment, this first metal layer to be a thickness be layers of copper of 25 microns.
Figure 21 is the structural profile schematic diagram with the first blind hole 313.This first blind hole 313 extends through this first metal layer 31 and this first insulating barrier 312, and be aligned in this second contact pad 114 of this intermediary layer 11 '.This first blind hole 313 is formed by various technology, and it comprises laser drill, plasma etching and photoetching technique, and usually has the diameter of 50 microns.Pulse laser can be used to improve laser drill usefulness, or, metal light cover and scanning type laser bundle can be used.For example, copper coin can first be etched to manufacture after a metal window irradiating laser again.
With reference to Figure 22, first wire 315 is formed on this first insulating barrier 312, its be by deposit one first coating 31 ' on this first metal layer 31 and deposition enter in this first blind hole 313, then this first metal layer 31 of patterning and this first coating 31 ' on it.Or, in aforesaid technique, when the first metal layer 31 not being laminated on this first insulating barrier 312, can this first insulating barrier 312 of substrate surfaces to form this first wire 315.This first wire 315 is downward to extension by this first insulating barrier 312, extend laterally on this first insulating barrier 312, and extending into this first blind hole 313 to form the first conductive blind hole 317 in upward direction, this first conductive blind hole 317 is these second contact pads 114 directly contacting this intermediary layer 11 '.Therefore, this first wire 315 can provide the horizontal signal route of both X or Y-direction, and provides vertical signal route by this first blind hole 313, and as the electric connection of this intermediary layer 11 '.
First coating 31 ' can utilize various technology with deposited monolayers or sandwich construction, and its method comprises plating, electroless-plating, evaporation, sputter and combination thereof.For example, first this structure is immersed in activator solution, make the first insulating barrier 312 produce catalyst with electroless copper to react, then using the coating thin copper layer of electroless-plating mode as crystal seed layer, be then formed on crystal seed layer with second layers of copper of plating mode by desired thickness.Or deposit copper electroplating layer on crystal seed layer before, this kind layer forms the crystal seed layer film as titanium/copper by sputtering way.Once reach required thickness, various technology patterning coating can be used, to form the first wire 315, it comprise wet etching, chemical etching, laser assisted etching and with the combination of etching light shield (not shown) defining the first wire 315.
For convenience of explanation, the first metal layer 31 and on the first coating 31 ' be represent with simple layer, because copper is that homogeneity is coated to, the boundary line (all illustrating with dotted line) of metal interlevel not easily may be discovered and even cannot discover, but boundary line between the first coating 31 ' and the first insulating barrier 312 is then clearly visible.
Figure 23 is by one second insulating barrier 322 and one second metal level 32 lamination/the coat structural profile schematic diagram on this first insulating barrier 312 and this first wire 315.This second insulating barrier 322 is between this first wire 315 of this first insulating barrier 312/ and this second metal level 32, and can be made up of epoxy resin, glass-epoxy resin, polyimides etc., and usually has the thickness of 50 microns.In the present embodiment, this second metal level 32 to be a thickness be layers of copper of 25 microns.Preferably, this first insulating barrier 312 and this second insulating barrier 322 are made up of identical material.
Figure 24 has the second blind hole 323 to appear the structural profile schematic diagram at the selected position of this first wire 315.This second blind hole 323 extends through this second metal level 32 and this second insulating barrier 322.As this first blind hole 313, this second blind hole 323 is formed by various technology, and it comprises laser drill, plasma etching and photoetching technique, and usually has the diameter of 50 microns.Preferably, this first blind hole 313 and this second blind hole 323 have identical size.
With reference to Figure 25, by deposit one second coating 32 ' on this second metal level 32 and deposition enter this second blind hole 323, then this second metal level 32 of patterning and this second coating 32 ' formed thereon, be formed at the second wire 325 on this second insulating barrier 322.Or, when the second metal level 32 not being laminated on this second insulating barrier 322 in previous processes, can this second insulating barrier 322 of substrate surfaces to form this second wire 325.This second wire 325 is from this second insulating barrier 322 downward to extension, extends laterally on this second insulating barrier 322, and extends into this second blind hole 323 to form second conductive blind hole 327 in electrical contact with this first wire 315 in upward direction.Preferably, this first wire 315 and this second wire 325 are made up of identical material and have identical thickness.
Therefore, as shown in figure 25, the semiconductor device 110 completed comprises an inorganic intermediary layer 11 ', chip 13, radiating seat 20 and a resin to increase layer circuit 30.In this figure, this increasing layer circuit 30 comprises balance layer 311,1 first insulating barrier 312, first wire 315,1 second insulating barrier 322 and second wire 325.This chip 13 is electrically connected on a prefabricated intermediary layer 11 ' by epitaxy technique, to prepare one chip-interposer element 10.Use first and second adhesive agent 191,193 to be attached on this radiating seat 20 by this chip-interposer element 10, wherein this chip 13 is seated in this depression 211, and this intermediary layer 11 ' extends laterally beyond this depression 211.The mechanicalness that this first adhesive agent 191 is to provide between this chip 13 with this radiating seat 20 is connected and heat transfer, and this second adhesive agent 193 is to provide between this chip with this radiating seat 20 and mechanicalness between this intermediary layer 11 ' and this radiating seat 20 is connected.This increasing layer circuit 30 is electrically connected to this intermediary layer 11 ', and it is directly contacted with this second contact pad 114 of this intermediary layer 11 ' by this first conductive blind hole 317, and do not have solder therebetween.Therefore, the interconnection route (routing interconnection) of this chip 13 provided by the composite base plate comprising this inorganic intermediary layer 11 ' and this resin increasing layer circuit 30, and the matched coefficients of thermal expansion interface between this inorganic intermediary layer 11 ' of this chip 13 and this composite base plate, the reliability of its device can be improved.
Embodiment 2
Figure 26-33 is according in another aspect of the present invention, preparation has the configuration guiding element be arranged on this depression, using the configuration guiding element as intermediary layer, and preparation method's generalized section of second half conductor means of the extra conductive blind hole contacted with this radiating seat.
In order to the object of brief description, any in embodiment 1 describes the same application part that can be incorporated into herein, and no longer repeats identical describing.
Figure 26 is a profile with the radiating seat 20 of the configuration guiding element 213 of the opening around this depression 211.This configuration guiding element 213 is by removing the selected part of this metallic plate 21 or being formed on this metallic plate 21 by patterned deposition one metal or plastic material.Usually by coating, etching or mechanicalness boring to form this configuration guiding element 213.Therefore, this configuration guiding element 213 is from this flat surfaces 212 adjacent to this radiating seat 20 of this depression opening downward to extension, and its thickness can be 5 to 200 microns.In this embodiment, thickness is this configuration guiding element 213 of 50 microns is the peripheral edges extending laterally to this radiating seat 20, and in it, peripheral edge conforms to four of the intermediary layer in follow-up setting sides.
Figure 27 is radiating seat 20 profile that one first adhesive agent 191 is scattered in its depression 211.This first adhesive agent 191 is generally a heat transfer adhesive agent, and is scattered in bottom this depression 211.
Figure 28 is the generalized section that this chip-interposer element 10 is attached on this radiating seat 20 by this first adhesive agent 191 of use.This intermediary layer 11 ' and this chip 13 are attached on this radiating seat 20, and this chip 13 inserts in this depression 211, and this configuration guiding element 213 is side direction alignment and the peripheral edge of this intermediary layer 11 ' close.This configuration guiding element 213 there is provided this intermediary layer allocation position accurately.This configuration guiding element 213 is these first surfaces 111 in extending beyond this intermediary layer 11 ' in downward direction, and is positioned at this intermediary layer 11 ' top, and four side surfaces of this intermediary layer 11 ' that aligns in lateral side direction.When this configuration guiding element 213 is four side surfaces being close to this intermediary layer 11 ' in lateral, and when being consistent with four side surfaces of this intermediary layer 11 ', prevent any unnecessary displacement of this chip-interposer element 10 caused because of adhesive agent solidification.Preferably, the gap between this intermediary layer 11 ' and this configuration guiding element 213 is about 5 to 50 microns.The attaching of this intermediary layer 11 ' also can not use configuration guiding element 213.Although because the size of this depression and the degree of depth are difficult to control, the allocation position of this chip-interposer element 10 cannot be accurately provided, so due to large contact pad size and the Large space of this intermediary layer 11 ', therefore be unlikely to make follow-up increasing in the technique of layer circuit in the upper formation of this intermediary layer 11 ' cause micropore connection error.
Figure 29 is that this second adhesive agent 193 is filled in space between this intermediary layer 11 ' and radiating seat 20, and more extends into the section of structure of this depression 211.This second adhesive agent 193 is the normally filling glue be electrically insulated, and is dispersed to the gap between this intermediary layer 11 ' and this radiating seat 20, and the remaining space in this depression 211.
Figure 30 removes the profile of overflow to the unnecessary adhesive agent on this configuration guiding element 213.Or can omit the step removing unnecessary adhesive agent, described unnecessary adhesive agent is a part for this increasing layer circuit becoming follow-up setting.
Figure 31 be balance layer 311,1 first insulating barrier 312 and a first metal layer 31 stacked/coat section of structure on this intermediary layer 11 ' and this radiating seat 20.This balance layer 311 contacts this radiating seat 20, and from this radiating seat 20 downward to extension, and side direction covering and homotype are coated in the sidewall of this intermediary layer 11 ', more extend laterally to the peripheral edge of this structure from this intermediary layer 11 '.This first insulating barrier 312 contacts and provides the mechanicalness between this first metal layer 31 with this intermediary layer 11 ' and between this first metal layer 31 with this balance layer 311 to be connected.
Figure 32 is the section of structure with the first blind hole 313,314.This first blind hole 313 extends through this first metal layer 31 and this first insulating barrier 312, and be aligned in this second contact pad 114 of this intermediary layer 11 '.In addition, the first extra blind hole 314 extends through this first metal layer 31, this first insulating barrier 312 and this balance layer 311, and be aligned in the selected part of this radiating seat 20.
With reference to Figure 33, first wire 315 is formed on this first insulating barrier 312, its be by deposit one first coating 31 ' on this first metal layer 31 and deposition enter in this first blind hole 313,314, then this first metal layer 31 of patterning and this first coating 31 ' on it and prepare.This first wire 315 is downward to extension from this first insulating barrier 312, extend laterally on this first insulating barrier 312, and extending into form this first conductive blind hole 317,318 in this first blind hole 313,314 in upward direction, this first conductive blind hole 317,318 directly contacts this second contact pad 114 of this intermediary layer 11 ' and the selected part of this radiating seat 20.Therefore, this first wire 315 can provide the signal route of this intermediary layer 11 ' and the grounding connection of this radiating seat 20.
Accordingly, as shown in figure 33, the semiconductor device 120 completed comprises increasing layer circuit 30 according to inorganic intermediary layer 11 ', chip 13, radiating seat 20 and resin.In this figure, this increasing layer circuit 30 comprises balance layer 311,1 first insulating barrier 312 and first wire 315.This chip 13 is electrically connected on a prefabricated intermediary layer 11 ' by epitaxy technique, to prepare one chip-interposer element 10.Use first and second adhesive agent 191,193 to be attached on this radiating seat 20 by this chip-interposer element 10, wherein this chip 13 is seated in this depression 211, and this intermediary layer 11 ' extends laterally beyond this depression 211.The mechanicalness that this first adhesive agent 191 is to provide between this chip 13 with this radiating seat 20 is connected and heat transfer, and this second adhesive agent 193 is to provide between this chip 13 with this radiating seat 20 and mechanicalness between this intermediary layer 11 ' and this radiating seat 20 is connected.The configuration guiding element 213 of this radiating seat 20 is these first surfaces 111 in extending beyond this intermediary layer 11 ' in downward direction, and near the peripheral edge of this intermediary layer 11 ' to provide this intermediary layer 11 ' accurate setting position.This increasing layer circuit 30 is electrically connected to this intermediary layer 11 ' and this radiating seat 20 by this first conductive blind hole 317,318, and this first conductive blind hole 317,318 directly contacts with this second contact pad 114 of this intermediary layer 11 ' and the selected position of this radiating seat 20.
Embodiment 3
Figure 34-42 is according in another enforcement aspect of the present invention, and preparation has the preparation method generalized section of multilayer board as the another semiconductor device of radiating seat.
In order to the object of brief description, any in above-described embodiment describes the same application part that can be incorporated into herein, and no longer repeats identical describing.
Figure 34 and 35 is according to the present invention, forms the generalized section of a configuration guiding element on the dielectric layer of a multilayer board.
Figure 34 is the profile of the multilayer board comprising metallic plate 21, dielectric layer 23 and a metal level 25.This dielectric layer 23 is arranged between this metallic plate 21 and this metal level 25.This dielectric layer 23 is normally prepared by epoxy resin, glass epoxy resin, polyimides etc., and has the thickness of 50 microns.This metal level 25 is generally copper, but also can use copper alloy or other materials (as aluminium, stainless steel or its alloy).The thickness of this metal level 25 can be 5 to 200 microns.In this embodiment, this metal level 25 to be a thickness be copper coin of 50 microns.
Figure 35 is the section of structure that this configuration guiding element 253 is formed on this dielectric layer 23.This configuration guiding element 253 removes the selected position of this metal level 25 by photoetching process or Wet-type etching and is formed.In this embodiment, this configuration guiding element 253 comprises multiple metal projections of a rectangular array, is to be consistent with four of the intermediary layer of follow-up setting side surfaces.But the figure of this configuration guiding element is not limited to this, and can be various figure, with the displacement avoiding the intermediary layer of follow-up setting unnecessary.For example, this configuration guiding element 253 can comprise a continuous or discrete batten, and is consistent with four sides of the intermediary layer of follow-up setting, two diagonal angles.
Figure 36 and 37 is another kind of method generalized sections forming a configuration guiding element on the dielectric layer of a multilayer board.
Figure 36 is the multilayer board profile with one group of opening 251.As mentioned above, this multilayer board comprises metallic plate 21, dielectric layer 23 and a metal level 25, and this opening 251 is selected part by removing this metal level 25 and is formed.
Figure 37 is the profile be formed at by configuration guiding element 253 on this dielectric layer 23.This configuration guiding element 253 by dispersion or printing one photosensitive plastic (as epoxy, polyimides) in or nonphotosensitive material among this opening 251, then remove bulk metal layer 25 and formed.At this, this configuration guiding element 253 comprises multiple resin projection and has a figure, with the displacement avoiding the intermediary layer of follow-up setting unnecessary.
Figure 38 is this radiating seat 20 with a depression 211.This depression 211 extends through this dielectric layer 23 and more extends into this metallic plate 21.
Figure 39 is the generalized section that one chip-interposer element 10 is attached on this radiating seat 20 by use one adhesive agent 194.In this figure, except it is installed in except on this intermediary layer 11 ' with one chip 13 extension, this chip-interposer element 10 is similar to shown in Fig. 5.This chip 13 is arranged in this depression 211, and this intermediary layer 11 ' is positioned on this depression, and its first surface 111 is attached on this dielectric layer 23.This chip 13 is by disperseing this adhesive agent 194 in the bottom of this depression 211, the chip 13 then inserting this chip-interposer element 10 in this depression 211, to be installed on this radiating seat 20.This adhesive agent 194 (is generally heat transfer adhesive agent, but not the adhesive agent that is electrically insulated) be in this depression 211, and compress through this chip 13, flow to the gap between this chip 13 and this depression 211 sidewall upward, and overflow is on the flat surfaces of this dielectric layer 23.Therefore, this adhesive agent 194 is around this this chip 13 be embedded into, and the part extruded is also as the adhesive agent attaching this intermediary layer 11 '.This configuration guiding element 253 extends from this dielectric layer 23, and extend beyond this first surface 111 of this intermediary layer 11 ' in upward direction, and the peripheral edge of this intermediary layer 11 ' close, to provide this intermediary layer 11 ' accurate allocation position.
Figure 40 be balance layer 311, first insulating barrier 312 and the first metal layer 31 stacked/coat section of structure on this intermediary layer 11 ' and this radiating seat 20.This balance layer 311 is contact and covers dielectric layer 23 and this intermediary layer 11 ' sidewall of this radiating seat 20.This first insulating barrier 312 contacts and provides the mechanicalness between this first metal layer 31 with this intermediary layer 11 ' and between this first metal layer 31 with this balance layer 311 to be connected.
Figure 41 is to provide the section of structure with the first blind hole 313.This first blind hole 313 extends through this first metal layer 31 and this first insulating barrier 312, and the second contact pad 114 of this intermediary layer 11 ' that aligns.
With reference to Figure 42, this first wire 315 is formed on this first insulating barrier 312, its be by deposit one first coating 31 ' on this first metal layer 31 and deposition enter in this first blind hole 313, then this first metal layer 31 of patterning and this first coating 31 ' on it and prepare.This first wire 315 is upward to extension from this first insulating barrier 312, extend laterally on this first insulating barrier 312, and in extending into form this first conductive blind hole 317 in this first blind hole 313 in downward direction, this first conductive blind hole 317 is these second contact pads 114 directly contacting this intermediary layer 11 '.Therefore, this first wire 315 can provide the signal route of this intermediary layer 11 '.
Accordingly, as shown in figure 42, the semiconductor device 130 completed comprises an inorganic intermediary layer 11 ', chip 13, radiating seat 20 and a resin to increase layer circuit 30.This chip 13 is electrically connected on a prefabricated intermediary layer 11 ' by epitaxy technique, to prepare one chip-interposer element 10.This radiating seat 20 comprises a depression 211, and this depression 211 extends through this dielectric layer 23, and extend into this metallic plate 21.This chip-interposer element 10 uses adhesive agent 194 and is attached on this radiating seat 20, and wherein this chip 13 is seated in this depression 211, and this intermediary layer 11 ' extends laterally beyond this depression 211.This adhesive agent 194 is around this chip 13 be embedded into, and its part extruded is contact and between this first surface and this dielectric layer 23 of this intermediary layer 11 ', using as the adhesive agent pasting intermediary layer 11 '.The configuration guiding element 253 of this radiating seat 20 is from this dielectric layer 23 upward to extension, and extends beyond this first surface 111 of this intermediary layer 11 ', and the peripheral edge of this intermediary layer 11 ' close, to provide this intermediary layer accurate setting position.This increasing layer circuit 30 is this first conductive blind hole 317 by directly contacting with this second contact pad 114 of this intermediary layer 11 ' and is electrically connected to this intermediary layer 11 '.
Embodiment 4
Figure 43 48 is according in another aspect of the present invention, is prepared in the depression of radiating seat the method schematic diagram of the semiconductor device with a configuration guiding element.
In order to the object of brief description, any in embodiment 1 describes the same application part that can be incorporated into herein, and no longer repeats identical describing.
Figure 43 is the section of structure forming configuration guiding element 213 on metallic plate 21.In the present embodiment, the layers of copper of this metallic plate 21 to be thickness be 1mm.This configuration guiding element 213 is by removing the selected part of this metallic plate 21 or being formed on this metallic plate 21 by patterned deposition one metal or plastic material.In this embodiment, this configuration guiding element 213 is the multiple metal projections comprising a rectangular array, is to be consistent with four of the intermediary layer of follow-up setting side surfaces.But the figure of this configuration guiding element is not limited to this, and can be various figure, with the displacement avoiding the intermediary layer of follow-up setting unnecessary.
Figure 44 comprises the profile that this configuration guiding element 213 inserts the radiating seat 20 of a through hole 221 of this basalis 22.This basalis 22 is laminated on this metallic plate 21, and wherein this configuration guiding element 213 is alignment and inserts the through hole 221 of this basalis 22.This basalis 22 can by resins such as epoxy, bismaleimide-triazine (BT), polyimides, or resin/glass composite formed.In this figure, the thickness of this basalis 22 is 0.21mm, with the projection of the chip and 0.05mm that meet 0.15mm.Therefore, a depression 211 can define due to this through hole 221 of this basalis 22 on this metallic plate 21, and this configuration guiding element 213 is the bottoms being positioned at this depression 211.
Figure 45 is the section of structure that one chip-interposer element 10 is attached on this radiating seat 20 by use adhesive agent 194.This intermediary layer 11 ' and this chip 13 are attached on this radiating seat 20, and this chip 13 inserts in this depression 211, and this to join guiding element 213 be that side direction is alignd the peripheral edge of this chip 13.This adhesive agent 194 is these chips 13 around being embedded into, and its part extruded be contact and between this intermediary layer 11 ' and this basalis 22.This configuration guiding element 213 is from the bottom of this depression 211 upward to extension, and extends beyond the non-active face 133 of this chip 13, and the peripheral edge of this chip 13 close, to provide this chip-interposer element 10 accurate setting position.
Figure 46 be balance layer 311, first insulating barrier 312 and the first metal layer 31 stacked/coat section of structure on this intermediary layer 11 ' and this radiating seat 20.This balance layer 311 contacts and covers this basalis 22 of this radiating seat 20 and the sidewall of this intermediary layer 11 '.This first insulating barrier 312 contacts and provides the mechanicalness between this first metal layer 31 with this intermediary layer 11 ' and between this first metal layer 31 with this balance layer 311 to be connected.
Figure 47 is to provide the section of structure of one first blind hole 313.This first blind hole 313 extends through this first metal layer 31 and this first insulating barrier 312, and be aligned in this second contact pad 114 of this intermediary layer 11 '.
With reference to Figure 48, first wire 315 be by deposit one first coating 31 ' on this first metal layer 31 and deposition enter in this first blind hole 313, then this first metal layer 31 of patterning and this first coating 31 ' formed thereon, and be formed at this first insulating barrier 312.This first wire 315 is upward to extension from this first insulating barrier 312, and extend laterally on this first insulating barrier 312, and in extending into this first blind hole 313 to form the first conductive blind hole 317 in downward direction, this first conductive blind hole 317 directly contacts with this second contact pad 114 of this intermediary layer 11 '.
Accordingly, as shown in figure 48, the semiconductor device 140 completed comprises an organic intermediary layer 11 ', chip 13, radiating seat 20 and a resin to increase layer circuit 30.This chip 13 is electrically connected on a prefabricated intermediary layer 11 ' by epitaxy technique, to prepare one chip-interposer element 10.Use an adhesive agent 194 to be attached on this radiating seat 20 by this chip-interposer element 10, wherein this chip 13 is seated in this depression 211, and this configuration guiding element 213 is side direction alignment and the peripheral edge of this chip 13 close.This adhesive agent 194 is contact and provides between this intermediary layer 11 ' and this radiating seat 20, and the mechanicalness between this radiating seat 20 with this chip 13 is connected.This increasing layer circuit 30 is electrically connected to this intermediary layer 11 ' via this first conductive blind hole 317 and provides the route of its fan-out/interior access path.
Above-mentioned group body is only illustrative example, and the present invention still can pass through other various embodiments and realizes.In addition, above-described embodiment can based on design and the consideration of reliability, and being mixed with each other collocation uses or uses with other embodiment mix and match.This chip can be shared with other chips or not share depression.For example, single depression can hold one chip, and radiating seat can comprise the depression of multiple arrayed, to hold multiple chip.Or multiple chip can be arranged in single depression, therefore, a chip and other chips can be shared or not share intermediary layer, and such as, a chip can be electrically connected to an intermediary layer, or multiple chip can be connected on an intermediary layer.For example, can by four little die attach of 2x2 matrix on intermediary layer, and this intermediary layer can comprise extra contact pad, with the chip mat received and outside allocation.In addition, this increasing layer circuit can comprise extra wire to hold the extra contact pad of intermediary layer.
Embodiment described above, the semiconductor device of one uniqueness can represent excellent heat dispersion and reliability, and this semiconductor device comprises a chip, a radiating seat, an adhesive agent and comprises the composite base plate prepared by two steps that an inorganic intermediary layer and increases layer circuit.
This chip can be and encapsulates or unpackaged chip.In addition, this semiconductor subassembly can be bare chip or wafer-level packaging chip (wafer level packaged die) etc.
This radiating seat is extensible puts the peripheral edge of this device to provide the mechanical support of this chip, this inorganic intermediary layer and this increasing layer circuit.In a preferred embodiment, this radiating seat comprises a metallic plate, to provide the heat dissipation path of the chip necessity be embedded into.The thickness of this metallic plate can be 0.1mm to 10mm.The selection of the material of this metallic plate should be taken into account its heat dissipation characteristics, and can comprise copper, aluminium, stainless steel or its alloy.This radiating seat can be single or multiple lift structure, and comprises the depression extending into this metallic plate, or is defined by the through hole of the basalis be positioned on metallic plate.For example, this radiating seat can be the metallic plate with the depression be defined in wherein, and from the flat surfaces that this depression opening extends laterally.Or this radiating seat can be a stacked substrate, it comprises a metallic plate and a dielectric layer, and has one and extend through this dielectric layer and along extending into the depression of this metallic plate.In addition, this radiating seat can comprise the basalis that a metallic plate and has through hole, and its depression defined by the through hole of the basalis on this metallic plate.Therefore, the thermo-contact that the heat energy produced by chip can provide via the metallic plate bottom depression is surperficial and scatter and disappear.Have depression and be defined in radiating seat in metallic plate, the metal sidewall of this depression also can be used as the extra heat dissipation contact surface beyond depression metal bottom.
In addition, this radiating seat also can comprise a configuration guiding element arrange attaching with what provide this intermediary layer on this depression or in this depression.When in radiating seat, this configuration guiding element is on this depression, this configuration guiding element extends towards this second vertical direction from the flat surfaces adjacent to this radiating seat of depression, and this first surface extending beyond this intermediary layer (for convenience of description, the direction that this first surface of this intermediary layer faces is defined as the first vertical direction, and the direction that this second surface of this intermediary layer faces is defined as the second vertical direction).On the other hand, when in radiating seat, this configuration guiding element is in this depression, this configuration guiding element is that the metallic plate flat surfaces bottom this depression extends towards this second vertical direction, and extends beyond non-active of this extension in the second vertical direction.Therefore, this configuration guiding element is the peripheral edge of side direction alignment this intermediary layer close or this chip, to provide this intermediary layer allocation position accurately.
This configuration guiding element can be made up of metal, photosensitive plastic material or nonphotosensitive material.For example, this configuration guiding element can comprise copper, aluminium, nickel, iron, tin or its alloy.This configuration guiding element also can comprise epoxy resin or polyimides or be made up of epoxy resin or polyimides.In addition, this configuration guiding element can have the shape avoiding this intermediary layer or the unnecessary displacement of this chip.Such as, this configuration guiding element can comprise the protruded stigma of a continuous or discrete batten or an array, or this configuration guiding element can extend laterally to the peripheral edge of this radiating seat, and has the edge, inner edge be consistent with the peripheral edge of this intermediary layer or this chip.Specifically, this configuration guiding element can side direction to align four side surfaces of this intermediary layer or this chip, with define one with this intermediary layer or the same or analogous region of this chip form, to avoid the lateral displacement of this intermediary layer or this chip.For example, this configuration guiding element can along this intermediary layer or four sides of this chip, two diagonal angles or four corner alignment, and be consistent with it, and the gap between this intermediary layer and this configuration guiding element or between this chip and this configuration guiding element is preferably in the scope of about 5 to 50 microns.Therefore, this configuration guiding element be positioned on this intermediary layer or this chip can provide this chip-interposer element allocation position accurately.In addition, this configuration guiding element is the better height with 5 to 200 microns.
In this depression of this radiating seat, its opening can have the diameter large compared with bottom or size, and has the degree of depth of a 0.05mm to 1.0mm.For example, this depression can be flat taper (cut-offconical) or pyramid, from the bottom of this depression towards its be opened on the second vertical direction extend time, its radius or size with increase.Or this depression can be the cylindrical of mono-disperse.The opening of this depression or its bottom also can be circle, square or rectangle.
This adhesive agent can be dispersed to the bottom of this depression, and when insertion chip is in this depression, the adhesive agent of part is extruded this depression.Accordingly, this adhesive agent can contact and be embedded into chip around this in the depression of this radiating seat, and its part adhesive agent be extruded can contact and between this first surface of this intermediary layer and this flat surfaces of this radiating seat, this flat surfaces extends laterally from this depression opening.Or a heat transfer adhesive agent dispersibles to this depression, and be present in this depression when this chip of insertion is in this depression.One second adhesive agent (being generally electrical insulating property filler) dispersibles and is filled in the remaining space in this depression, and the space extended between this first surface of this intermediary layer and the flat surfaces of this radiating seat, this flat surfaces of this radiating seat extends laterally from this depression opening.Accordingly, this first adhesive agent mechanicalness provided between this chip with this radiating seat is connected and heat conduction connects, and the mechanicalness that this second adhesive agent is to provide between this intermediary layer with this radiating seat is connected.
This inorganic intermediary layer extends laterally beyond this depression, and can paste the flat surfaces to this radiating seat, and this flat surfaces of this radiating seat is this depression opening adjacent, and the first surface of this inorganic intermediary layer faces this radiating seat.This inorganic intermediary layer can be made up of materials such as silicon, glass, pottery or graphite, and has the thickness of 50 to 500 microns, and can comprise a wire pattern, is fanned out to the thick spacing of this second contact pad by the fine pitch of this first contact pad.Accordingly, this intermediary layer can provide the fan-out route/interior connection of the first level of this chip.In addition, this inorganic intermediary layer is made up of the material of elastic modulus usually, and (such as, the thermal coefficient of expansion of aluminium nitride is about 5.3 × 10 to have the thermal linear expansion coefficient (CTE) conformed to this chip -6k -1, the thermal coefficient of expansion of Pyrex is about 3.3 × 10 -6k -1), therefore can significantly compensate or reduce due to the coefficient of expansion do not mate pressure in caused chip and its electrically in the broken string that connects.
This increasing layer circuit be sedimentary facies adjacent to the second surface of this intermediary layer and this radiating seat, and the fan-out route/interior connection of the second level can be provided.In addition, this increasing layer circuit more can be electrically connected to this metal surface of this radiating seat by extra conductive blind hole, to provide ground connection.This increasing layer circuit comprises a balance layer, an insulating barrier and one or more wire.This balance layer is deposited on this radiating seat, and side direction covers the sidewall of this intermediary layer.This insulating barrier be deposited on this intermediary layer second surface and this balance layer on.This wire extends laterally on this insulating barrier, and extend through one or more blind hole in this insulating barrier, and to form one or more conductive blind hole, it directly contacts this second contact pad of this intermediary layer and optionally contacts this radiating seat.Accordingly, this wire directly can contact with this second contact pad the signal route providing this intermediary layer, thus the electric connection between this intermediary layer and this increasing layer circuit can not have a solder.
If necessary, this increasing layer circuit also can comprise extra insulating barrier, extra blind hole and extra wire.The outermost wire of this increasing layer circuit can have the terminal connection pad of a patterned array, to provide the group body of another level or another is as the electric connection of the electronic installation of semiconductor chip, plastic capsulation structure or another semiconductor group body.Therefore, can use as multiple connecting medias (the terminal connection pad as this increasing layer circuit) such as gold or tin balls, make the group body of next level or another electronic installation can be electrically connected to the chip be embedded into.
In herein, " covering " one word refer to vertical and/or side surface direction not exclusively and completely cover.Such as, under the state that the depression of intermediary layer faces upward direction, this metallic plate covers this chip in upward direction, no matter whether have another assembly (as: adhesive agent) between this metallic plate and this chip.
" alignment " one word mean the relative position of inter-module, whether no matter to keep at a distance each other between assembly or adjacent, or an assembly inserts and extends in another assembly.Such as, when imaginary horizontal line runs through this configuration guiding element and intermediary layer, configuration guiding element is that side direction is aligned in this intermediary layer, no matter whether there are other be supposed to the assembly that line runs through between configuration guiding element and intermediary layer, no matter and whether there is another run through intermediary layer but do not run through configuration guiding element or another runs through configuration guiding element but does not run through the vertual (virtual) horizontal line of intermediary layer.Similarly, the first blind hole is this second contact pad of this intermediary layer of alignment.
" close " one the word width that means the gap of inter-module be no more than maximum acceptable scope.Logical knowledge as known in the art, when configuring the gap between guiding element and intermediary layer and being narrow not, cause the site error of intermediary layer may exceed the restriction of acceptable worst error due to the lateral displacement of intermediary layer in gap, site error once intermediary layer exceedes greatest limit, laser beam then can not be used to aim at contact pad, and the electric connection mistake causing intermediary layer and increase between layer circuit.Therefore, according to the size of intermediary layer, via trial and error pricing to confirm the maximum acceptable scope in the gap between intermediary layer and configuration guiding element, thus can guarantee that contact pad aims at the precalculated position of intermediary layer in those skilled in the art.Thus, the term of " configuration guiding element is near the peripheral edge of intermediary layer " and " configuration guiding element is near the peripheral edge of chip " to refer between the peripheral edge of intermediary layer and configuration guiding element or is be too narrow to be enough to prevent the site error of intermediary layer from exceeding acceptable worst error to limit with the gap of chip.
" setting ", " stacked ", " attachment " and " attaching " one language comprise contact with the single or multiple supporting component of noncontact.Such as, intermediary layer is arranged on radiating seat, no matter intermediary layer is actual contact radiating seat or is separated by with an adhesive agent with radiating seat.
" electric connection " one word mean direct or indirect electric connection.Such as, the first wire provides the electric connection between the second connection pad of terminal connection pad and intermediary layer, no matter whether its first wire adjoins terminal connection pad or be electrically connected to the second wire via extra wire.
" the first vertical direction " and " the second vertical direction " not depends on the orientation of device, and all personages being familiar with this skill can understand the direction of its actual indication easily.Such as, the first surface of this intermediary layer faces the first vertical direction, and the second surface of intermediary layer faces the second vertical direction, and whether this and device are inverted irrelevant.Similarly, keeper aims at radiating seat in a lateral plane " side direction ", and whether this and wiring board are inverted, rotate or tilt to have nothing to do.Therefore, this first and second vertical direction is opposite each other and perpendicular to side surface direction, and the assembly of lateral alignment intersects at the lateral plane perpendicular to first and second vertical direction.Moreover when the second surface of intermediary layer is when facing upward direction, the first vertical direction is in downward direction, and the second vertical direction is upward direction; When the second surface of intermediary layer be face in downward direction time, the first vertical direction is upward direction, and the second vertical direction is in downward direction.
Semiconductor device of the present invention has multiple advantages.For example, chip is electrically connected on intermediary layer by the extension joint method known by such as hot pressing or reflow soldering etc., can avoid using when sticking together carrier as temporary joint in known method, the problem of intrinsic allocation position accuracy.This intermediary layer is generally be made up of the inorganic material of elastic modulus, and to provide the fan-out route/interior connection of the first level being embedded into chip, and resin increases fan-out route/interior connection that layer circuit is to provide the second level.When increase layer circuit be formed at there is large scale and pitch space intermediary layer on time, compared to general, increasing layer circuit is formed on the I/O pad of chip, and when not having the form of fan-out route, its product road can significantly promote.This configuration guiding element can provide intermediary layer accurate allocation position, therefore, must not controlled accurately for the shape and the degree of depth holding the depression of the chip be embedded into.Radiating seat can provide be embedded into chip heat radiation, electromagnetic shielding and protection against the tide, and chip, intermediary layer are provided and increase the mechanical support of layer circuit.Intermediary layer and to increase between layer circuit be directly electric connection, and do not have a solder, be conducive to high I/O value and high performance application.Device reliability thus prepared by method is high, price is plain and extremely applicable volume production.
The manufacture method of this case has high applicability, and is with the electrically connect of unique, the progressive various maturation of mode R. concomitans and mechanicalness connecting technology.In addition, the manufacture method of this case does not need expensive tool to implement.Therefore, compared to conventional packaging techniques, this manufacture method can significantly improving yield, yield, usefulness and cost benefit.
Embodiment described herein is the use for illustration, and wherein said embodiment may simplify or omit the assembly or step that the art known, in order to avoid fuzzy feature of the present invention.Similarly, for making accompanying drawing clear, accompanying drawing also may omit repetition or non-essential assembly and element numbers.

Claims (9)

1. a preparation method for semiconductor device, its step comprises:
One chip is provided;
One inorganic intermediary layer is provided, this inorganic intermediary layer comprises multiple through hole, a first surface, a second surface, it is in contrast to this first surface, multiple first contact pad, it is on this first surface and multiple second contact pad, it is on this second surface, wherein, described through hole is electrically connected described first contact pad and described second contact pad;
This chip is electrically connected in described first contact pad of this inorganic intermediary layer, to provide one chip-interposer element by multiple projection;
There is provided a radiating seat, this radiating seat has a depression;
Use an adhesive agent this chip-interposer element to be attached on this radiating seat, and this chip inserts in this depression, this inorganic intermediary layer extends laterally beyond this depression; Then
Form one and increase layer circuit on this second surface of this radiating seat and this inorganic intermediary layer, wherein, this increasing layer circuit by multiple conductive blind holes of this increasing layer circuit to be electrically connected to described second contact pad of this inorganic intermediary layer.
2. the preparation method of semiconductor device as claimed in claim 1, wherein, the step be electrically connected to by this chip in described first contact pad of this intermediary layer is carried out on a plate gauge mould, and perform unification step before this chip-interposer element is attached at the step of this radiating seat, to be separated multiple one chip-interposer element.
3. the preparation method of semiconductor device as claimed in claim 1, wherein, this radiating seat also comprises a configuration guiding element on this depression, and this chip-interposer element is attached at this radiating seat, this configuration guiding element side direction align this inorganic intermediary layer peripheral edge and near the peripheral edge of this inorganic intermediary layer.
4. the preparation method of semiconductor device as claimed in claim 3, wherein, provides the step of this radiating seat to comprise:
One metallic plate is provided;
Form this depression in this metallic plate; And
By the selected part that removes this metallic plate or by patterned deposition one metal or a plastic material on this metallic plate, form this configuration guiding element in the opening around this depression.
5. the preparation method of semiconductor device as claimed in claim 3, wherein, provides the step of this radiating seat to comprise:
There is provided a multilayer board, it comprises a dielectric layer and a metallic plate;
By the selected part that removes a metallic plate on this dielectric layer or by patterned deposition one metal or a plastic material on this dielectric layer, to form this configuration guiding element on this dielectric layer; And
Form this depression, this depression extends through this dielectric layer, and optionally extends into this metallic plate.
6. the preparation method of semiconductor device as claimed in claim 1, wherein, this radiating seat also comprises a configuration guiding element in this depression, and this chip-interposer element is attached on this radiating seat, this configuration guiding element side direction align this chip peripheral edge and near the peripheral edge of this chip.
7. the preparation method of semiconductor device as claimed in claim 6, wherein, provides the step of this radiating seat to comprise:
One metallic plate is provided;
By the selected part that removes this metallic plate or by patterned deposition one metal or a plastic material on this metallic plate, to form this configuration guiding element in a surface of this metallic plate; And
There is provided a basalis on this metallic plate, and this configuration guiding element is arranged in a through hole of this basalis.
8. the preparation method of semiconductor device as claimed in claim 1, wherein, the step forming this increasing layer circuit comprises: by the extra conductive blind hole of this increasing layer circuit to be electrically connected this radiating seat to this increasing layer circuit.
9. a semiconductor device, its method comprised the following steps and preparing:
One chip is provided;
One inorganic intermediary layer is provided, this inorganic intermediary layer comprises multiple through hole, a first surface, a second surface, it is in contrast to this first surface, multiple first contact pad, it is on this first surface and multiple second contact pad, it is on this second surface, wherein, described through hole is electrically connected described first contact pad and described second contact pad;
This chip is electrically connected in described first contact pad of this inorganic intermediary layer, to provide one chip-interposer element by multiple projection;
There is provided a radiating seat, this radiating seat has a depression;
Use an adhesive agent this chip-interposer element to be attached on this radiating seat, and this chip inserts in this depression, this inorganic intermediary layer extends laterally beyond this depression; Then
Form one and increase layer circuit on this second surface of this radiating seat and this inorganic intermediary layer, wherein, this increasing layer circuit is to be electrically connected to described second contact pad of this inorganic intermediary layer by multiple conductive blind holes of this increasing layer circuit.
CN201410568376.2A 2013-10-25 2014-10-23 Semiconductor assembly and method of making the same Pending CN104701187A (en)

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US14/449,201 US20150115433A1 (en) 2013-10-25 2014-08-01 Semiconducor device and method of manufacturing the same

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CN107210275A (en) * 2015-02-18 2017-09-26 高通股份有限公司 Systems, devices and methods for heat dissipation
CN107230640A (en) * 2016-03-24 2017-10-03 钰桥半导体股份有限公司 Have radiating seat and the heat-dissipating gain-type semiconductor subassembly and its preparation method of double build-up circuitries
CN108109974A (en) * 2016-11-25 2018-06-01 钰桥半导体股份有限公司 Semiconductor subassembly and production method with electromagnetic shielding and heat dissipation characteristics
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CN109698170A (en) * 2017-10-24 2019-04-30 长鑫存储技术有限公司 A kind of semiconductor package and its manufacturing method

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