CN104700044B - The fault-resistant injection attacks method and apparatus that register input and output are exchanged - Google Patents
The fault-resistant injection attacks method and apparatus that register input and output are exchanged Download PDFInfo
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Abstract
The invention discloses the fault-resistant injection attacks method and apparatus that a kind of register input and output are exchanged, the fault-resistant injection attacks method that register input and output are exchanged includes：S1, obtains the first maximum data width that can be run on target integrated circuit；S2, the second maximum data width needed when obtaining according to the first maximum data width and run AES on target integrated circuit；The multiple registers for needing to carry out input and output exchange are grouped by S3 according to the second maximum data width；S4, is transformed circuit at every group of multiple registers；S5, determines the control number of circuit progress data selection at every group of multiple registers；S6, determines that the data of circuit at every group of multiple registers select rule according to control number.The present invention enables to the register for storing AES data no longer to fix, and reduces the probability that failure is successfully injected into circuit, improves the security of circuit.
Description
Technical field
The present invention relates to Research on Integrated Circuit Security technical field, the fault-resistant that more particularly to a kind of register input and output are exchanged
The fault-resistant injection attacks device that injection attacks method and a kind of register input and output are exchanged.
Background technology
Today's society science and technology fast development, life is increasingly information-based, digitize and networking.Safety of the people to information
Property is also increasingly paid attention to, and this also promotes cipher processor to update.In order to preferably ensure the safety of information, cipher processor
The AES for not only needing security higher, while being also required to protect cipher processor in itself in hardware view.
For AES, by taking widely used Advanced Encryption Standard (AES) in the world as an example, AES is considered as
With very high security, if wanting to crack AES completely by mathematical way, time of cost will in terms of billions of years, because
This can consider that existing AES is safe in mathematics aspect.And in the hardware view of Cipher Processing, still face
Very big security threat, wherein fault injection attacks are exactly a kind of attack pattern implemented in hardware view, and its feature is energy
Enough instantaneous logical values changed on encryption processor encrypted circuit, cause the transient fault of circuit, ultimately result in encryption processor
The output ciphertext of mistake is produced, ciphertext is exported using some mistakes, attacker is possible to decode key or to key attack
Help is provided.
Attacker perform fault injection attacks when, it is necessary first to circuit carry out injection test enter, that is, to circuit each
Part all carries out the injection of certain number of times, in order to which output end can be reflected by determining the failure of which part in circuit,
The mistake output ciphertext of true-to-shape is produced, this process is referred to as the search phase.Can be close to exporting in attacker finds circuit
, it is necessary to right after the part of text generation specific effect (such a influence causes output ciphertext to be utilized to parse key by attacker)
The partial circuit carries out lasting injection, with the mistake output ciphertext for the enough quantity for obtaining attacker's needs, when acquisition foot
After the wrong ciphertext enough needed, fault injection attacks are completed, and this process is referred to as lasting injection stage.
In order to reduce the threat of fault injection attacks, cipher processor needs to take fault-resistant injection attacks measure.Tradition
The measure of fault-resistant injection attacks using redundancy and the mode that compares, testing mechanism is added in circuit, detection ciphering process is
It is no exception occur.It is broadly divided into：Information redundancy, time redundancy and hardware redundancy.Information redundancy refers to increasing within hardware
A part realizes that fault verification code waits the circuit of linearly or nonlinearly function to detect mistake within the specific limits.Time redundancy refers to
Be that ciphering process all or in part is repeated in time, two times result is identical just to be exported, and temporal is opened with performing
Pin brings the lifting of security.Hardware redundancy refers to be replicated all or part of of original circuit, and compares the two
As a result the security of output ciphertext is improved with this.
By traditional redundancy countermeasure above it is recognised that redundancy countermeasure is acted as to existing failure in circuit
With, but do not increase the difficulty of attacker's direct fault location, in order to preferably resistance fault injection attacks, it can be noted in failure
Entering the stage increases the difficulty of direct fault location, makes attacker be difficult to successfully inject failure.The object of attack one of fault injection attacks
As for the ALU (ALU) and register on computing array.And related research shows that register more holds than ALU
Easily implement injection, therefore, data, which are protected, in the direct fault location stage is to register just seems necessary.
The content of the invention
It is contemplated that at least solving one of technical problem in correlation technique to a certain extent.Therefore, the present invention
One purpose, which is that proposition is a kind of, can reduce the register that attacker carries out the probability of successfully injection by register pair circuit
The fault-resistant injection attacks method that input and output are exchanged.
It is another object of the present invention to the fault-resistant injection attacks device for proposing that a kind of register input and output are exchanged.
To achieve these goals, the fault-resistant injection attacks that register input and output according to embodiments of the present invention are exchanged
Method, comprises the following steps：S1, according to the computing array scale of target integrated circuit and the interconnection mode of the computing array,
The the first maximum data width that can be run on the target integrated circuit is obtained, wherein, the computing array includes multiple basic
Computing unit (PE), the PE includes the multiple MUXs (MUX) and the register being connected with the ALU being connected with ALU；
S2, according to the first maximum data width, obtains second needed when running AES on the target integrated circuit most
Big data width；S3, according to the second maximum data width to needing the multiple registers for carrying out input and output exchange to carry out
Packet；S4, is transformed circuit at every group of multiple registers, wherein, each register in improved circuit
Input and output end are connected with input MUX IN_MUX and output multi-channel selector OUT_MUX respectively；S5, it is determined that often
The corresponding multiple IN_MUX of circuit and multiple OUT_MUX carry out the control of data selection at multiple registers of group
Number；And S6, the corresponding multiple IN_MUX of circuit are determined at every group of multiple registers and multiple according to the control number
The data selection rule of the OUT_MUX.
The beneficial effect for the fault-resistant injection attacks method that register input and output according to embodiments of the present invention are exchanged is：
Enable to the register for storing AES data no longer to fix, reduce the probability that failure is successfully injected into circuit, carry
The high security of circuit.
Further, in one embodiment of the invention, the control number is produced by randomizer RNG.
Further, in one embodiment of the invention, multiple deposits that every group is determined according to the control number
Circuit corresponding multiple IN_MUX and multiple OUT_MUX data selection rule is specially at device：According to the control
Number processed determines the data selection rule of the corresponding multiple IN_MUX of circuit at every group of multiple registers；And according to multiple
The data selection rule of the IN_MUX determines corresponding multiple OUT_MUX data selection rule.
Further, in one embodiment of the invention, circuit is corresponding multiple described at every group of multiple registers
The OUT_MUX regular regular holding of data selection with multiple IN_MUX of data selection is synchronous to be changed.
Further, in one embodiment of the invention, determined according to the interconnection mode of the computing array to need
The multiple register for carrying out input and output exchange is by row packet or by column split.
Further, in one embodiment of the invention, the multiple registers for needing to carry out input and output exchange
To store the register of the ALU result of calculations.
To achieve these goals, the fault-resistant injection attacks that register input and output according to embodiments of the present invention are exchanged
Device, including：First maximum data width acquisition module, by the computing array scale according to target integrated circuit and it is described based on
The interconnection mode of array is calculated, the first maximum data width that can be run on the target integrated circuit is obtained, wherein, it is described to calculate
Array includes multiple PE, and the PE includes the multiple MUX being connected with ALU and the register being connected with the ALU；Second maximum number
According to width acquisition module, calculated for according to the first maximum data width, obtaining operation encryption on the target integrated circuit
The the second maximum data width needed during method；Grouping module, for according to the second maximum data width to need carry out it is defeated
The multiple registers for entering output exchange are grouped；Circuit modification module, is carried out for circuit at multiple registers to every group
Transformation, wherein, the input and output end of each register are respectively with inputting MUX IN_ in improved circuit
MUX is connected with output multi-channel selector OUT_MUX；Number determining module is controlled, for determining circuit at every group of multiple registers
Corresponding multiple IN_MUX and multiple OUT_MUX carry out the control number of data selection；And data selection rule is really
Cover half block, for determining at every group of multiple registers the corresponding multiple IN_MUX of circuit and multiple according to the control number
The data selection rule of the OUT_MUX.
Further, in one embodiment of the invention, the control number is produced by randomizer RNG.
Further, in one embodiment of the invention, the regular determining module of data selection specifically for：According to
The control number determines the data selection rule of the corresponding multiple IN_MUX of circuit at every group of multiple registers；And root
Determine that corresponding multiple OUT_MUX data select rule according to multiple IN_MUX data selection rule.
Further, in one embodiment of the invention, circuit is corresponding multiple described at every group of multiple registers
The OUT_MUX regular regular holding of data selection with multiple IN_MUX of data selection is synchronous to be changed.
Further, in one embodiment of the invention, the grouping module specifically for：According to the computing array
Interconnection mode come determine to need carry out input and output exchange the multiple register be by row packet or by column split.
Further, in one embodiment of the invention, the multiple registers for needing to carry out input and output exchange
To store the register of the ALU result of calculations.
The beneficial effect for the fault-resistant injection attacks device that register input and output according to embodiments of the present invention are exchanged is：
Enable to the register for storing AES data no longer to fix, reduce the probability that failure is successfully injected into circuit, carry
The high security of circuit.
Brief description of the drawings
Fig. 1 is the flow for the fault-resistant injection attacks method that register input and output according to embodiments of the present invention are exchanged
Figure；
Fig. 2 is the fault-resistant injection attacks method exchanged according to the register input and output of one specific embodiment of the present invention
Middle computing array schematic diagram；
Fig. 3 is the fault-resistant injection attacks method exchanged according to the register input and output of one specific embodiment of the present invention
Middle register is grouped schematic diagram；
Fig. 4 is the fault-resistant injection attacks method exchanged according to the register input and output of one specific embodiment of the present invention
Middle IN_MUX and the OUT_MUX regular schematic diagram of data selection；
Fig. 5 is the fault-resistant injection attacks method exchanged according to the register input and output of one specific embodiment of the present invention
PE operating diagram after middle transformation；And
Fig. 6 is that the square frame for the fault-resistant injection attacks device that register input and output according to embodiments of the present invention are exchanged shows
It is intended to.
Embodiment
Embodiments of the invention are described below in detail, the example of the embodiment is shown in the drawings, wherein from beginning to end
Same or similar label represents same or similar element or the element with same or like function.Below with reference to attached
The embodiment of figure description is exemplary, it is intended to for explaining the present invention, and be not considered as limiting the invention.
Below with reference to the accompanying drawings the fault-resistant injection attacks method that the register input and output of the embodiment of the present invention are exchanged is described
And the fault-resistant injection attacks device that register input and output are exchanged.
As shown in figure 1, the fault-resistant injection attacks method that register input and output according to embodiments of the present invention are exchanged, bag
Include following steps：
S1, according to the computing array scale and the interconnection mode of computing array of target integrated circuit, obtains the integrated electricity of target
First maximum data width of Lu Shangneng operations, wherein, computing array includes multiple PE, and PE includes the multiple MUX being connected with ALU
The register being connected with ALU.
In one embodiment of the invention, the first maximum data width is designated as wi.In order to express easily, wiCan be with PE
Number be unit.Therefore wiDepending on computing array scale and the interconnection mode of computing array.If for example, computing array is
16 rows 32 are arranged, and can after calculating using this one-way data interconnection mode of interconnection in the ranks of adjacent lines, the i.e. data per a line
To pass to next line, then now wi=32 (i.e. the columns of array).If computing array is interconnected using between the row of adjacent column
Pattern, then wiFor the line number of array, i.e. wi=16.
Fig. 2 is the fault-resistant injection attacks method exchanged according to the register input and output of one specific embodiment of the present invention
Middle computing array schematic diagram.As shown in Fig. 2 interconnection line of the computing array by multiple PE and therebetween is constituted, it is shown in figure
An array scale is to be connected between the computing array of 4 × 4 (4 rows 4 are arranged), PE by interconnection line.PE is selected when working by MUX
The data required calculation, pass data to ALU and carry out computing, the structure of computing is stored into register, finally afterwards
Data pass to other PE by interconnection line or are used as end product and export in register.
S2, according to the first maximum data width, obtains second needed when running AES on target integrated circuit most
Big data width.
In one embodiment of the invention, the second maximum data width is designated as wa, waCan also be using PE number to be single
Position.For example for conventional AES-128 AESs, each operation of AES is both for 128 bit packet datas
, then the maximum data width of each step of the AES is 128 bits.Assuming that PE processing width is 8 bits, obtain
To waBit=16 of=128 bits/8.
The multiple registers for needing to carry out input and output exchange are grouped by S3 according to the second maximum data width.
The fault-resistant injection attacks method that the register input and output of the present invention are exchanged can be used in cipher processor.For
Effective exchange of register input and output is realized, cipher processor needs some registers being grouped, specifically, in the present invention
One embodiment in, it is necessary to carry out input and output exchange multiple registers can for storage ALU result of calculations register.
It should be noted that cipher processor can also regard other registers in computing array as the deposit for needing to be grouped as needed
Device.
Further, in one embodiment of the invention, it can be determined according to the interconnection mode of computing array to need
The multiple registers for carrying out input and output exchange are by row packet or by column split.Specifically, in the reality of the present invention
Apply in example, if computing array uses this one-way data interconnection mode of interconnection in the ranks of adjacent lines, multiple register packets are pressed
Row is grouped., whereas if computing array using adjacent column row between interconnection mode, then multiple registers by row divided
Group.Further, in one embodiment of the invention, if multiple registers are by row packet when being grouped, then illustrate meter
Calculate array has w per a lineiIndividual register stores ALU result of calculation.Because target integrated circuit is needed when running AES
The the second maximum data width wanted is wa, to ensure independently to change between encryption data, the register of same a line is divided into waGroup.
During packet, it is 1-w that the register of same a line is numbered from left to righti, the register of same a line is organized into groups successively afterwards, for example, compiled
Number the 1st group is incorporated into for 1 register, the register that numbering is 2 is incorporated into the 2nd group ..., and numbering is wa+ 1 register is also incorporated into
1 group, until all registers are all organized into groups, then with same method by all storage ALU result of calculations in computing array
Register packet.
Fig. 3 is the fault-resistant injection attacks method exchanged according to the register input and output of one specific embodiment of the present invention
Middle register is grouped schematic diagram.8 PE are had in Fig. 3, numbering corresponds to PE1-PE8 respectively.Array shown in Fig. 3 is 2 × 4 (2
Row 4 is arranged) array, it is assumed that the array uses the interconnection mode in the ranks of adjacent lines, then wi=4, so that need to be by row during register packet
Packet.It is register 1-1 ..., register 1-4, register 2-1 ..., register 2-4 by the register number for needing to be grouped.Post
Which row first digit represents register-bit in storage numbering, and second digit represents numbering of the register in the row.
Assuming that the second maximum data width w needed when running AES on target integrated circuitaFor 2.The result of register packet
For it is one group that register 1-1, register 1-3, which are compiled, and packet numbering is 1-1.It is one group that register 1-2, register 1-4, which are compiled, packet
Numbering is 1-2.The packet situation of second row is similar, when simply packet numbering first digit is 2, is represented as point of the second row
Group.
S4, is transformed circuit at every group of multiple registers, wherein, each register is defeated in improved circuit
Enter end and output end respectively with input MUX IN_MUX and output multi-channel selector OUT_MUX to be connected.
S5, determines that circuit corresponding multiple IN_MUX and multiple OUT_MUX carry out data choosing at every group of multiple registers
The control number selected.
In one embodiment of the invention, control number can be produced by randomizer RNG.I.e. every group multiple
Circuit corresponding multiple IN_MUX and multiple OUT_MUX progress data selection are driven by randomizer (RNG) at register
Move, it is necessary to which circuit corresponding multiple IN_MUX and multiple OUT_MUX can also be by it at explanation, every group of multiple registers
The driving of his part, but for the effect that reaches fault-resistant injection attacks, there is provided the control to multiple IN_MUX and multiple OUT_MUX
Number is that MUX control signal is needed with certain randomness.Most AESs all using the calculation of wheel iteration, that is, pass through
Series of computation is operated to iterate and performs to improve the security of cryptographic algorithm, the operation for once needing to iterate is performed
Referred to as one wheel.Therefore, it is assumed that whenever AES has performed the operation of a wheel, RNG MUX control signal output in the present invention
Also change once, as long as in fact, the generation speed of RNG MUX control signal meets the demand of data processing, i.e. password
When processor handles different pieces of information, MUX control signal is changed.
S6, circuit corresponding multiple IN_MUX and multiple OUT_MUX at every group of multiple registers are determined according to control number
Data selection rule.
Input source before register is not connected with IN_MUX in the present invention is called input source, is not connected with OUT_MUX
Output object component before is output target.In order to ensure that encryption process is correctly carried out, in the implementation of the present invention
In example, the corresponding multiple OUT_MUX of the circuit regular data with multiple IN_MUX of data selection at every group of multiple registers
Selection rule can keep synchronous change, the input source data with multiple registers in group is still transmitted to output
Target.
Further, in one embodiment of the invention, circuit at every group of multiple registers is determined according to control number
Corresponding multiple IN_MUX and multiple OUT_MUX data selection rule are that step S6 is specifically as follows：
S61, determines that the data of the corresponding multiple IN_MUX of circuit at every group of multiple registers select to advise according to control number
Then.
Assuming that the quantity of multiple registers is n in a certain group, then multiple IN_MUX quantity is n.IN_MUX input comes
From in to should register with the original input of all registers (including itself) of group, the i.e. quantity of input source be also n.No
Plus in the case of limiting, each IN_MUX can select the data of any one in this n input source to be exported, and thus have
There may be the situation of input source loss of data (does not have IN_MUX to select the data of the input source to make in the presence of some input source
For output), so, it is necessary to which ensureing the data of each input source at any time has one during design IN_MUX data selection rules
Individual IN_MUX is selected and exported, while the complexity in order to reduce control, sets the possible data output choosing of this n IN_MUX
N kinds are selected as, this artificial specified possible situation of n kinds is at this moment needed, then obtains circuit correspondence at every group of multiple registers
Multiple IN_MUX data selection rule.
S62, selects rule to determine that corresponding multiple OUT_MUX data select rule according to multiple IN_MUX data.
Fig. 4 is the fault-resistant injection attacks method exchanged according to the register input and output of one specific embodiment of the present invention
Middle IN_MUX and the OUT_MUX regular schematic diagram of data selection.As shown in figure 4, after being grouped to register, it is necessary first to same
Circuit structure carries out certain transformation at register in group, it is assumed that include 3 registers, register in the packet of some register
1st, register 2 and register 3.By taking register 1 as an example, before not transforming, ALU1 operation result is stored in register 1, and
Exported eventually as OUT1.After transformation, the input of register 1 and output end have met IN_MUX1 and OUT_ respectively
MUX1.IN_MUX1 input data comes from ALU1-ALU3, outputs data to register 1.OUT_MUX1 input data comes from
Register 1- registers 3, output is exported as OUT1.The control signal that IN_MUX1 and OUT_MUX1 carries out data selection is come all
From in RNG output, control signal is to control number to be Integer N.Register 2 is similar with the transformation at register 3, no longer goes to live in the household of one's in-laws on getting married below
State.
It is corresponding many with register in group when further, due to determining that IN_MUX and OUT_MUX data select rule
Individual OUT_MUX data selection rule selects rule settings according to IN_MUX data, therefore firstly the need of the multiple deposits for determining every group
The corresponding multiple IN_MUX of circuit data selection rule at device, the quantity of data selection rule is 3.As shown in figure 4, IN_
MUX1-IN_MUX3 input comes from ALU1-ALU3.In the case of without limitation, each IN_MUX can be selected in this 3 ALU
The data of any one are exported, and thus there may exist the situation of ALU loss of datas and (do not have in the presence of some ALU
IN_MUX selects the ALU data as output), so, it is necessary to ensure at any time during design IN_MUX data selection rules
Each ALU data have an IN_MUX to select and export, while the complexity in order to reduce control, sets this 3 IN_
The possible data output selections of MUX are 3 kinds.At this moment artificial specifying in this 3 kinds of possible situations, Fig. 4 is needed to illustrate 3 kinds
IN_MUX data select situation.The data source of IN_MUX1, IN_MUX2, IN_MUX3 selection is respectively in the case of the first
ALU1、ALU2、ALU3.In the case of second IN_MUX1, IN_MUX2, IN_MUX3 select data source be respectively ALU2,
ALU3、ALU1.In the case of the third IN_MUX1, IN_MUX2, IN_MUX3 select data source be respectively ALU3, ALU1,
ALU2.IN_MUX1, IN_MUX2, IN_MUX3 data selection rule, which can be obtained, by these three situations corresponds to N mod 3 respectively
+1、(N+1)mod 3+1、(N+2)mod 3+1.Rule is selected according to obtained data, no matter what value MUX control signal N takes, most
Whole IN_MUX data selection is all one of above-mentioned three kinds of situations.
In addition, in order to ensure that ALU result of calculation outgoing position is constant, such as：ALU1 result is exported as OUT1.
OUT_MUX data selection situation needs to select situation to determine according to IN_MUX data.IN_MUX the first data selection
Situation is regular situation, therefore is illustrated by taking IN_MUX second of data selection situation as an example.In second of data selection feelings
Under condition, in ALU1 result deposit register 3, in order that data are exported as OUT1 in ALU1, OUT_MUX1 needs selection to post
The data of storage 3, similar, OUT_MUX2 needs the data of mask register 1, and OUT_MUX3 needs the number of mask register 2
According to.Situation is selected according to OUT_MUX data, OUT_MUX1, OUT_MUX2, OUT_MUX3 data selection rule point is can obtain
(- N) mod 3+1, (- N+1) mod 3+1, (- N+2) mod 3+1 are not corresponded to.
Fig. 5 is the fault-resistant injection attacks method exchanged according to the register input and output of one specific embodiment of the present invention
PE operating diagram after middle transformation.It is two registers shown in Fig. 5 as one group, what register input and output were exchanged shows
It is intended to, wherein MUX control signal is the random bit (1 or 0) that RNG is produced.When the random number that RNG is produced is 0, register
1 storage ALU1 result of calculation, register 2 stores ALU2 result of calculation.When the random number that RNG is produced is 1, register 1
ALU2 result of calculation is stored, register 2 stores ALU1 result of calculation, so that ALU result of calculation storage locations there occurs
Change, reduces the probability that failure is successfully injected into circuit, improves the security of circuit.
The beneficial effects of the invention are as follows：MUX is added by the input in register and output end to be deposited
Device actually enters the control of source and output target, so that the register of storage AES data is no longer fixed, reduces
Failure is successfully injected into the probability in circuit, improves the security of circuit.
In order to realize above-described embodiment, the present invention also proposes the fault-resistant injection attacks that a kind of register input and output are exchanged
Device, as shown in fig. 6, the fault-resistant injection attacks device that the register input and output are exchanged includes：First maximum data width
Acquisition module 10, the second maximum data width acquisition module 20, grouping module 30, circuit modification module 40, control number determine mould
Block 50 and the regular determining module 60 of data selection.Wherein, the first maximum data width acquisition module 10 is used for integrated according to target
The computing array scale and the interconnection mode of computing array of circuit, obtain the first maximum data that can be run on target integrated circuit
Width, wherein, computing array includes multiple PE, and PE includes the MUX being connected with ALU and the register being connected with ALU.Second is maximum
Data width acquisition module 20 is used for according to the first maximum data width, and obtain needs when AES is run on target integrated circuit
The the second maximum data width wanted.Grouping module 30 is used for according to the second maximum data width to needing to carry out input and output exchange
Multiple registers be grouped.Circuit modification module 40 is used to transform circuit at every group of multiple registers, wherein,
The input and output end of each register are respectively with inputting MUX IN_MUX and output multi-channel in improved circuit
Selector OUT_MUX is connected.Control number determining module 50 is used to determining the corresponding multiple IN_ of circuit at every group of multiple registers
MUX and multiple OUT_MUX carries out the control number of data selection.The regular determining module 60 of data selection is used to be determined according to control number
Circuit corresponding multiple IN_MUX and multiple OUT_MUX data selection rule at every group of multiple registers.
In one embodiment of the invention, the first maximum data width is designated as wi.In order to express easily, wiCan be with PE
Number be unit.Therefore wiDepending on computing array scale and the interconnection mode of computing array.If for example, computing array is
16 rows 32 are arranged, and can after calculating using this one-way data interconnection mode of interconnection in the ranks of adjacent lines, the i.e. data per a line
To pass to next line, then now wi- 32 (i.e. the columns of array).If computing array is using mutual gang mould between the row of adjacent column
Formula, then wiFor the line number of array, i.e. wi-16.In another embodiment of the present invention, the second maximum data width is designated as wa,
waCan also be in units of PE number.For example for conventional AES-128 AESs, each operation of AES is all
It is to be directed to 128 bit packet datas, then the maximum data width of each step of the AES is 128 bits.Assuming that
PE processing width is 8 bits, obtains waBit=16 of=128 bits/8.
The fault-resistant injection attacks device that the register input and output of the present invention are exchanged can be used in cipher processor.For
Effective exchange of register input and output is realized, cipher processor needs some registers being grouped, specifically, in the present invention
One embodiment in, it is necessary to carry out input and output exchange multiple registers can for storage ALU result of calculations register.
It should be noted that cipher processor as needed can also need other registers in computing array as grouping module 30
The register of packet.Further, in one embodiment of the invention, grouping module 30 is specifically for according to computing array
Interconnection mode come determine to need carry out input and output exchange multiple registers be by row packet or by column split.
Specifically, in one embodiment of the invention, if computing array uses this list of interconnection in the ranks of adjacent lines
To data interconnection pattern, multiple register packets are grouped by row., whereas if computing array is using mutual between the row of adjacent column
Gang mould formula, then multiple registers be grouped by row.Further, in one embodiment of the invention, if multiple deposits
Device is by row packet when being grouped, then illustrate that computing array has w per a lineiIndividual register stores ALU result of calculation.Due to mesh
The second maximum data width that mark integrated circuit needs when running AES is wa, to ensure independently to become between encryption data
Change, the register of same a line is divided into waGroup.During packet, it is 1-w that the register of same a line is numbered from left to righti, afterwards will be same
The register of a line is organized into groups successively, and the register that for example numbering is 1 is incorporated into the 1st group, and the register that numbering is 2 is incorporated into the 2nd
Group ..., numbering is wa+ 1 register is also incorporated into the 1st group, until all registers are all organized into groups, then with same method
By the register packet of all storage ALU result of calculations in computing array.
Further, in one embodiment of the invention, control number is produced by randomizer RNG.I.e. every group
Multiple registers at circuit corresponding multiple IN_MUX and multiple OUT_MUX carry out data select by randomizer
(RNG) drive, it is necessary to illustrate, circuit corresponding multiple IN_MUX and multiple OUT_MUX at every group of multiple registers
It can also be driven by miscellaneous part, but in order to reach the effects of fault-resistant injection attacks, there is provided to multiple IN_MUX and multiple
OUT_MUX control number is that MUX control signal is needed with certain randomness.Most AESs are all using the meter of wheel iteration
Calculation mode, i.e., perform to improve the security of cryptographic algorithm, execution once needs by iterating to series of computation operation
The operation iterated is referred to as a wheel.Therefore, the present invention in it is assumed that whenever AES has performed one take turns operation, RNG's
MUX control signal output also changes once, as long as in fact, the generation speed of RNG MUX control signal meets data processing
When demand, i.e. cipher processor handle different pieces of information, MUX control signal is changed.
Input source before register is not connected with IN_MUX in the present invention is called input source, is not connected with OUT_MUX
Output object component before is output target.In order to ensure that encryption process is correctly carried out, in the implementation of the present invention
In example, the corresponding multiple OUT_MUX of the circuit regular data with multiple IN_MUX of data selection at every group of multiple registers
Selection rule can keep synchronous change, the input source data with multiple registers in group is still transmitted to output
Target.
Further, in one embodiment of the invention, the regular determining module 60 of data selection is specifically for according to control
Number processed determines the data selection rule of the corresponding multiple IN_MUX of circuit at every group of multiple registers, and according to multiple IN_
MUX data selection rule determines corresponding multiple OUT_MUX data selection rule.Assuming that multiple registers in a certain group
Quantity is n, then multiple IN_MUX quantity is n.IN_MUX input come from to should register with group all deposits
The original input of device (including itself), the i.e. quantity of input source are also n.In the case of without limitation, each IN_MUX can be selected
Select the data of any one in this n input source to be exported, thus there may exist the situation of input source loss of data (i.e.
There is no IN_MUX to select the data of the input source as output in the presence of some input source), so design IN_MUX data selections
There is an IN_MUX to select and export, it is necessary to ensure the data of each input source at any time when regular, while in order to
The complexity of control is reduced, it is n kinds to set the possible data output selections of this n IN_MUX, at this moment needs this artificial specified n
Possible situation is planted, the data selection rule of the corresponding multiple IN_MUX of circuit at every group of multiple registers is then obtained.
The beneficial effects of the invention are as follows：MUX is added by the input in register and output end to be deposited
Device actually enters the control of source and output target, so that the register of storage AES data is no longer fixed, reduces
Failure is successfully injected into the probability in circuit, improves the security of circuit.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means to combine specific features, structure, material or the spy that the embodiment or example are described
Point is contained at least one embodiment of the present invention or example.In this manual, to the schematic representation of above-mentioned term not
Identical embodiment or example must be directed to.Moreover, specific features, structure, material or the feature of description can be with office
Combined in an appropriate manner in one or more embodiments or example.In addition, in the case of not conflicting, the skill of this area
Art personnel can be tied the not be the same as Example or the feature of example and non-be the same as Example or example described in this specification
Close and combine.
In addition, term " first ", " second " are only used for describing purpose, and it is not intended that indicating or implying relative importance
Or the implicit quantity for indicating indicated technical characteristic.Thus, define " first ", the feature of " second " can express or
Implicitly include at least one this feature.In the description of the invention, " multiple " are meant that at least two, such as two, three
It is individual etc., unless otherwise specifically defined.
Any process described otherwise above or method description are construed as in flow chart or herein, represent to include
Module, fragment or the portion of the code of one or more executable instructions for the step of realizing specific logical function or process
Point, and the scope of the preferred embodiment of the present invention includes other realization, wherein can not be by shown or discussion suitable
Sequence, including according to involved function by it is basic simultaneously in the way of or in the opposite order, carry out perform function, this should be of the invention
Embodiment person of ordinary skill in the field understood.
Represent in flow charts or logic and/or step described otherwise above herein, for example, being considered use
In the order list for the executable instruction for realizing logic function, it may be embodied in any computer-readable medium, for
Instruction execution system, device or equipment (such as computer based system including the system of processor or other can be held from instruction
The system of row system, device or equipment instruction fetch and execute instruction) use, or combine these instruction execution systems, device or set
It is standby and use.For the purpose of this specification, " computer-readable medium " can any can be included, store, communicate, propagate or pass
Defeated program is for instruction execution system, device or equipment or the dress for combining these instruction execution systems, device or equipment and using
Put.The more specifically example (non-exhaustive list) of computer-readable medium includes following：Electricity with one or more wirings
Connecting portion (electronic installation), portable computer diskette box (magnetic device), random access memory (RAM), read-only storage
(ROM), erasable edit read-only storage (EPROM or flash memory), fiber device, and portable optic disk is read-only deposits
Reservoir (CDROM).In addition, can even is that can be in the paper of printing described program thereon or other are suitable for computer-readable medium
Medium, because can then enter edlin, interpretation or if necessary with it for example by carrying out optical scanner to paper or other media
His suitable method is handled electronically to obtain described program, is then stored in computer storage.
It should be appreciated that each several part of the present invention can be realized with hardware, software, firmware or combinations thereof.Above-mentioned
In embodiment, the software that multiple steps or method can in memory and by suitable instruction execution system be performed with storage
Or firmware is realized.If, and in another embodiment, can be with well known in the art for example, realized with hardware
Any one of row technology or their combination are realized：With the logic gates for realizing logic function to data-signal
Discrete logic, the application specific integrated circuit with suitable combinational logic gate circuit, programmable gate array (PGA), scene
Programmable gate array (FPGA) etc..
Those skilled in the art are appreciated that to realize all or part of step that above-described embodiment method is carried
Rapid to can be by program to instruct the hardware of correlation to complete, described program can be stored in a kind of computer-readable storage medium
In matter, the program upon execution, including one or a combination set of the step of embodiment of the method.
In addition, each functional unit in each embodiment of the invention can be integrated in a processing module, can also
That unit is individually physically present, can also two or more units be integrated in a module.Above-mentioned integrated mould
Block can both be realized in the form of hardware, it would however also be possible to employ the form of software function module is realized.The integrated module is such as
Fruit is realized using in the form of software function module and as independent production marketing or in use, can also be stored in a computer
In read/write memory medium.
Storage medium mentioned above can be read-only storage, disk or CD etc..Although having been shown and retouching above
Embodiments of the invention are stated, it is to be understood that above-described embodiment is exemplary, it is impossible to be interpreted as the limit to the present invention
System, one of ordinary skill in the art can be changed to above-described embodiment, change, replace and become within the scope of the invention
Type.
Claims (12)
1. a kind of fault-resistant injection attacks method that register input and output are exchanged, it is characterised in that comprise the following steps：
S1, according to the computing array scale of target integrated circuit and the interconnection mode of the computing array, obtains the object set
The the first maximum data width that can be run on into circuit, wherein, the computing array includes multiple basic computational ele- ment PE, described
PE includes the multiple MUX MUX being connected with arithmetic logic unit alu and the register being connected with the ALU；
S2, according to the first maximum data width, obtains the needed when running AES on the target integrated circuit
Two maximum data width；
The multiple registers for needing to carry out input and output exchange are grouped by S3 according to the second maximum data width；
S4, is transformed circuit at every group of multiple registers, wherein, each register is defeated in improved circuit
Enter end and output end respectively with input MUX IN_MUX and output multi-channel selector OUT_MUX to be connected；
S5, determines that circuit corresponding multiple IN_MUX and multiple OUT_MUX enter line number at every group of multiple registers
According to the control number of selection；And
S6, the corresponding multiple IN_MUX of circuit are determined at every group of multiple registers and multiple described according to the control number
OUT_MUX data selection rule.
2. the fault-resistant injection attacks method that register input and output as claimed in claim 1 are exchanged, it is characterised in that described
Control number is produced by randomizer RNG.
3. the fault-resistant injection attacks method that register input and output as claimed in claim 1 are exchanged, it is characterised in that described
Circuit corresponding multiple IN_MUX and multiple OUT_MUX at every group of multiple registers are determined according to the control number
Data selection rule be specially：
Determine that the data of the corresponding multiple IN_MUX of circuit at every group of multiple registers select rule according to the control number
Then；And
Rule is selected to determine that corresponding multiple OUT_MUX data select rule according to multiple IN_MUX data.
4. the fault-resistant injection attacks method that register input and output as claimed in claim 3 are exchanged, it is characterised in that every group
Multiple registers at the corresponding multiple OUT_MUX of circuit regular data with multiple IN_MUX of data selection select
Select rule and keep synchronous change.
5. the fault-resistant injection attacks method that register input and output as claimed in claim 1 are exchanged, according to the calculating battle array
The interconnection mode of row come determine to need carry out input and output exchange the multiple register be by row packet or by row point
Group.
6. the fault-resistant injection attacks method that register input and output as claimed in claim 5 are exchanged, it is characterised in that described
Need to carry out multiple registers of input and output exchange to store the register of the ALU result of calculations.
7. the fault-resistant injection attacks device that a kind of register input and output are exchanged, it is characterised in that including：
First maximum data width acquisition module, for the computing array scale and the computing array according to target integrated circuit
Interconnection mode, obtain the first maximum data width that can be run on the target integrated circuit, wherein, the computing array bag
Include multiple basic computational ele- ment PE, the PE include the multiple MUX MUX being connected with arithmetic logic unit alu and with institute
State the connected registers of ALU；
Second maximum data width acquisition module, for according to the first maximum data width, obtaining the integrated electricity of target
The the second maximum data width needed when running AES on road；
Grouping module, for being entered according to the second maximum data width to the multiple registers for needing to carry out input and output exchange
Row packet；
Circuit modification module, is transformed for circuit at multiple registers to every group, wherein, it is each in improved circuit
The input and output end of the register are respectively with inputting MUX IN_MUX and output multi-channel selector OUT_MUX phases
Even；
Number determining module is controlled, for determining the corresponding multiple IN_MUX of circuit and multiple institutes at every group of multiple registers
State the control number that OUT_MUX carries out data selection；And
The regular determining module of data selection, for determining that circuit is corresponding more at every group of multiple registers according to the control number
The individual IN_MUX and multiple OUT_MUX data selection rule.
8. the fault-resistant injection attacks device that register input and output as claimed in claim 7 are exchanged, it is characterised in that described
Control number is produced by randomizer RNG.
9. the fault-resistant injection attacks device that register input and output as claimed in claim 7 are exchanged, it is characterised in that described
The regular determining module of data selection specifically for：
Determine that the data of the corresponding multiple IN_MUX of circuit at every group of multiple registers select rule according to the control number
Then；And
Rule is selected to determine that corresponding multiple OUT_MUX data select rule according to multiple IN_MUX data.
10. the fault-resistant injection attacks device that register input and output as claimed in claim 9 are exchanged, it is characterised in that every
The corresponding multiple OUT_MUX of the circuit regular data with multiple IN_MUX of data selection at multiple registers of group
Selection rule keeps synchronous change.
11. the fault-resistant injection attacks device that register input and output as claimed in claim 7 are exchanged, it is characterised in that institute
State grouping module specifically for：
Determined according to the interconnection mode of the computing array to need carry out input and output exchange the multiple register be
By row packet or by column split.
12. the fault-resistant injection attacks device that register input and output as claimed in claim 11 are exchanged, it is characterised in that institute
Stating needs to carry out multiple registers of input and output exchange to store the register of the ALU result of calculations.
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| CN1558587A (en) * | 2004-01-20 | 2004-12-29 | 海信集团有限公司 | Method for designing reconfigurable S cassette module of reconfigurable cipher code coprocessor |
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| CN103905182A (en) * | 2014-04-25 | 2014-07-02 | 东南大学 | Anti-attack method based on middle data storage position dynamic change and circuit implementation |
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| GB2424557A (en) * | 2005-03-24 | 2006-09-27 | Sony Uk Ltd | FPGA with hardware decryptor for configuration programme which adds second key to itself before re-encrypting and overwriting itself in memory when run |
| US8781112B2 (en) * | 2007-11-02 | 2014-07-15 | Certicom Corp. | Signed montgomery arithmetic |
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| CN1558587A (en) * | 2004-01-20 | 2004-12-29 | 海信集团有限公司 | Method for designing reconfigurable S cassette module of reconfigurable cipher code coprocessor |
| CN100565445C (en) * | 2004-01-27 | 2009-12-02 | Nxp股份有限公司 | Protection to power analysis attacks |
| US7536559B1 (en) * | 2005-05-05 | 2009-05-19 | Xilinx, Inc. | Method and apparatus for providing secure programmable logic devices |
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