CN104699531B - 3d芯片***中的电压下降缓解 - Google Patents

3d芯片***中的电压下降缓解 Download PDF

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CN104699531B
CN104699531B CN201310659511.XA CN201310659511A CN104699531B CN 104699531 B CN104699531 B CN 104699531B CN 201310659511 A CN201310659511 A CN 201310659511A CN 104699531 B CN104699531 B CN 104699531B
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CN104699531A (zh
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徐懿
胡杏
谢源
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F2119/12—Timing analysis or timing optimisation
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    • G06—COMPUTING; CALCULATING OR COUNTING
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Abstract

本发明涉及一种多芯片***以及一种用于在3D堆叠芯片***中调度线程的方法。该多芯片***包括垂直堆叠的、电耦合在一起的多个芯片；所述多个芯片中的每个芯片包括一个或多个核，所述多个芯片中的每个芯片进一步包括：至少一个电压违限感测单元，该至少一个电压违限感测单元与所述每个芯片的一个或多个核连接，该至少一个电压违限感测单元被配置成独立感测所述每个芯片中的每个核的电压违限；以及至少一个频率调谐单元，该至少一个频率调谐单元被配置成调谐所述每个芯片的每个核的频率，该至少一个频率调谐单元与所述至少一个电压违限感测单元连接。本发明中所描述的该多芯片***和该调度线程的方法具有多个优点，例如降低电压违限、缓解电压下降和节约功耗。

Description

3D芯片***中的电压下降缓解
技术领域
本发明总体涉及三维集成电路技术（3D芯片技术）。更具体地，本发明涉及3D堆叠式芯片***以及3D堆叠式多芯片***中的电压控制和调节。
背景技术
具有多个芯片通过硅穿孔（TSV）互连的垂直堆叠的集成电路是一种类型的3D集成电路技术，其技术提供了两个或更多的芯片的垂直堆叠，其提供了密集的、高速的接口。这种技术中的总电线长度是随着所使用的芯片层数的平方根来减少的，从而获得了性能的改善和互连的功率的降低。因此，三维集成技术在提供密集和高速通信接口以获得具有更低传输功率和更高性能方面是一种富有前景的技术。
图1显示了一种在倒装芯片技术中使用了硅穿孔的3D堆叠式多芯片封装100的示意结构。在该示意结构中，四层芯片110-140通过多个微小得连接物160依次叠置在封装基板150的上方。硅穿孔170用于传导电子和功率信号。功率从芯片外的电压调节器（未显示）通过控制熔塌芯片连接（C4）凸点180传送到底部芯片110，然后再经由硅穿孔170传送至上部的芯片120-140。热界面材料190、散热座191和散热片192依次设置在芯片140上方。
通常，3D堆叠式芯片由功率输送***供电，该功率输送***由两部分组成，即芯片外路径和芯片上网络。芯片外路径指的是从电压源和/或封装基板至芯片的功率输送路径。芯片上网络指的是芯片内的电阻、电感和/或电容网络，其通常包括位于输送路径上的寄生电阻、电感以及用于消除瞬态电压噪声的去耦电容。图2显示了一种3D堆叠式多芯片封装的功率输送网络的简化示意电路模型，其中用于3D堆叠式多芯片封装的功率输送***200包括芯片外路径210和芯片上网络220，它们都用图2所示的虚线框标示。芯片外路径210经功率从电压源经由凸点230传送到3D芯片上网络220。
尽管具有快速的层间数据传输速率、较低的传输功率和高的期间密度这些有益的特征，但是3D集成技术仍然面临着许多挑战，其中之一就是电源噪声。与相同尺寸的2D芯片相比，由于将多个芯片垂直堆叠，3D芯片具有更高的负载，从而会由于功率传输网络的不完善的寄生阻抗和电路的电流波动而导致更大的电压下降（voltage droop），损害电源完整性。电源完整性问题会导致时序错误，从而降低***的可靠性。
发明内容
在使用硅穿孔的3D集成电路中，多个芯片通过硅穿孔垂直连接以形成多层芯片，芯片间的连接物长度通常是3D芯片的连接物的0.1%-1%。如此短的连接物使得层间具有更紧密的电压相互影响。然而，芯片之间的、在垂直方向上的极短的距离会在垂直方向上导致很强的电压干涉。短的连接物会加重线程共振问题并且使得电压下降问题比2D芯片中更加严重。同时，在多线程应用中的诸如单程序多数据技术之类的计算技术会在线程间刺激破坏性的干涉（核共振）并加剧电压下降。
为了解决3D堆叠式芯片***中的上述问题，传统的解决方案是为最坏情况的电压下降分配充足的电压裕度。然而这种方案的成本很高，特别是在未来的3D芯片中，随着晶体管尺寸的减小和层数量的增加更是如此。现在的工作已经集中在物理设计和底层（floorplan）对3D功率传输网络中的电压下降的影响，并且观察到增加去耦电容或者硅穿孔密度能够缓和电压下降。然而，为了克服电源完整性问题，在芯片上设置足够的硅穿孔和去耦电容会导致成本过高。而且，为了有效降低电压噪声，去耦电容应当设置在有源电路旁边。因此，静态的解决方案并不是有效和灵活的，因为电路的状态是动态变化的。
因此，为了克服现有技术中的上述缺陷，本发明的多个方面提供了下面的技术方案。
在体现第一方面的实施例中，提供了一种多芯片***。该多芯片***包括垂直堆叠的、电耦合在一起的多个芯片。所述多个芯片中的每个芯片包括一个或多个核，所述多个芯片中的每个芯片进一步包括：至少一个电压违限感测单元，该至少一个电压违限感测单元与所述每个芯片的一个或多个核连接，该至少一个电压违限感测单元被配置成独立感测所述每个芯片中的每个核的电压违限；以及至少一个频率调谐单元，该至少一个频率调谐单元被配置成调谐所述每个芯片的每个核的频率，该至少一个频率调谐单元与所述至少一个电压违限感测单元连接。
在体现第二方面的第二实施例中，提供了一种用于3D堆叠芯片***的控制方法。所述3D堆叠芯片***包括多个垂直堆叠的芯片，每个所述芯片包括一个或多个核，该方法为所述3D堆叠芯片***中的每个芯片独立地执行，并且该方法包括：
（a）通过与所述核连接的至少一个电压违限感测单元感测所述芯片的一个或多个核中是否存在电压违限；（b）如果是，则通过与所述电压违限感测单元连接的频率调谐单元调谐该芯片的频率；以及（c）如果否，则继续进行步骤（a）。
在体现第三方面的第三实施例中，提供了一种用于在3D堆叠芯片***中调度线程的方法。该方法包括如下步骤：（a）估测来自一个或多个应用的多个线程的固有下降强度；（b）将该多个线程根据固有下降强度以降序排列并将它们排成队列；（c）选择该队列的头部的线程并将其设置在所述3D堆叠芯片***中的可获得的最低层芯片的可获得的核中；以及（d）检测所述队列是否已空，并重复步骤（c）直到所述队列变空。
在体现第四方面的第四实施例中，提供了一种用于在3D堆叠芯片***中调度线程的***。该***包括装置，用于估测来自一个或多个应用的多个线程的固有下降强度；装置，用于将该多个线程根据固有下降强度以降序排列并将它们排成队列；装置，用于选择该队列的头部的线程并将其设置在所述3D堆叠芯片***中的可获得的最低层芯片的可获得的核中；以及装置，用于检测所述队列是否已空。
下文详细描述了其它方面和实施例。
附图说明
附图以示例的方式图示了本发明，其并不构成对本发明的限制。在附图中相同的数字表示相同的部件，其中：
图1显示了现有技术中的3D堆叠式多芯片封装100的示例性结构；
图2显示了3D堆叠式芯片的功率传输***的示例性示意图；
图3为显示了运行16个Conocean和Waternsq应用的线程一百万个周期的最大和平均电压下降的示例性比较图；
图4为显示了多个线程分配的不同情形的示意图；
图5显示了在图4所示的不同情形中的相应的最严重情况的电压下降；
图6显示了一种多芯片***和根据一个示例性实施例的用于单独控制3D芯片的每一层的***；
图7为描述了根据一个示例性实施例的用于在3D堆叠式芯片***中调度线程的方法的流程图；
图8显示了一种示例性的包括核心层和缓存层的3D堆叠式芯片；以及
图9为显示了在执行本发明的线程调度方法之前和之后的每一芯片层的最严重的电压下降的比较图。
具体实施方式
下面将参照附图中所示的一些实施例具体描述本发明。在下文的描述中，描述了一些具体的细节以提供对本发明的更深的理解。然而，对于本领域的技术人员来说显而易见的是，即使不具有这些具体细节中的一些，本发明也可被实施。另一方面，一些公知的工艺步骤和/或结构没有被详细描述以避免不必要地使本发明变得难以理解。
本发明发现，在3D芯片中，电压下降（voltage droop（VD））在空间和时间上是非对称分布的。并且，电压下架的幅度随着不同的执行阶段而变化，以及最严重情况的（worst-case）电压下降比平均情况的（average-case）电压下降大得多，但是其很少发生。以Conocean和Waternsq应用的线程为例，图3为显示了运行16个Conocean和Waternsq应用的线程一百万个周期的最大和平均电压下降的比较图。通该图可知，关于运行16个Conocean线程或者Waternsq线程的情形，最严重情况的电压下降的幅度几乎是平均情况的电压下降幅度的四倍。然而，基于实验数据，大的电压下降（≤-130mv）的几率仅仅为0.6%。因此，为最严重电压下降分配大的电压裕度的功率效率是很低的。
线程多样化能够缓解水平干扰。如图3所示，在同时运行8个Conocean线程和8个Waternsq线程的情形中，即，运行混合线程，最严重情况的电压下降比上面的运行单一线程的情形小得多。这主要是因为在相同的平面内的相邻的线程之间存在的干涉所引起的。具有相似转换活动的线程会在活动的核心之间引入电压共振（voltage resonance），这被称为破坏性的干涉。由相同应用所引起的线程通常具有相似的功率曲线从而更可能产生破坏性的干涉。此外，当具有不同性质的线程被安排在一起的时候，电压温和的（voltage-mild）线程能够帮助稳定电压猛烈的（voltage-violent）线程。这种相互作用能够降低最严重情况的电压下降，因而被称为有益的干涉。因此，图3的前两个情形产生了比混合情形更高的电压下降。利用线程多样化以避免核心之间的破坏性的干涉能够消除大的电压下降。
在3D堆叠式芯片中，除了水平相互作用外，在位于不同层的芯片中的线程之间还存在垂直的相互作用，这也会影响电压下降。例如，图4和5为显示了垂直相互作用和水平相互作用是如何影响电压下降的示意图。图4为显示了线程分配的不同情形的示例图。线程A代表电压温和的线程，而线程B代表电压猛烈的线程，其正弦幅度是线程A的两倍。图5显示了图4中的不同情形的相应的最严重情况的电压下降。在图4的例子中，一共有4层芯片，即L0、L1、L2和L3，每层芯片具有四个核心。在情形（a）中，由相同应用引发的线程被分配在相同垂直方向的各个层中，而在情形（b）中，最猛烈的线程被安排在底部的层中。
图5显示了情形（a）和情形（b）的相应的电压下降。图4中显示的C0和C1代表每层中执行两种不同类型的线程的两个核心。情形（a）中的最严重情况的电压下降比情形（b）要大约14%，这表示垂直干涉比水平干扰效应更加严重并且会扩大电压下降。并且，在核心之间，情形（a）具有比情形（b）更大的层内间隙。C0的最严重情况的电压下降比C1大约大13%，这表明垂直干涉会潜在地扩大层内不平衡。
情形（b）、（c）、（d）和（e）被比较以显示电压猛烈线程位置对电压下降的影响。图4中的情形（c）中的方案是将最猛烈线程设置在最上层。情形（d）的方案是将电压猛烈的线程和电压温和的线程沿着垂直方向交错设置。情形（e）的方案是将不同类型的线程在水平方向和垂直方向都交错设置。
如图5所示，在四种线程调度方案中，情形（c）导致了最严重的电压下降。情形（b）在最严重情况的电压下降方面比其它几种情况要好，这表明将电压猛烈的线程远离电压源设置会导致更大的电压下降。虽然情形（e）尽量缓和水平和垂直方向的核心间的共振，但是电压猛烈的线程的位置设置对电压下架具有更到的影响，这被认为是线程调度的第一位的考虑因素。
此外，从图4和图5中可以看出，在一般情况的电压下降和最严重情况的电压下降之间存在着较大的差距。线程多样化能够缓解破坏性的水平干涉。垂直干涉比水平干涉更加严重。电压猛烈的线程的位置对电压下降具有更重要的影响，这是线程调度的主要考虑因素。
以上所述表明，在执行一个或多个应用期间，电压裕度在3D芯片中的分布是不均匀的。为整个芯片按照最严重情况的电压下降来分配电压裕度会浪费电力。因此，为了解决这个问题，本发明提供了一种新的用于3D芯片的硬件设计以避免浪费电压裕度。总体来说，该新的用于3D芯片的硬件设计为3D芯片配备了具有多个频率域的功率传输***，从而使得该3D芯片的每一层能够以独立的频率工作并且能够被单独控制。
作为示例性实施例，图6显示了一种用于独立控制3D芯片的每一层的硬件设计。根据图6，多芯片***600可包括多个芯片610，其中每个芯片包括电压违限感测单元620和频率调谐单元630。如图6所示，电压违限感测单元620可以是关键路径监测器（critical-pathmonitor（CPM））620。频率调谐单元630可以是数字锁相环（digital-phase locked loop（DPLL））630。此外，如图6所示，该多芯片***600还可包括性能监测器640和电压调节器650，性能监测器640被配置成周期性地监视该***的工作频率，该电压调节器650被配置成调节提供至多个芯片610的电压。
在图6所示的示例性实施例中，一共有四个芯片，即四层芯片。每个芯片包括四个核660。在其它实施例中，芯片和核心的数量并不限于图6所示，该多芯片***也可以包括更多或更少的芯片以及每个芯片也可以包括更多或更少的核。而且，除了核芯片外，该多芯片***还可以包括一个或多个叠置在核芯片之上或之下的缓存芯片。
在图6所示的示例性实施例中，每个芯片包括关键路径监测器，并且该芯片中的每个核与该芯片中的关键路径监测器620连接。该关键路径监测器还被进一步与相应的数字锁相环630连接。此外，每个数字锁相环进一步与性能监测器640连接，该性能监测器又与电压调节器650连接。
在图6所示的***中，功率从底部的层经由中间的层传输到上部的层。如上所述，在上部的芯片中的核比在下部的芯片中的核具有更大的电压下降，因为更长的功率传输路径消耗了更多的功率。底部的层与上部的层的最严重情况的电压下降相差30mv。此外，上层芯片中的电压违限的发生频率要高于下层芯片。为了缓解层间的干涉，图6中的层独立设计使得每一层在其合适的频率下工作，并且局部作出调节和恢复而不会影响到其它层。例如，当某一个核降低局部的频率以避免潜在的时序错误时，其它层将不会受到干扰并能全速执行。
为了解决电压违限问题，在图6的多芯片***，关键路径监测器的输出表示被监测的关键路径的时序裕度。时序延迟受到例如程序、热量、老化以及电压等多种因素的影响。热量和老化的影响比较缓慢，因此，大多数瞬时的时序违限与电压变化有关。因此，关键路径监测器的瞬时变化能够被解释为电压变化。为了节约功率，将本发明中的电压裕度根据一般情况的电压下降来设置，而不是根据最严重情况的电压下降来设置。一旦关键路径监测器在每个核中感测到电压违限，数字锁相环能够快速地调谐频率以避免时序错误。研究表明该快速的数字锁相环能够在几个周期内将峰值频率调低约7%。
此外，通过与所有的数字锁相环连接，该性能监测器640能够周期性地监测该多芯片***的平均工作频率以保持性能。另外，通过与数字锁相环连接，该性能监测器640能够监测该***的工作频率，但该工作频率超过上限时，表明该期限内电压裕度过量提供。但频率低于下限时，表明提供的电压不足而需要提高。然后，该电压调节器开始调节提供至3D芯片的相应电压。该调节分辨率可以提前设置，例如设置为6.25mv。一般需要几微秒来完成调节过程。
本发明还提供了一种用于在3D堆叠式芯片中调度线程的方法。如图5所示，不同的线程分布对电压下降具有不同的影响。因此，为了最小化最严重情况的电压下降以及电压违限的次数，每个线程的电压下降特性被量化。线程是电压猛烈的还是电压温和的可根据线程的固有下降强度（intrinsic droop intensity）来预测。电压猛烈的线程具有较高的固有下降强度，而电压温和的线程具有较低的固有下降强度。
本发明发现三个用于线程调度的指导方针：（1）将电压猛烈的线程设置在下面的层中（即，靠近功率传输***的层），否则其会在垂直的芯片叠层中引发严重的电压下降；（2）将具有接近的固有下降强度的线程设置在同一个层中以缓解垂直的干涉和最小化一个层中的多个核的不对称电压裕度。如上所述，垂直方向的共振会引起比水平方向的共振更大的电压下降，因此，将相似的线程设置在同一个芯片中而不是垂直设置在不同的层中是合理的。此外，多个核的最严重情况的电压下降是随着线程的特性而改变的。当整个层共享频率检测和驱动***时，时序裕度需要承受最严重情况的线程，从而对于温和的核来说，导致了裕度的浪费。这种方法缓和了多个核之间的层内差距；（3）在相同的芯片内，将不停的应用的线程设置成相邻能够帮助减少由相似的管线活动所导致的局部电压共振。
本发明的用于在3D堆叠式芯片中调度线程的方法的示例性实施例可包括如图7所示的下述步骤。第一，在步骤710，估测来自一个或多个应用的多个线程的固有下降强度；然后，在步骤720，将该多个线程根据固有下降强度以降序排列并将它们排成队列；然后，在步骤730，选择该队列的头部的线程并将其设置在可获得的最低层芯片的可获得的核中；然后，在步骤740，检测所述队列是否已空，并重复步骤730直到队列变空。
另外，在步骤720中，如果多个线程具有相同的固有下降强度，那么可利用循环算法从不同的应用中选择线程以缓解水平方向的干涉。
关于步骤710，电压下降与管线活动密切相关，因此，由性能计数器捕获的微架构事件信息可以用来估测来自应用的线程的固有下降强度，以便预测线程是电压猛烈的还是电压温和的，这在本领域是已知的。统计学可用于将性能计数器的输入（例如分支误预测强度、缓存未命中强度、转换查找缓冲器（TLB）未命中强度）与线程电压下降强度相关联。因为这些运行时间统计是非线性相关的，所以回归树是一种理想的方法以处理这种关系。这种模型训练方法可以离线进行。在训练过程中，性能计数器信息和线程的相应的下降强度被集合成训练集以产生回归树。该下降强度能够用例如关键路径监测器之类的在线测量感测器来计算。为了避免干涉，在训练期间，一次只有一个线程运行在功率域中。当回归树被训练达到稳定的状态时，其能够被嵌入目标芯片中以预测线程的电压特性。
此外，3D芯片可包括核和缓存或存储器，其中一个或多个缓存层可叠置在核层的上方。例如，图8显示了包括核层和缓存层的示例性3D芯片，其中缓存层810叠置在核层820的上方。该缓存层810可包括多个缓存库830。核层820可包括多个核840。一个或多个线程能够在该多个核840中被执行。在执行线程的过程中，数据频繁地从所述缓存库中取出或存入该缓存库。缓存活动也会在功率传输网络中产生波动的电流。缓存的功率消耗随着缓存存取的频率而改变。例如，当线程具有许多数据交互作用时，功率消耗会变大。因此，这会导致核和缓存在垂直方向上的共振。在这种情况下，需要监测缓存的行为和核的行为并估计缓存库的功率消耗。如图8所示，当核和缓存间的共振发生时，将触发线程调度或者数据重新映射。能够通过将电压猛烈的线程与缓存库分开的方法来避免核和缓存之间的共振。可通过将数据移动到远处的缓存库（见图8中缓存层810上方的箭头）或者通过将电压温和的线程分配至核的方式（见图8中核层820下方的箭头）来分开所述电压猛烈的线程和缓存库。
在将数据移动到远处的缓存库或者通过将电压温和的线程分配至核来缓解或避免核与缓存间的共振之前，需要监测缓存行为。回归模型可以用于表现缓存库的存取强度和电压下降强度之间的关联。该回归模型的训练阶段也是离线进行的。在预测阶段，监测器将每个缓存库的存取计数作为输入以预测电压下降强度。因此，需要增加缓存库存取计数器指核或者缓存层以记录缓存紧急标识的存取。如果监测器部件是实施在核中，那么将读/写请求的地址转换成缓存库的标识。然后相应的计数器根据每一次缓存存取而增加。如果监测器是实施在缓存中，那么监测器可嵌入在缓存库的读/写电路中。相关的缓存库的存取计数器根据每一次数据存取而增加。然后，如果缓存行为表明在3D芯片中存在核和缓存间的共振，则通过将数据移动到远处的缓存库或者通过将电压温和的线程分配给核来分开电压猛烈的线程和缓存库。
在一个或多个实施例中，上面描述的线程调度方法可通过软件来实施，用于实现本发明的线程调度方法的各步骤的功能的计算机可读代码可以存储在计算机可读介质中。本发明的计算机可读介质的例子包括但不限于：磁介质，如硬盘、软盘和磁带；光介质，如CD-ROM和全息设备；磁-光介质，如光软盘；以及为了存储和执行程序代码专门配置的硬件设备，如专用集成电路（ASIC）、可编程逻辑器件以及ROM和RAM器件。所述计算机可读代码能够被一个或更多的处理单元执行。
通过使用本发明的层独立控制***，电压违限的平均减少量可以达到例如40%。并且，如图9所示，本发明的线程调度方法能够缓解每一层中的电压下降大约13%，并且能降低3D芯片中的电压下降。这是因为本发明对线程的电压特性作了预测并且积极地调度线程以最小化较大的电压下降。除了降低电压违限外，该线程调度方法也能够降低一般情况的电压下降的电压裕度约9%。此外，本发明的调度方法也能减小层内的电压下降差距。层0内的最严重情况的电压下降约为20mv，在调度后，该差距仅仅为6mv。应注意的是，随着芯片层数量以及芯片架构的改变，电压违限或者电压下降的降低效果也会改变。
对于本领域的技术人员来说显而易见的是，可以在不背离本发明的精神和权利要求的范围的情况下对本发明作不同的修改和变型。因此，如果对本发明的修改和变型落入了权利要求和它们的等同物的范围内，那么应当认为本发明覆盖了对本发明所描述的不同实施例的修改和变型。

Claims (8)

1.一种多芯片***，包括垂直堆叠的、电耦合在一起的多个芯片；
所述多个芯片中的每个芯片包括一个或多个核，所述多个芯片中的每个芯片进一步包括：
至少一个电压违限感测单元，该至少一个电压违限感测单元与所述每个芯片的一个或多个核连接，该至少一个电压违限感测单元被配置成独立感测所述每个芯片中的每个核的电压违限；以及
至少一个频率调谐单元，该至少一个频率调谐单元被配置成调谐所述每个芯片的每个核的频率以当在每个核中感测到电压违限时避免时序错误，该至少一个频率调谐单元与所述至少一个电压违限感测单元连接，
其中所述多个芯片的电压裕度根据一般情况的电压下降来配置。
2.根据权利要求1所述的多芯片***，其中所述至少一个电压违限感测单元是关键路径监测器。
3.根据权利要求2所述的多芯片***，其中所述至少一个频率调谐单元是数字锁相环。
4.根据权利要求1-3中任一项所述的多芯片***，其中所述多芯片***还包括性能监测器和电压调节器，所述性能监测器与一个或多个所述频率调谐单元连接并且被配置成监测所述堆叠的芯片的频率，所述电压调节器与所述性能监测器连接并且被配置成调节提供至所述多个芯片的电压。
5.一种用于3D堆叠芯片***的控制方法，所述3D堆叠芯片***包括多个垂直堆叠的芯片，每个所述芯片包括一个或多个核，该方法包括：
(a)通过与所述核连接的至少一个电压违限感测单元感测所述芯片的一个或多个核中是否存在电压违限；
(b)如果是，则通过与所述电压违限感测单元连接的频率调谐单元调谐该芯片的频率以避免时序错误；以及
(c)如果否，则继续进行步骤(a)，
其中所述控制方法为所述3D堆叠芯片***中的每个芯片独立地执行，
其中所述多个芯片的电压裕度根据一般情况的电压下降来配置。
6.根据权利要求5所述的方法，还包括：
监测所述3D堆叠芯片***的频率以确定该频率是否高于上限或低于下限；
如果该频率高于所述上限，则降低提供至该3D堆叠芯片***的电压；
如果该频率低于所述下限，则提高提供至该3D堆叠芯片***的电压。
7.根据权利要求5或6所述的方法，其中所述电压违限感测单元是关键路径监测器。
8.根据权利要求7所述的方法，其中所述频率调谐单元是数字锁相环。
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