CN104698364A - Automatic balancing circuit - Google Patents
Automatic balancing circuit Download PDFInfo
- Publication number
- CN104698364A CN104698364A CN201510091876.6A CN201510091876A CN104698364A CN 104698364 A CN104698364 A CN 104698364A CN 201510091876 A CN201510091876 A CN 201510091876A CN 104698364 A CN104698364 A CN 104698364A
- Authority
- CN
- China
- Prior art keywords
- trim
- comparer
- phase inverter
- selector switch
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
The invention provides an automatic balancing circuit. The automatic balancing circuit is that a plurality of comparators are adopted to compare a value to be balanced with a set value; when the value to be balanced reaches the set value, the balancing result is outputted and recorded, so that the purpose of automatically balancing can be quickly achieved; when one value to be balanced is balanced, a selector can select to automatically balance another value to be balanced, thus a plurality of values to be balanced can be balanced, and as a result the time consumed by the balancing manner in the prior art can be greatly reduced; the testing cost can be reduced while the testing time is saved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of auto-trim circuit.
Background technology
Integrated circuit has the action required point in the range of operating parameters of circuit.In order to reach this action required point, manufacturer must regulate some to regulate the signal being provided to the various assemblies of system.These positions through adjustment are commonly referred to trim position.
In prior art, usually perform the setting of trim position in the following ways.First, manufacturer's design test program.Described test procedure setting trim position, is applied to circuit by trim position, and measurement result.Test procedure analysis result based on results modification trim position.Repeat this process until find the best hyte for impelling circuit to perform at action required point.Described best hyte is recorded and uses during circuit operation.The method considerably increases time and the cost of designing integrated circuit.
High pressure trim is very necessary when flash memory circuit is tested, and whether the performance reflecting flash memory that the accuracy of test voltage can be correct is good.But the trim mode adopted in prior art is when integrated level is more and more higher, and test duration and cost will increase greatly, is unfavorable for carrying out volume production.Therefore, how to shorten test duration and cost, just become those skilled in the art's technical matters to be solved.
Summary of the invention
The object of the present invention is to provide a kind of auto-trim circuit, automatically can carry out trim, reduce the time needed for trim, reduce testing cost.
To achieve these goals, the present invention proposes a kind of auto-trim circuit, comprise: multiple comparer and selector switch, wherein, the input of comparer described in each all connects a setting value and and treats trim value, and the output of described comparer connects the input of described selector switch, and described selector switch is used for any one comparer selected and carries out work, when described reach described setting value until trim value time, trim result is exported and record by described comparer.
Further, also comprise phase inverter, the input of described phase inverter connects the output of described selector switch, and described trim result is exported by described phase inverter.
Further, the number of described phase inverter is 2, be respectively the first phase inverter and the second phase inverter, the input of described first phase inverter connects the output of described selector switch, the input of described second phase inverter connects the output of described first phase inverter, and described trim result is exported by described second phase inverter.
Further, the number of described comparer is 2.
Further, described comparer is forward comparer and negative sense comparer, the input of described forward comparer is provided with the first setting value and first and treats trim value, the input of described negative sense comparer is provided with the second setting value and second and treats trim value, and described forward comparer exports with negative sense comparer two inputs being connected described selector switch respectively.
Further, described selector switch is two-way selector switch.
Further, the selection signal of described selector switch is identical with the enable signal of described forward comparer or negative sense comparer.
Further, described first setting value and the second setting value share a test panel.
Compared with prior art, beneficial effect of the present invention is mainly reflected in: adopt multiple comparer, treat trim value and setting value compares, when reaching setting value until trim value, trim result is exported and record, thus the object of automatic trim can be reached fast, when completing a trim until trim value, can be undertaken selecting to treat that trim value carries out automatic trim to another by described selector switch, be applicable to treat that trim value carries out trim to multiple, thus the time that greatly reducing in prior art spent by trim mode, while saving the test duration, also reduce testing cost.
Accompanying drawing explanation
Fig. 1 is the structural representation of auto-trim circuit in the embodiment of the present invention.
Embodiment
Below in conjunction with schematic diagram, auto-trim circuit of the present invention is described in more detail, which show the preferred embodiments of the present invention, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, a large amount of implementation detail must be made to realize the specific objective of developer, such as, according to regarding system or the restriction about business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, more specifically the present invention is described by way of example with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
In the present embodiment, propose a kind of auto-trim circuit, comprise: multiple comparer and selector switch, wherein, the input of comparer described in each all connects a setting value and and treats trim value, and the output of described comparer connects the input of described selector switch, and described selector switch is used for any one comparer selected and carries out work, when described reach described setting value until trim value time, trim result is exported and record by described comparer.
Due in reality test; usually the tests such as high pressure are needed; therefore, in order to accurately test voltage can be reached, positive voltage divider (positive divider) and negative voltage divider (negative divider) usually can be used; trim is carried out for high pressure being divided into multiple low voltage; be convenient to realize, in existing 90nm flash memory, all need to use positive voltage divider and negative voltage divider; it is pointed out that the voltage that negative voltage divider separates is positive voltage.Therefore, accordingly, in the present embodiment, the number of described comparer is 2, is forward comparer 11 and negative sense comparer 12 respectively.Concrete, please refer to Fig. 1, the input of described forward comparer 11 is provided with the first setting value VREF_ATRM1 and first and treats trim value DETP, the input of described negative sense comparer 11 is provided with the second setting value VERF_ATRM2 and second and treats trim value VNEG_DET, the output CMPOUTP of described forward comparer 11 and the output CMPOUTN of negative sense comparer 12 are connected two inputs of described selector switch 20 respectively, respectively corresponding IN1 and IN2.
Wherein, described forward comparer 11 carries out trim for the voltage aligned needed for voltage divider, and described negative sense comparer 12 is for carrying out trim to the voltage needed for negative voltage divider.
Owing to being provided with 2 comparers, therefore, described selector switch 20 is in the present embodiment two-way selector switch.The selection signal of described selector switch 20 is identical with the enable signal of described forward comparer 11 or negative sense comparer 12, please refer to Fig. 1, the enable signal of selection signal in the present embodiment and described negative sense comparer 12 is HV_TRMEN<1>, and the enable signal of described forward comparer 11 is HV_TRMENP.When the selection signal that namely can define selector switch 20 is high level, selected forward comparer 11 compares work, and when the selection signal of selector switch 20 is low level, selected negative sense comparer 12 compares work.
In addition, in order to reduce the area shared by auto-trim circuit, described first setting value VREF_ATRM1 and the second setting value VREF_ATRM2 can be made to share a test panel (test pad), thus manufacture and testing cost can be reduced.
In the present embodiment, please continue to refer to Fig. 1, described auto-trim circuit also comprises phase inverter, the number of described phase inverter is 2, be respectively the first phase inverter 31 and the second phase inverter 32, the input of described first phase inverter 31 connects the output of described selector switch 20, and the input of described second phase inverter 32 connects the output of described first phase inverter 31, and described trim result HVCMPOUT is exported by described second phase inverter 32.
When carrying out trim, such as positive voltage needed for voltage divider is 1V, when carrying out trim to it, first setting value VREF_ATRM1 of forward comparer 11 is 1V, trim result can be 4-digit number signal, when first time carries out trim, trim exports as a<0000>, first treats that trim value DETP is such as 0.8V, then be less than the first setting value VREF_ATRM1, therefore, the output of forward comparer 11 is low level, then, carry out second time trim, if first when trim value DETP during 0.85V, trim exports and should be a<0001>, still be less than the first setting value VREF_ATRM1, exporting still is low level, circulate successively, carry out trim, until the output of forward comparer 11 is high level, namely first treat that trim value DETP is more than or equal to the first setting value VREF_ATRM1, complete a trim, and trim output (being such as a<0011>) is recorded.In like manner, when carrying out trim to negative voltage divider, only needing the selection signal level of selector switch 20 to change, namely work being compared to negative sense comparer 12.Identical all with forward comparer 11 of the mode of trim and principle, therefore not to repeat here.
To sum up, in the auto-trim circuit that the embodiment of the present invention provides, adopt multiple comparer, treat trim value and setting value compares, when reaching setting value until trim value, trim result is exported and record, thus the object of automatic trim can be reached fast, when completing a trim until trim value, can be undertaken selecting to treat that trim value carries out automatic trim to another by described selector switch, be applicable to treat that trim value carries out trim to multiple, thus the time that greatly reducing in prior art spent by trim mode, while saving the test duration, also reduce testing cost.
Above are only the preferred embodiments of the present invention, any restriction is not played to the present invention.Any person of ordinary skill in the field; in the scope not departing from technical scheme of the present invention; the technical scheme disclose the present invention and technology contents make the variations such as any type of equivalent replacement or amendment; all belong to the content not departing from technical scheme of the present invention, still belong within protection scope of the present invention.
Claims (8)
1. an auto-trim circuit, it is characterized in that, comprise: multiple comparer and selector switch, wherein, the input of comparer described in each all connects a setting value and and treats trim value, and the output of described comparer connects the input of described selector switch, and described selector switch is used for any one comparer selected and carries out work, when described reach described setting value until trim value time, trim result is exported and record by described comparer.
2. auto-trim circuit as claimed in claim 1, it is characterized in that, also comprise phase inverter, the input of described phase inverter connects the output of described selector switch, and described trim result is exported by described phase inverter.
3. auto-trim circuit as claimed in claim 2, it is characterized in that, the number of described phase inverter is 2, be respectively the first phase inverter and the second phase inverter, the input of described first phase inverter connects the output of described selector switch, the input of described second phase inverter connects the output of described first phase inverter, and described trim result is exported by described second phase inverter.
4. auto-trim circuit as claimed in claim 1, it is characterized in that, the number of described comparer is 2.
5. auto-trim circuit as claimed in claim 4, it is characterized in that, described comparer is forward comparer and negative sense comparer, the input of described forward comparer is provided with the first setting value and first and treats trim value, the input of described negative sense comparer is provided with the second setting value and second and treats trim value, and described forward comparer exports with negative sense comparer two inputs being connected described selector switch respectively.
6. auto-trim circuit as claimed in claim 5, it is characterized in that, described selector switch is two-way selector switch.
7. auto-trim circuit as claimed in claim 5, it is characterized in that, the selection signal of described selector switch is identical with the enable signal of described forward comparer or negative sense comparer.
8. auto-trim circuit as claimed in claim 5, is characterized in that, described first setting value and the second setting value share a test panel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510091876.6A CN104698364A (en) | 2015-02-28 | 2015-02-28 | Automatic balancing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510091876.6A CN104698364A (en) | 2015-02-28 | 2015-02-28 | Automatic balancing circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104698364A true CN104698364A (en) | 2015-06-10 |
Family
ID=53345692
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510091876.6A Pending CN104698364A (en) | 2015-02-28 | 2015-02-28 | Automatic balancing circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104698364A (en) |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1085413A1 (en) * | 1999-09-14 | 2001-03-21 | STMicroelectronics S.r.l. | Electronic circuit and corresponding method for trimming an IC |
| US6675360B1 (en) * | 1999-11-23 | 2004-01-06 | Stmicroelectronics S.R.L. | System of management of the trimming of integrated fuses within a scan test architecture |
| KR20040006416A (en) * | 2002-07-12 | 2004-01-24 | 주식회사 하이닉스반도체 | Method of trimming reference voltage of a flash memory cell and apparatus of trimming reference voltage of a flash memory cell |
| US20040135617A1 (en) * | 2002-10-07 | 2004-07-15 | Liu Jonathan H. | Method and apparatus for detection and quantification of on-die voltage noise in microcircuits |
| US20050189954A1 (en) * | 2001-10-26 | 2005-09-01 | Micrel, Incorporated | Method for optimizing the accuracy of an electronic circuit |
| US20080144390A1 (en) * | 2006-12-15 | 2008-06-19 | Spansion Llc | Drain voltage regulator |
| CN101377537A (en) * | 2007-08-27 | 2009-03-04 | 爱特梅尔公司 | Auto-trim circuit |
| US20090284246A1 (en) * | 2008-05-16 | 2009-11-19 | Ranjit Kumar Dash | Low dropout regulator testing system and device |
| US20120126781A1 (en) * | 2010-11-22 | 2012-05-24 | Texas Instruments Incorporated | On-chip ir drop detectors for functional and test mode scenarios, circuits, processes and systems |
| CN103943146A (en) * | 2014-03-20 | 2014-07-23 | 广东博观科技有限公司 | Device and method for rapid setting of target voltages |
| US20140225110A1 (en) * | 2013-02-12 | 2014-08-14 | Texas Instruments Incorporated | Default Trim Code Technique |
| US8842482B1 (en) * | 2012-06-29 | 2014-09-23 | Cypress Semiconductor Corporation | Programmable memory with skewed replica and redundant bits for reset control |
-
2015
- 2015-02-28 CN CN201510091876.6A patent/CN104698364A/en active Pending
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1085413A1 (en) * | 1999-09-14 | 2001-03-21 | STMicroelectronics S.r.l. | Electronic circuit and corresponding method for trimming an IC |
| US6675360B1 (en) * | 1999-11-23 | 2004-01-06 | Stmicroelectronics S.R.L. | System of management of the trimming of integrated fuses within a scan test architecture |
| US20050189954A1 (en) * | 2001-10-26 | 2005-09-01 | Micrel, Incorporated | Method for optimizing the accuracy of an electronic circuit |
| KR20040006416A (en) * | 2002-07-12 | 2004-01-24 | 주식회사 하이닉스반도체 | Method of trimming reference voltage of a flash memory cell and apparatus of trimming reference voltage of a flash memory cell |
| US20040135617A1 (en) * | 2002-10-07 | 2004-07-15 | Liu Jonathan H. | Method and apparatus for detection and quantification of on-die voltage noise in microcircuits |
| US20080144390A1 (en) * | 2006-12-15 | 2008-06-19 | Spansion Llc | Drain voltage regulator |
| CN101377537A (en) * | 2007-08-27 | 2009-03-04 | 爱特梅尔公司 | Auto-trim circuit |
| US20090284246A1 (en) * | 2008-05-16 | 2009-11-19 | Ranjit Kumar Dash | Low dropout regulator testing system and device |
| US20120126781A1 (en) * | 2010-11-22 | 2012-05-24 | Texas Instruments Incorporated | On-chip ir drop detectors for functional and test mode scenarios, circuits, processes and systems |
| US8842482B1 (en) * | 2012-06-29 | 2014-09-23 | Cypress Semiconductor Corporation | Programmable memory with skewed replica and redundant bits for reset control |
| US20140225110A1 (en) * | 2013-02-12 | 2014-08-14 | Texas Instruments Incorporated | Default Trim Code Technique |
| CN103943146A (en) * | 2014-03-20 | 2014-07-23 | 广东博观科技有限公司 | Device and method for rapid setting of target voltages |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8346977B2 (en) | Device address assignment in a bus cascade system | |
| KR20090127834A (en) | Systems and methods for testing integrated circuit devices | |
| CN108009055B (en) | Method and device for repairing hold time violation | |
| US11113222B2 (en) | NAND switch | |
| CN111142006B (en) | Trim test method and automatic test equipment for chip | |
| CN103617810A (en) | Test structure and test method for embedded memory | |
| CN105468797A (en) | Information processing method and apparatus | |
| US20160224451A1 (en) | Multi-Domain Fuse Management | |
| CN117033251B (en) | Regression testing method and device for multi-version system of mobile electronic equipment | |
| US20160293272A1 (en) | Method and apparatus for optimized memory test status detection and debug | |
| CN102799479A (en) | Mainboard with multifunctional basic input output system (BIOS) and test method thereof | |
| US20100332932A1 (en) | Test method, test control program and semiconductor device | |
| CN104635142A (en) | Testing device and testing method for improving testing accuracy | |
| CN104698364A (en) | Automatic balancing circuit | |
| US10054634B2 (en) | Test device | |
| CN101398451A (en) | Rapid detection method for testing backing board | |
| CN103235633A (en) | Bidirectional current trimming circuit and current trimming method thereof | |
| US8726206B1 (en) | Deadlock detection method and related machine readable medium | |
| CN105679690A (en) | Method for prolonging service life of test wafer | |
| US9355018B1 (en) | History N-section for property location | |
| US8933725B2 (en) | State machine circuit and state adjusting method | |
| US9482718B2 (en) | Integrated circuit | |
| JP2014215178A (en) | Semiconductor device | |
| US11556818B2 (en) | Dynamic intelligent test method and computer device employing the method | |
| US10554395B2 (en) | Semiconductor device managing power budget and operating method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20150610 |