CN104682701B - Boosted circuit - Google Patents
Boosted circuit Download PDFInfo
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- CN104682701B CN104682701B CN201310611534.3A CN201310611534A CN104682701B CN 104682701 B CN104682701 B CN 104682701B CN 201310611534 A CN201310611534 A CN 201310611534A CN 104682701 B CN104682701 B CN 104682701B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
The invention discloses a boosted circuit, comprising a power supply rail for supplying supply voltage, a switch transistor for controlling the output of a boost signal, and a timing sequence and voltage control circuit for generating an equalization (EQ) signal to be applied to a grid electrode of the switch transistor, wherein the boost signal is output by a source electrode of the switch transistor, and the EQ signal has a level, namely an EQ high level, or an EQ low level lower than the EQ high level, or an EQ clamp level between the EQ low level and the EQ high level.
Description
Technical field
The invention relates to a kind of booster circuit, and in particular to a kind of with the control for avoiding booster circuit from collapsing
The booster circuit of circuit processed, and the method to avoid booster circuit from collapsing.
Background technology
In semiconductor circuit, certain part for needing to apply a particular voltage level to semiconductor circuit is there may come a time when
, correctly there is effectiveness so that semiconductor circuit can be made in (such as specific substrate or wordline).In some cases, specific voltage is phase
When high voltage.This high voltage can be produced by a charge pump (charge pump) circuit, and it is electric by relatively low input
Pressure is promoted to relatively high output voltage.In general, charge pump circuit needs to be worked together with frequency signal, the frequency needed for it
Rate signal has higher voltage level than the frequency signal for being just commonly used for the other parts of semiconductor circuit.For example,
If the supply voltage V on the power rail (power rail) of semiconductor circuitDDAbout 1.8V, the then frequency in semiconductor circuit
The voltage level of rate signal is also about 1.8V.In order to allow charge pump circuit to produce higher than supply voltage VDDVoltage, need tool
Have approximately twice as supply voltage VDDVoltage level (that is, about 3.6V) high voltage frequency signal.
Booster circuit can be used to the voltage of " boosting " one input frequency signal and produce to have be approximately twice supply voltage
VDDThe high voltage frequency signal (that is, boost frequency signal) of level.Booster circuit may include multiple semiconductor devices, including field
Effect transistor (Field-Effect Transistor, FET), such as metal-oxide semiconductor (MOS) FET (Metal-Oxide-
Semiconductor Field-Effect Transistor, MOSFET).When the voltage of input frequency signal it is boosted paramount
In VDDWhen, it is approximately twice supply voltage VDDBoosting high voltage may also be applied to one or more FET.
Sometimes, semiconductor circuit may be needed in low VDDCondition and high VDD(such as in V between conditionDDAbout 1.8V's
Operating condition and VDDAbout between the operating condition of 3.3V) switching.In VDDDuring operation during about 3.3V, voltage-frequency is risen
Rate signal is about 6.6V, and it could possibly be higher than the breakdown voltage of one or more FET in booster circuit, thus cause one or
Multiple FET collapses.
The content of the invention
According to the present invention, there is provided a kind of booster circuit.This booster circuit includes：One power rail, to provide supply electricity
Pressure；One switching transistor, controls the output of a boost signal, and boost signal is exported by the source electrode of switching transistor；And for the moment
Sequence and voltage control circuit, the EQ signals of the grid to produce a switching transistor to be applied to.EQ signals are electric with one
It is flat, its be an EQ high level, one less than EQ high level EQ low levels or an EQ between EQ low levels and EQ high level
Clamp level.
Again according to the present invention, there is provided a kind of method for controlling the output of a boost signal.The method includes producing one
EQ signals with a level, this level is an EQ high level, one less than the EQ low levels of EQ high level and low between EQ
One of them of EQ clamp levels between level and EQ high level.The method further includes applying EQ signals to a switching transistor
A grid, use control boost signal output.
To partly propose in the following description according to the feature and advantage of the present invention, and part will be from this explanation it is aobvious and
It is clear to, or can learns to arrive by the enforcement of description.This feature and advantage will be utilized in appended claims
Specifically noted element and combination and realize and obtain.
We will be appreciated that, both above-mentioned general remark and following detailed description be only for the present invention illustration and explanation and
Unrestricted scope of the presently claimed invention.
Be incorporated to and constitute the accompanying drawing of a part for this description, show the present invention several embodiments, and with explanation
It is used to together illustrate the principle of the present invention.
Description of the drawings
Fig. 1 illustrates the figure according to a booster circuit of illustrative embodiments.
Fig. 2 is illustrated according to input frequency signal CLK, the first frequency signal PCLK1 and second frequency letter of illustrative embodiments
The oscillogram of number PCLK2.
Fig. 3 illustrates the circuit diagram of the boost in voltage block according to the booster circuit of illustrative embodiments.
Fig. 4 illustrate according to illustrative embodiments first boosting source signal BST1, second boosting source signal BST2, first
The oscillogram of boost signal BT1 and the second boost signal BT2.
Fig. 5 is illustrated according to a sequential and a section of voltage control zone block of the booster circuit of illustrative embodiments
(segment) figure.
Fig. 6 illustrate according to illustrative embodiments first frequency signal PCLK1, postpone first frequency signal PCLK1, first
The oscillogram of boosting source signal BST1 and EQ input signals EQIN1.
Fig. 7 illustrates the circuit diagram according to the sequential of illustrative embodiments and a kind of EQ generating elements of voltage control zone block.
Fig. 8 A and Fig. 8 B are illustrated according to illustrative embodiments in low VDDEQ input signals EQIN1 during operation, electricity
The oscillogram of source control signal PWCTL, the first equating signal EQ1 and the second equating signal EQ2, and in high VDDDuring operation
First EQ input signals EQIN1, secondary signal PB2, power control signal PWCTL, the first equating signal EQ1 and second etc. change letter
The oscillogram of number EQ2.
Fig. 9 A and Fig. 9 B is illustrated respectively according to illustrative embodiments in low VDDWith high VDDThe first equating signal during operation
EQ1, the second equating signal EQ2, the first boosting source signal BST1, the second boosting source signal BST2, the first boost signal
The oscillogram of BT1, the second boost signal BT2, the first boost frequency signal CK1 and the second boost frequency signal CK2.
【Symbol description】
BST1：First boosting source signal
BST2：Second boosting source signal
BT1：First boost signal
BT2：Second boost signal
C1、C2：Capacitor
CK1：First boost frequency signal
CK2：Second boost frequency signal
CLK：Input frequency signal
EQ1：First EQ signals
EQ2：2nd EQ signals
EQIN1：First EQ input signals
EQIN2：2nd EQ input signals
M31 to M38：Transistor
M71 to M77：Transistor
PB1：First signal
PB2：Secondary signal
PCLK1：First frequency signal
PCLK2：Second frequency signal
PWCTL：Power control signal
VBOOST：Boosted-high level
VBOOST-CK：Boosting high frequency level
VCLAMP：EQ clamp levels
VDD：Supply voltage
VHIGH1：First high level
VHIGH2：Second high level
Vref：Reference voltage
VSHARE：Pressure drop
100：Booster circuit
102：Non-overlapping frequency produces block
104：Sequential and voltage control zone block
106：Boost in voltage block
302：Power rail
304：Earth terminal
500：Section
502：Time delay element
503：Logic circuit
504：AND gate
506：OR grid
508：EQ generating elements
702：First circuit branch
704：Second circuit branch
706：Tertiary circuit branch
708：EQ lead-out terminals
710：Phase inverter
Specific embodiment
Include being able to maintain that the booster circuit of high output voltage and to avoid a liter piezoelectricity according to embodiments of the invention
The method of road collapse.
Hereinafter, will illustrate according to embodiments of the invention with reference to schema.If if being possible to, will use throughout these schemas
Identical reference number is representing same or similar part.
Fig. 1 is illustrated according to an illustration booster circuit 100 of the embodiment of the present invention.Booster circuit 100 is to produce a boosting
Frequency signal, it has a boosting high frequency level, is higher than the high frequency level of input frequency signal (boosting altofrequency electricity
The flat high frequency level for being for example approximately twice input frequency signal), wherein the high frequency level of input frequency signal about with
Supply voltage VDDIt is identical.In certain embodiments, as shown in figure 1, booster circuit 100 produces two boost frequency signals, i.e., the
One boost frequency signal CK1 and the second boost frequency signal CK2.
According to embodiments of the invention, booster circuit 100 is in low VDDOperating condition and high VDDBoth operating conditions
Under operate, and between two operating conditions switch.As used in this description, low VDDRepresent such VDD
Breakdown voltage of the boosting high frequency level of boost frequency signal higher than the electronic component in booster circuit 100 is not result in, and
High VDDRepresent such VDDThe boosting high frequency level of boost frequency signal may be caused higher than the electronics in booster circuit 100
The breakdown voltage of element.For example, low VDDCan be about 1.65V to about 2V, and high VDD2.7V can be about to about
3.6V.In certain embodiments, low VDDCan be about 1.8V, and high VDD3.3V can be about.
Fig. 1 is refer to, booster circuit 100 includes that non-overlapping frequency produces block 102, sequential and voltage control zone block 104
And boost in voltage block 106.It is to produce the first frequency based on input frequency signal CLK that non-overlapping frequency produces block 102
Rate signal PCLK1 and second frequency signal PCLK2.
Fig. 2 illustrates the illustration ripple of input frequency signal CLK, first frequency signal PCLK1 and second frequency signal PCLK2
Shape.Foundation embodiments of the invention, input frequency signal CLK, first frequency signal PCLK1 and second frequency signal PCLK2 are all
With approximately equal to VDDHigh level and the approximately equal to low level of ground voltage (that is, 0V), the cycle is for example all 40ns.
Hereinafter, unless otherwise stated, the high level ideal of a waveform is considered about VDD, but may for example because of dead resistance
Compare VDDIt is a little low.Also, the low level of a waveform is considered to be about 0V, but may be for example high than 0V because of dead resistance
A bit.In high level and VDDBetween and difference between low level and 0V it is little, it is because they are due to for example parasitic
The pressure drop of electric capacity.As shown in Fig. 2 first frequency signal PCLK1 and second frequency signal PCLK2 do not overlap each other, that is, the
One frequency signal PCLK1 and second frequency signal PCLK2 are not uprised simultaneously.Within a cycle, first frequency signal
It is the time delay that rises to high level from low level in input frequency signal CLK that PCLK1 rises to high level from low level
Afterwards, and first frequency signal PCLK1 drops to low level from high level is dropped to from high level with input frequency signal CLK
The low level about the same time.Similarly, it is in incoming frequency letter that second frequency signal PCLK2 rises to high level from low level
Number CLK is dropped to after a low level time delay from high level, and second frequency signal PCLK2 drop to from high level it is low
Level is to rise to the high level about the same time from low level with input frequency signal CLK.Hereinafter, a waveform is from a level
Transformation to another level is also referred to as the edge of waveform.Transformation of the waveform from low level to high level is also referred to as waveform
Rising edge, and waveform is also referred to as drop edge from high level to low level transformation.
Refer again to Fig. 1, first frequency signal PCLK1 and second frequency signal PCLK2 to be input into sequential and voltage control
Block 104, and sequential and voltage control zone block 104 produce the first boosting source signal BST1 and the second boosting source signal
BST2, to be boosted by boost in voltage block 106.First boosting source signal BST1 and the second boosting source signal BST2 are also participated in
The operation of control voltage boosting block 106.Sequential and voltage control zone block 104 further produce first (EQ) signal
EQ1 and the 2nd EQ signal EQ2, the operation of its block 106 that also boosts to control voltage.Subsequently will discuss in this description, the
One EQ signals EQ1 and the 2nd EQ signal EQ2 are that the switch element for controlling an output boost frequency signal (for example switchs crystal
Pipe) conducting be not turned on operation.
Fig. 3 is illustrated according to the example voltages boosting block 106 of the embodiment of the present invention.Example voltages boosting shown in Fig. 3
Block 106 has " mirror " (mirror) structure (that is, a symmetrical structure), and " mirror " structure includes transistor M31-M38 and electric capacity
Device C1 and C2.Transistor M31-M38 be metal oxide semiconductcor field effect transistor (MOSFET), wherein transistor M31, M32,
M35, M36, M37 and M38 are n-channel MOSFET (n-MOS), and transistor M33 and M34 are p-channel MOSFET (p-MOS).Such as
To see from Fig. 3 and in this description the discussion below, though during high VDD is operated, for transistor M31, M32, M35 and
For each of M36, the voltage differences being applied between grid and source/drain are relatively low, and this voltage differences is not
More than the breakdown voltage of oxide, i.e., destroyed not less than the gate oxide of transistor voltage.Hereinafter, unless otherwise saying
Bright, the oxide breakdown voltage of otherwise transistor is also referred to as the breakdown voltage of transistor.Therefore, to transistor M31, M32,
For M35 and M36, when can reduce power consumption and shared electric charge using the thin-oxide n-MOS with lower threshold voltage
Between.
As shown in figure 3, the drain electrode of transistor M31 and M32 is connected to power rail 302, power rail 302 provides supply voltage
VDD.Transistor M31 and M32 form a charge path, and charge path is believed together with capacitor C1 and C2 with the first boosting source
The boosting source signal BST2 of number BST1 and second produce the first boost signal BT1 and the second boost signal BT2 as input.Figure
4 illustrate the first boosting source signal BST1, the second boosting source signal BST2, the first boost signal BT1 and the second boost signal
The illustration waveform of BT2.This description subsequently will be discussed further the boostings of the first boosting source signal BST1 and second source letter
The generation of number BST2.From Fig. 4 it can be seen that when the second boosting source signal BST2 rises to high level from low level, first boosts
Signal BT1 is to be charged to the first high level V by power rail 302HIGH1And this voltage level is maintained at until the first boosting comes
Till source signal BST1 rises to high level from low level, in now the first boost signal BT1 systems from the first high level VHIGH1Rise
It is depressed into boosted-high level VBOOST, boosted-high level VBOOSTV can be aboutDD1.8 times to about 2 times.Ideally, the first high electricity
Flat VHIGH1Will be with VDDIt is identical.But as previously described, because the dead resistance and electric capacity of the electronic component in booster circuit 100,
One high level VHIGH1Less than VDD.When the first boosting source signal BST1 is down to low level from high level, the first boost signal
BT1 is from boosted-high level VBOOSTIt is down to the second high level VHIGH2.Similarly, since dead resistance and electric capacity, the second high level
VHIGH2System is higher than earth level but less than VDDAnd the first high level VHIGH1.Second boost signal BT2 changes over time are class
Be similar to the first boost signal BT1, but with out of phase, so as in this and it is unspecified.
Fig. 3 is refer again to, the source electrode of transistor M37 and M38 is connected to earth terminal 304, the leakage of transistor M37 and M38
Pole is connected to the source electrode of transistor M35 and M36, and the grid of transistor M37 and M38 is respectively by the second boosting source signal
The boosting source signal BST1 of BST2 and first are controlled.Additionally, the grid of transistor M35 and M36 is connected to power rail 302,
Therefore, transistor M35 and M36 is always turned on during the operation of booster circuit 100.Transistor M35, M36, M37 and M38 are formed
One discharge path.Discharge path is for rising to high level to turn on transistor M37 in the second boosting source signal BST2
When, the first boost frequency signal CK1 is pulled to into low level.Similarly, discharge path is also used in the first boosting source signal
BST1 rises to high level to turn on during transistor M38, and the second boost frequency signal CK2 is pulled to into low level.Transistor M35 and
M36 is inserted in discharge path, to avoid the generation of big peak discharge current, and respectively to avoid transistor M37 and
M38 collapses.
Transistor M33 and M34 controls respectively first liter of voltage-frequency as the shared switch element of electric charge, the shared switch element of electric charge
The output of rate signal CK1 and the second boost frequency signal CK2.That is, transistor M33 and M34 are in boost in voltage block 106
Switching transistor.For example, as shown in figure 3, when the 2nd EQ signals EQ2 be located at conducting transistor M33 level when, transistor
M33 receives the first boost signal BT1 in its drain electrode, and exports the first boost frequency signal CK1 in its source electrode.Similarly, when
When one EQ signals EQ1 is located at the level of conducting transistor M34, transistor M34 receives the second boost signal BT2 in its drain electrode, and
The second boost frequency signal CK2 is exported in its source electrode.First EQ signal EQ1, the 2nd EQ signal EQ2, the first boost frequency signal
The illustration waveform of CK1 and the second boost frequency signal CK2 subsequently will the explanation in this description.
As described above, first boosting source signal BST1, second boosting source signal BST2, an EQ signals EQ1 and
2nd EQ signal EQ2 are produced by sequential and voltage control zone block 104.According to embodiments of the invention, sequential and voltage control
Block processed 104 includes two intimate identical sections (segment).One of section of two sections is to produce first liter
A pressure source signal BST1 and EQ signal EQ1, and another section is boosted source signal BST2 and for producing second
Two EQ signal EQ2.For example, Fig. 5 illustrates an illustration section 500 of sequential and voltage control zone block 104, and it is to produce
A raw first boosting source signal BST1 and EQ signal EQ1.In sequential and voltage control zone block 104, to produce second liter
Another section system of source signal BST2 and the 2nd EQ signal EQ2 is pressed similar to section 500, so as to not depict in this.
As shown in figure 5, section 500 includes a time delay element 502, to produce one based on an input signal letter is postponed
Number.For example, time delay element 502 postpones first frequency signal PCLK1 to produce the first frequency signal of delay
PCLK1.That is, the output (that is, the first frequency signal PCLK1 for postponing) of time delay element 502 has similar to the first frequency
The waveform of rate signal PCLK1, but it is delayed by such as about 2ns.First frequency signal PCLK1 and the first frequency signal of delay
Both PCLK1 are input to a logic circuit 503 to produce a first boosting source signal BST1 and EQ signal EQ1.At certain
In a little embodiments, as shown in figure 5, logic circuit 503 includes an AND gate 504, an OR grid 506 and an EQ generating elements 508.
Specifically, the first frequency signal PCLK1 of delay is input into together with first frequency signal PCLK1 to AND gate 504 to produce
First boosting source signal BST1.Similarly, the first frequency signal PCLK1 of delay is also together with first frequency signal PCLK1
It is input into OR grid 506 to produce EQ input signals EQIN1, EQ input signals EQIN1 are then input into EQ and produce unit
Part 508 is producing an EQ signal EQ1.
First frequency signal PCLK1, the first boosting source signal BST1 that Fig. 6 illustrates first frequency signal PCLK1, postpones
And the first EQ input signals EQIN1 illustration waveform, each signal changes all between a high level and a low level.From figure
6 can be seen that, within a cycle, first boosting source signal BST1 rising edge with postpone first frequency signal
The rising edge of PCLK1 is consistent.That is, when the first frequency signal PCLK1 for postponing rises to a high level from a low level,
First boosting source signal BST1 rises to a high level in the about the same time from a low level.First boosting source signal
The drop edge of BST1 is consistent with the drop edge of first frequency signal PCLK1.That is, when first frequency signal PCLK1 is from one
When high level is down to a low level, the first boosting source signal BST1 is down to low level in the about the same time from high level.
Also, the rising edge of EQ input signals EQIN1 is consistent with the rising edge of first frequency signal PCLK1, and an EQ is defeated
The drop edge for entering signal EQIN1 is consistent with the drop edge of the first frequency signal PCLK1 for postponing.That is, EQ inputs
Signal EQIN1 rose before the first boosting source signal BST1 rises and after the first boosting source signal BST1 declines under
Drop.We may be noted that due to system delay two edges consistent with each other do not mean them on the just identical time
Rise or decline.For example, the rising edge of the first boosting source signal BST1 can slightly in the first frequency signal PCLK1 for postponing
Rising edge rear, this delay is typically smaller than deliberately delay by caused by time delay element 502.
Fig. 7 illustrates the EQ generating elements 508 according to an illustration of the embodiment of the present invention.EQ generating elements 508 include one the
One circuit branch 702, a second circuit branch 704 and a tertiary circuit branch 706, to produce an EQ signal EQ1's
The different piece of waveform, an EQ signal EQ1 are exported from EQ lead-out terminals 708.As shown in fig. 7, the first circuit branch 702 with
Second circuit branch 704 is connected between power rail 302 and EQ lead-out terminals 708, and tertiary circuit branch 706 is to be connected to
Between earth terminal 304 and EQ lead-out terminals 708.
In the example shown in Fig. 7, EQ generating elements 508 include a phase inverter 710 and are controlled by unlike signal
Transistor M71-M77.In the figure 7, transistor M71, M74, M75 and M76 is p-MOS, and transistor M72, M73 and M77 are n-
MOS.First circuit branch 702 includes transistor M71.Second circuit branch 704 includes transistor M74, M75 and M76.3rd is electric
Road branch 706 includes transistor M72, M73 and M77.
According to embodiments of the invention, EQ generating elements 508 are in low VDD(such as about 1.65V is extremely for operating condition
About 2V) with high VDDWork under operating condition (such as about 2.7V to about 3.6V) two operating conditions.In the example shown in Fig. 7
In son, transistor M72 and M76 are controlled by a power control signal PWCTL, and it is in low VDDDuring operation under operating condition
Holding transistor M72 is turned on and transistor M76 is not turned on, and in high VDDTransistor M72 is kept during operation under operating condition
It is not turned on and transistor M76 conductings.That is, when EQ generating elements 508 are in low VDDWhen working under operating condition, second circuit point
Prop up 704 to be cut off, so as to the generation not to an EQ signal EQ1 is impacted.When EQ generating elements 508 are in high VDDOperation
Under the conditions of when working, second circuit branch 704 accesses (kicks in) and the generation to an EQ signal EQ1 is impacted.
Fig. 8 A are illustrated when the EQ generating elements 508 of the illustration shown in Fig. 7 are in low VDDEQ when operating under operating condition
The waveform of input signal EQIN1, power control signal PWCTL and an EQ signal EQ1.Although 8A figures do not show that first believes
The waveform (i.e. the output of phase inverter 710) of number PB1, but be familiar with art person and understand that the first signal PB1 is only EQ inputs
The inversion signal of signal EQIN1.In this example, power control signal PWCTL is set to high level to keep transistor M72 to lead
It is logical and transistor M76 is not turned on.As shown in Figure 8 A, in low VDDUnder operating condition, an EQ signal EQ1 have EQ high level or EQ
Low level level, its level is identical with the high level and low level of EQ input signals EQIN1.According to the enforcement of the present invention
Example, EQ high level is approximately equal to VDD, and EQ low levels are approximately equal to 0V.
When EQ generating elements 508 are in high VDDWhen operating under operating condition, as shown in Figure 8 B, power control signal PWCTL quilts
Low level is set to, to keep transistor M72 to be not turned on and transistor M76 conductings.According to embodiments of the invention, second is electric
Transistor M74 in road branch 704 is controlled by a reference voltage Vref so that transistor M74 is maintained at a local and turns on
State, and there is a pressure drop VSHAREThe drain electrode and source electrode of (such as about 2V) across transistor M74.Therefore, when transistor M75 leads
When logical, it is not about V to apply to the voltage of EQ lead-out terminalsDDVoltage, but about VDD-VSHAREVoltage.That is, by
Reference voltage VrefThe transistor M74 for being controlled is the voltage clamp that will be exported by EQ lead-out terminals as voltage clamping components
In EQ clamp level VCLAMP, approximately equal to VDD-VSHARE。
In certain embodiments, other electronic components can be used as voltage clamping components rather than VrefThe crystal of control
Pipe M74.For example, the FET of diode, or decoupling condenser are coupled to, voltage clamping components can be also normally used as.Make
The area of booster circuit 100 can be reduced with the FET for being coupled to diode, it is because being not required to produce reference voltage V with circuitref。
As described above, in high VDDDuring operation, power control signal PWCTL is set to low level, makes transistor M72 exist
This operation during be not turned on, equivalent to tertiary circuit branch 706 include transistor M72 and only include transistor M73 and
M77.As can be seen from Figure 7, the transistor M77 in the tertiary circuit branch 706 and transistor M75 in second circuit branch 704
Both are controlled by identical secondary signal PB2 (i.e. the inversion signal of the 2nd EQ input signals EQIN2).Because transistor
M75 and M77 belong to opposite types (in the example shown in Fig. 7, one for p-MOS another be n-MOS), so they according to
It is switched on and is not turned on to sequence.That is, when transistor M75 is turned on, transistor M77 is not turned on, and vice versa.Equally
Ground, transistor M71 and M73 also belong to opposite types and are by identical the first signal PB1 (i.e. EQ input signals EQIN1
Inversion signal) controlled, so as to turning in order and being not turned on.That is, when transistor M71 is turned on, transistor M73 is not
Conducting, and vice versa.This mechanism is guaranteed in high VDDDuring operation, the first circuit branch 702, second circuit branch 704 and
Tertiary circuit branch 706 is sequentially exported to EQ lead-out terminals 708, and with the level for producing an EQ signal EQ1 the high electricity of EQ is sequentially
Flat (about VDD), EQ clamp levels (about VDD-VSHARE) and EQ low levels (about 0V).
Fig. 8 B are illustrated when the EQ generating elements 508 of the illustration shown in Fig. 7 are in high VDDEQ when working under operating condition
The illustration waveform of input signal EQIN1, secondary signal PB2, power control signal PWCTL and an EQ signal EQ1.According to this
Bright embodiment, secondary signal PB2 is the waveform similar to the first signal PB1, is by the another of sequential and voltage control zone block 104
One section and produce.That is, secondary signal PB2 is substantially the inversion signal of the 2nd EQ input signals EQIN2.Fig. 8 A and Fig. 8 B
Also show the 2nd EQ signals EQ2 in low V respectivelyDDWith high V during operationDDWaveform during operation is using as comparing use.
As discussed above waveform (that is, the first boosting source signal BST1, the second boosting source signal BST2, the
One EQ signals EQ1 and the 2nd EQ signal EQ2) it is to be input into as illustrated in fig. 3 to boost in voltage block 106, to produce first
Boost frequency signal CK1 and the second boost frequency signal CK2.Fig. 9 A and Fig. 9 B is shown in respectively low VDDWith high VDDDuring operation
An EQ signal EQ1, the 2nd EQ signal EQ2, first boosting source signal BST1, second boosting source signal BST2, first
The illustration ripple of boost signal BT1, the second boost signal BT2, the first boost frequency signal CK1 and the second boost frequency signal CK2
Shape.When the first boost signal BT1 is located at boosted-high level VBOOSTWhen, the first boost frequency signal CK1 is also located at boosting altofrequency
Level VBOOST- CK, it is approximately equal to boosted-high level VBOOST.In fact, due to the dead resistance and electricity of for example transistor M33
Hold, positioned at boosting high frequency level V of the first boost frequency signal CK1BOOST- CK is likely lower than positioned at the first boost signal BT1
Boosted-high level VBOOST.Similarly, when the second boost signal BT2 is located at boosted-high level VBOOSTWhen, the second boost frequency letter
Number CK2 is also located at boosting high frequency level VBOOST- CK, it is approximately equal to boosted-high level VBOOST.In fact, due to for example brilliant
The dead resistance and electric capacity of body pipe M34, positioned at boosting high frequency level V of the second boost frequency signal CK2BOOST- CK may be low
In the boosted-high level V positioned at the second boost signal BT2BOOST。
Can be seen that from Fig. 9 B, in high VDDDuring operation, the 2nd EQ signals EQ2 is located at EQ clamp level VCLAMPTime week
Phase, is to cover (encompass) first boost frequency signal CK1 to be located at boosting high frequency level VBOOSTThe time cycle of-CK.Together
Sample ground, an EQ signals EQ1 is located at EQ clamp level VCLAMPTime cycle, be to cover the second boost frequency signal CK2 to be located at
Boosting high frequency level VBOOSTThe time cycle of-CK.That is, can cause switch element (i.e. Fig. 3 whenever output boost signal is located at
Switching transistor in shown example) collapse boosting high frequency level when, one be equal to EQ clamp level VCLAMPVoltage
The grid of switching transistor is just applied to, pressure drop of the switching transistor between grid and source electrode can be so reduced, is used and is kept away
Exempt from switching transistor collapse.According to embodiments of the invention, EQ clamp level VCLAMPCan be by control across a voltage clamp bit
The pressure drop V of part (such as the transistor M74 shown in Fig. 7)SHAREAnd control.Across the pressure drop V of transistor M74SHARECan be by control
Reference voltage VrefAnd control.
For simplified illustration, each edge of each waveform shown in the drawings of the present invention be depicted as one it is straight
Vertical line.We may be noted that and prolong caused by the delay institute controlled due to such as parasitism RC circuits, grid delay or frequency counter
Late, edge cannot be straight vertical line, and be probably to bend, bend or inclined line.Additionally, in the present invention, it is assumed that electricity
Pressure boosting block 106 is symmetrical, and therefore from the left side of boost in voltage block 106 and the output of right-hand part that are analogous to
This, except the phase place difference of each of which.For example, as shown in Fig. 9 A and Fig. 9 B, the boostings of the first boost signal BT1 and second
The waveform of signal BT2 is mutually the same, the boostings of the first boost frequency signal CK1 and second in addition to the phase place of each of which
Frequency signal CK2 is mutually the same in addition to the phase place of each of which.But in fact, due in booster circuit 100,
Have differences between sign identical electronic component, the output from the left side of boost in voltage block 106 and right-hand part may
It is different each other.For example, the boosted-high level of the first boost signal BT1 is likely differed from positioned at the second boost signal
The boosted-high level of BT2, and the boosting high frequency level of the first boost frequency signal CK1 likely differs from the second boost frequency letter
The boosting high frequency level of number CK2.
In sum, although the present invention is disclosed above with preferred embodiment, so it is not limited to the present invention.This
Bright those of ordinary skill in the art, without departing from the spirit and scope of the present invention, when various changes can be made
With retouching.Therefore, protection scope of the present invention is when depending on being defined that appended claims scope is defined.
Claims (9)
1. a kind of booster circuit, including：
One power rail, to provide a supply voltage；
One switching transistor, controls the output of a boost signal, and the switching transistor has a grid；And
One sequential and voltage control circuit, to produce first (Equalization, EQ) signal, the EQ signals are applied to
The grid of the switching transistor, the EQ signals have a level, and the level is an EQ high level, an EQ low levels and an EQ
One of them of clamp level, the EQ low levels are less than the EQ high level, and the EQ clamp levels are between the EQ low levels and the EQ
Between high level；
Wherein, whenever output boost signal be located at can cause switching transistor collapse boosting high frequency level when, sequential and
The EQ signals that voltage control circuit is produced just are applied to the grid of the switching transistor, can so reduce switching transistor in grid
Pressure drop between pole and source electrode, uses and avoids switching transistor from collapsing.
2. booster circuit according to claim 1,
Wherein the boost signal has a boosted-high level during the cycle very first time, has during one second time cycle
There is a low level；
Wherein the sequential and voltage control circuit include：
One first circuit branch, is connected between the power rail and a lead-out terminal, and the lead-out terminal is coupled to the switch crystal
The grid of pipe, first circuit branch is during one the 3rd time cycle, to produce the EQ high level to the outfan
Son；
One second circuit branch, is connected between the power rail and the lead-out terminal, and the second circuit branch is to one
During four time cycles, the EQ clamp levels are produced to the lead-out terminal；And
One tertiary circuit branch, is connected between an earth terminal and the lead-out terminal, and the tertiary circuit branch is to one
During five time cycles, the EQ low levels are produced to the lead-out terminal；
Wherein, the switching transistor is not turned on when the EQ signals are located at the EQ high level, and it is low to be located at the EQ in the EQ signals
Turn on when level or the EQ clamp levels, and
Wherein, the 4th time cycle cover the cycle very first time.
3. booster circuit according to claim 2, wherein：
First circuit branch includes a transistor, and the transistor is turned on during the 3rd time cycle so that the outfan
Son is electrically coupled to the power rail, and
The EQ high level is equal to the supply voltage.
4. booster circuit according to claim 2, wherein：
The second circuit branch includes：
One transistor, the transistor is turned on during the 4th time cycle；And
One voltage clamping components, are electrically coupled to the transistor, the voltage clamp that the voltage clamping components export the lead-out terminal
Position to the EQ clamp levels, and
The EQ clamp levels are less than the supply voltage.
5. booster circuit according to claim 4, wherein：
The transistor is a first transistor, and
The voltage clamping components include the transistor seconds controlled by a reference voltage, so that the transistor seconds local is led
It is logical, and the pressure drop across the transistor seconds is high enough to so that the voltage of the lead-out terminal output is clamped on the EQ pincers
Bit level.
6. booster circuit according to claim 1, further includes a discharge path, and electric property coupling is in the switching transistor and
Between earth terminal, the discharge path includes：
One discharge transistor, is electrically coupled to the earth terminal, and the discharge transistor is switched on low so that the boost signal is pulled to into one
Level；And
One Low threshold transistor, electric property coupling between the discharge transistor and the switching transistor, the Low threshold transistor
One grid is electrically coupled to the power rail.
7. booster circuit according to claim 1, wherein：
The boost signal is one first boost signal, and first boost signal has one first liter during the cycle very first time
Pressure high level, has one first low level during one second time cycle, and first boosted-high level is higher than the switch crystal
One breakdown voltage of pipe, and
, more to control the output of one second boost signal, second boost signal is by the switching transistor for the switching transistor
Source electrode is exported, and second boost signal has one second boosted-high level during one the 3rd time cycle, in one the 4th time
There is one second low level, the breakdown voltage of second boosted-high level less than the switching transistor during cycle.
8. it is a kind of control boost signal output method, including：
An EQ signals with a level are produced, the level is an EQ high level, an EQ low levels and an EQ clamp levels
One of them, the EQ low levels are less than the EQ high level, the EQ clamp levels between the EQ low levels and the EQ high level it
Between；And
Apply a grid of the EQ signals a to switching transistor, use the output for controlling the boost signal；
Wherein：The boost signal has a boosted-high level during the cycle very first time, during one second time cycle
With a low level,
Producing the EQ signals includes：The EQ high level is produced during one the 3rd time cycle, during one the 4th time cycle
The EQ clamp levels are produced, and the EQ low levels are produced during one the 5th time cycle；
Applying the grid of the EQ signals to the switching transistor includes：Apply the EQ high level during the 3rd time cycle
To the grid of the switching transistor, so that the switching transistor is not turned on, the EQ pincers is applied during the 4th time cycle
The grid of bit level to the switching transistor, to turn on the switching transistor, and applies to be somebody's turn to do during the 5th time cycle
The grid of EQ low levels to the switching transistor, to turn on the switching transistor, and the 4th time cycle cover this first
Time cycle.
9. method according to claim 8, further includes：
Produce one to boost source signal, to boosted producing the boost signal；And
An EQ input signals are produced, to produce the EQ signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310611534.3A CN104682701B (en) | 2013-11-26 | 2013-11-26 | Boosted circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310611534.3A CN104682701B (en) | 2013-11-26 | 2013-11-26 | Boosted circuit |
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| Publication Number | Publication Date |
|---|---|
| CN104682701A CN104682701A (en) | 2015-06-03 |
| CN104682701B true CN104682701B (en) | 2017-04-26 |
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ID=53317401
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310611534.3A Active CN104682701B (en) | 2013-11-26 | 2013-11-26 | Boosted circuit |
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| Country | Link |
|---|---|
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8149032B2 (en) * | 2006-11-30 | 2012-04-03 | Mosaid Technologies Incorporated | Circuit for clamping current in a charge pump |
| CN102903384A (en) * | 2011-07-25 | 2013-01-30 | 旺宏电子股份有限公司 | Standby charge pump device and method for operating same |
| CN103003881A (en) * | 2010-07-08 | 2013-03-27 | 尹在万 | Semiconductor memory device |
| CN103326578A (en) * | 2012-03-19 | 2013-09-25 | 旺宏电子股份有限公司 | Voltage booster system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3872927B2 (en) * | 2000-03-22 | 2007-01-24 | 株式会社東芝 | Booster circuit |
-
2013
- 2013-11-26 CN CN201310611534.3A patent/CN104682701B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8149032B2 (en) * | 2006-11-30 | 2012-04-03 | Mosaid Technologies Incorporated | Circuit for clamping current in a charge pump |
| CN103003881A (en) * | 2010-07-08 | 2013-03-27 | 尹在万 | Semiconductor memory device |
| CN102903384A (en) * | 2011-07-25 | 2013-01-30 | 旺宏电子股份有限公司 | Standby charge pump device and method for operating same |
| CN103326578A (en) * | 2012-03-19 | 2013-09-25 | 旺宏电子股份有限公司 | Voltage booster system |
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|---|---|
| CN104682701A (en) | 2015-06-03 |
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