CN104681437A - Semiconductor device with strained channel and preparation method thereof - Google Patents
Semiconductor device with strained channel and preparation method thereof Download PDFInfo
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- CN104681437A CN104681437A CN201310612752.9A CN201310612752A CN104681437A CN 104681437 A CN104681437 A CN 104681437A CN 201310612752 A CN201310612752 A CN 201310612752A CN 104681437 A CN104681437 A CN 104681437A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 16
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
The invention mainly relates to a semiconductor device, in particular to a semiconductor device with a strained Ge channel and a preparation method thereof. Firstly, an insulating layer is formed and covers on an SOI (Silicon On Insulator) layer and the insulating layer is etched to form an opening; the SOI layer and a buried oxide below the insulating layer are etched by the opening and a channel structure positioned in the SOI layer and the buried oxide is formed; etching is carried out until a substrate is exposed in the channel structure; a strained epitaxial layer is formed at the bottom of a grid channel formed by abutting the channel structure with the opening; a grid oxide layer is formed on the strained epitaxial layer; a grid positioned on the grid oxide layer is formed at the top of the grid channel.
Description
Technical field
The present invention relates generally to semiconductor device, or rather, relates to one and has semiconductor device of strain Ge raceway groove (Strain Ge channel) and preparation method thereof.
Background technology
At integrated circuit industry, along with the scales of MOSFET declines, due to dielectric layer tunnelling current and oxidated layer thickness exponent function relation, a challenge is just that the thickness of gate dielectric layer can not infinitely reduce, such as, for traditional Si O
2or SiON dielectric layer, when thickness is reduced to 1nm, will cause complete device failure.Especially short-channel effect SCE(Short Channel Effect) be the phenomenon common when reducing of cmos device channel length, it can cause threshold voltage shift, even Punchthrough, drain-induced barrier reduces DIBL(Drain induction barrier lower) etc. characteristic, cmos device performance failure can be caused time serious, SCE can explain with the charge-sharing model that L.D.Yau proposes, be loaded in document " A simple theory to predict the threshold voltage of a short-channel IGFET's.Solid-State Electron..17.pp.1059-1063(1974) ", namely when raceway groove shortens, source serves as a contrast, the ratio that leakage lining PN junction shares raceway groove depletion region electric charge and raceway groove total electrical charge will increase, thus cause grid-control ability to decline.
Some are based on for ultra-shallow junctions USJ(Ultra shallow junction) technology be applied to the preparation technology of integrated circuit, the phase wing overcomes short-channel effect to a certain extent, but thing followed drawback also highlights in the lump, the thorny problems such as such as negative drain junction capacitance and junction leakage be difficult to suppress, this for tool two step drain-source injection technology NMOS problem become particularly serious.The high pressure of voltage source makes drain region and bag-like region (Halo) have higher electric field, when being used for when adopting heavily doped Halo suppressing break-through and SCE, and electric field value performance get Geng Gao.In order to obtain preferably SCE and tool more at a high speed and low junction capacitance, low junction leakage semiconductor device, at 65nm and with in the technique of lower node, HKMG technique is at lightly doped drain LDD(Low doped drain) after employing SiGe and side-wall technique.Wafer can receive test WAT(Wafer Acceptance Test) show not so good DIBL and turn off leakage current Ioff effect, a maximum difficult problem be, even if optimize the Implantation Energy of lightly doped drain LDD and bag-like region Packet, dosage, implant angle to greatest extent or even implement the means such as two bag-like region Packet injections, the effect of best DIBL, Ioff all cannot be reached.The SiGe that current HKMG adopts after LDD and side wall, unfavorable factor is the Negative Bias Temperature Instability effect NBTI(Negative bias temperature instability being easy to bring out) and hot carrier injection effect HCI(Hot carrier injection), to a great extent, can ascribe to when forming the groove of SiGe, and adjacent gate edge heavily stressed in the SiGe that causes of the extension original position Ge epitaxial growth that forms the step middle and high concentration of SiGe.。
Summary of the invention
In one embodiment of the invention, provide the preparation method of the semiconductor device with strained-channel, a buried oxide layer and a SOI(Silicon-on-insulator is disposed with in a substrate) layer, mainly comprise the following steps: form an insulating barrier and cover on soi layer; Etching insulating layer forms an opening; Nationality etches soi layer below it, buried oxide layer form the groove structure being arranged in soi layer, buried oxide layer by opening, and exposes substrate in groove structure; A strained epilayer is formed in the bottom of the gate trench formed by described groove structure and described open butt joint; A grid oxic horizon is formed on strained epilayer; The grid on grid oxic horizon is positioned in the top of gate trench formation one.
Above-mentioned method, after forming described grid, etches the through hole that described insulating barrier forms the soi layer aiming at gate trench both sides; And the region being exposed to via bottoms at soi layer upper surface forms metal silicide, and then fill metal material in through hole.
Above-mentioned method, before forming metal silicide, the part first utilizing through hole to be arranged in via bottoms at soi layer implants alloy, forms the heavily doped region that a doping content is greater than soi layer doping content.
Above-mentioned method, removes described insulating barrier after forming grid, then on the sidewall of the stack grid structure be made up of grid and grid oxic horizon, forms side wall, and implement following steps: on the region that soi layer upper surface exposes, form metal silicide; Depositing an interlayer dielectric layer covers above soi layer, stack grid structure and side wall; Etching interlayer dielectric layer forms the through hole of the soi layer of alignment grooves structure both sides; Metal material is filled in through hole.
Above-mentioned method, before forming metal silicide, and before or after the step forming side wall, two regional areas of the soi layer respectively near groove structure both sides be arranged in below grid oxic horizon two ends at the upper epidermis of strained epilayer adulterate, and form Liang Ge LDD district respectively.
Above-mentioned method, after forming grid, described insulating barrier is removed, then on the sidewall of the stack grid structure be made up of grid and grid oxic horizon, side wall is formed, and implement following steps: on soi layer, form a resilient coating, the maximum height controlling its upper surface is no more than the upper surface of stack grid structure, and resilient coating is insulated by side wall and stack grid structure and isolates; The upper surface of resilient coating forms metal silicide; Depositing an interlayer dielectric layer covers above resilient coating, stack grid structure and side wall; Etching interlayer dielectric layer forms the through hole of the resilient coating of aligned stack formula grid structure both sides; Metal material is filled in through hole.
Above-mentioned method, before forming resilient coating, and before or after the step forming side wall, two regional areas of the soi layer respectively near groove structure both sides be arranged in below grid oxic horizon two ends at the upper epidermis of strained epilayer adulterate, and form Liang Ge LDD district respectively.
Above-mentioned method, in the step forming resilient coating, with in-situ doped mode implanting dopants in resilient coating, to improve the doping content of resilient coating.
Above-mentioned method, is formed before insulating barrier, in the epitaxial process of soi layer, is implanted into alloy in in-situ doped mode at soi layer, or is implanted into alloy to the mode that established soi layer carries out ion implantation at soi layer.
Above-mentioned method, also implements over etching to described substrate in the step forming groove structure, and etching stops in the substrate to make the bottom of described groove structure extend downward in described substrate.
Above-mentioned method, in the step of strained epilayer described in epitaxial growth, the height and position of the upper surface of controlled strain epitaxial loayer, comprising: the upper surface of controlled strain epitaxial loayer higher than soi layer upper surface height and position but lower than the height and position of insulating barrier upper surface; Or the upper surface of controlled strain epitaxial loayer and the upper surface flush of soi layer.
Above-mentioned method, described soi layer is SiC layer, described substrate be comprise Si substrate substrate or for comprising Si substrate and being arranged on the substrate of Ge or the SiGe epitaxial loayer on Si substrate, described strained epilayer is Ge or SiGe, described insulating barrier is SiN, and described resilient coating is SiC or Si.
In another embodiment, the invention provides the preparation method of the semiconductor device with strained-channel, be disposed with a buried oxide layer and a soi layer in a substrate, mainly comprise the following steps: form an insulating barrier and cover on soi layer; Etching insulating layer forms an opening; Nationality etches soi layer below it, buried oxide layer form the groove structure being arranged in soi layer, buried oxide layer by opening, and exposes substrate in groove structure; A strained epilayer is formed in the gate trench formed by described groove structure and described open butt joint; A grid oxic horizon is formed on strained epilayer; Form a gate material layers to cover on insulating barrier and grid oxic horizon, and gate material layers described in patterning is to form the grid be positioned on grid oxic horizon; The sidewall of the stack grid structure be made up of grid and grid oxic horizon forms side wall; Remove described insulating barrier and on soi layer, form a resilient coating.
Above-mentioned method, is formed before insulating barrier, in the epitaxial process of soi layer, is implanted into alloy in in-situ doped mode at soi layer, or is implanted into alloy to the mode that established soi layer carries out ion implantation at soi layer.
Above-mentioned method, formed in the step of strained epilayer, the height and position of the upper surface of controlled strain epitaxial loayer, comprising: the upper surface of controlled strain epitaxial loayer and the upper surface flush of insulating barrier, and makes the bottom face of side wall and the upper surface flush of insulating barrier.
Above-mentioned method, formed in the step of strained epilayer, the height and position of the upper surface of controlled strain epitaxial loayer, comprise: the height of the upper surface of controlled strain epitaxial loayer higher than the upper surface of insulating barrier, and make the bottom of side wall along the sidewall of stack grid structure extend downward its bottom face lower than the upper surface of strained epilayer and with the upper surface flush of insulating barrier.
Above-mentioned method, in the step of resilient coating described in epitaxial growth, control the height and position of the upper surface of resilient coating, comprise: make the thickness of resilient coating be equal to or greater than the original thickness of insulating barrier, but the height and position controlling the upper surface of resilient coating is no more than the height and position of stack grid structure upper surface.
Above-mentioned method, is characterized in that, is formed after resilient coating, and two regional areas of the resilient coating respectively near strained epilayer both sides be arranged in below grid oxic horizon two ends at the upper epidermis of strained epilayer adulterate, and form Liang Ge LDD district respectively.
In some embodiments, the invention provides a kind of semiconductor device with strained-channel, be disposed with a buried oxide layer and a soi layer in a substrate, comprise: be arranged on the insulating barrier of one on soi layer with opening; Be formed in the groove structure in soi layer, buried oxide layer, groove structure and overlapping open butt joint above it form a gate trench; Be filled in the strained epilayer bottom gate trench; Be formed in the grid oxic horizon on strained epilayer; Be filled in one of gate trench top and be positioned at grid on grid oxic horizon; In strained epilayer wherein between the source area that nationality is made up of respectively the soi layer of gate trench both sides and drain region, be formed with a lateral channel district.
Above-mentioned semiconductor device, soi layer is SiC, and wherein doped with the alloy of N-type.
Above-mentioned semiconductor device, groove structure is to downward-extension until extend in substrate bottom it.
Above-mentioned semiconductor device, is provided with the through hole of the soi layer aiming at gate trench both sides respectively in insulating barrier; And described soi layer be arranged in via bottoms part implant have alloy, form the heavily doped region that a doping content is greater than soi layer doping content; The region that described soi layer upper surface is positioned at via bottoms is formed with metal silicide, and in through hole, is filled with the metal material of metal silicide in electrical contact.
Above-mentioned semiconductor device, the upper surface of strained epilayer is higher than the upper surface of described soi layer or the upper surface flush with described soi layer.
In other execution modes, the invention provides a kind of semiconductor device with strained-channel, be disposed with a buried oxide layer and a soi layer in a substrate, comprise: be formed in the groove structure in soi layer, buried oxide layer; Be filled in the strained epilayer in gate trench; Be formed in the grid oxic horizon on strained epilayer; Be arranged on the grid on grid oxic horizon; Cover the side wall on the sidewall of the stack grid structure be made up of grid and grid oxic horizon; In strained epilayer wherein between the source area that nationality is made up of respectively the soi layer of groove structure both sides and drain region, be formed with a lateral channel district.
Above-mentioned semiconductor device, is provided with a resilient coating on soi layer, and the height and position of its upper surface is no more than the upper surface of stack grid structure, and resilient coating is insulated by side wall and stack grid structure and isolates.
Above-mentioned semiconductor device, described soi layer is SiC and doped with the alloy of N-type, and described resilient coating is SiC or Si and doped with N-type dopant.
Above-mentioned semiconductor device, it is characterized in that, the upper surface of strained epilayer higher than the upper surface of described soi layer, wherein side wall bottom along the sidewall of stack grid structure extend downward its bottom face lower than the upper surface of strained epilayer and with the upper surface flush of SOI.
Above-mentioned semiconductor device, is characterized in that, the upper surface of strained epilayer and the upper surface flush of soi layer, wherein the bottom face of side wall and the upper surface flush of soi layer.
Above-mentioned semiconductor device, is characterized in that, is arranged in two regional areas of the soi layer respectively near groove structure both sides below grid oxic horizon two ends doped with alloy at the upper epidermis of strained epilayer, forms Liang Ge LDD district.
In some embodiments, the invention provides a kind of semiconductor device with strained-channel, a buried oxide layer and a soi layer is disposed with in a substrate, comprise: be formed in the groove structure in soi layer, buried oxide layer, with the strained epilayer be arranged in groove structure, wherein strained epilayer extends upwardly to the upper surface that its top protrudes from soi layer; The grid being formed in the grid oxic horizon on strained epilayer and being arranged on grid oxic horizon; Cover the side wall on the sidewall of the stack grid structure be made up of grid and grid oxic horizon; Be positioned at the resilient coating on soi layer, it is at least coated on strained epilayer and protrudes from the sidewall of the part of soi layer upper surface; At nationality by strained epilayer between the source area that the part of strained epilayer both sides is formed respectively and drain region of the lamination of soi layer, resilient coating, form a lateral channel district.
Above-mentioned semiconductor device, the bottom face of side wall and the upper surface flush of strained epilayer; And the upper surface of resilient coating and the upper surface flush of strained epilayer or higher than strained epilayer upper surface but be no more than the height of the upper surface of stack grid structure.
Above-mentioned semiconductor device, the bottom of side wall extends downward the upper surface of its bottom face lower than strained epilayer along the sidewall of stack grid structure; And the upper surface of resilient coating flushes with the bottom face of sidewall or higher than sidewall bottom face but be no more than the height of the upper surface of stack grid structure.
Above-mentioned semiconductor device, is arranged in two regional areas of the resilient coating respectively near strained epilayer both sides below grid oxic horizon two ends doped with alloy at the upper epidermis of strained epilayer, forms Liang Ge LDD district.
Accompanying drawing explanation
Read following detailed description also with reference to after the following drawings, Characteristics and advantages of the present invention will be apparent:
Figure 1A to 1H is the semiconductor device of preparation strain of the present invention Ge raceway groove and the method flow schematic diagram finally retained by the insulating barrier in SOI wafer that proposes.
Fig. 2 A to 2C is step based on Figure 1A ~ 1H but need removes the method flow schematic diagram of insulating barrier.
Fig. 3 A to 3B is step based on Fig. 2 A ~ 2B but on SOI, additionally prepares the method schematic diagram of resilient coating.
Fig. 4 A to 4H-2 is the semiconductor device of preparation strain of the present invention Ge raceway groove and being removed by the insulating barrier in SOI wafer of proposing and additionally prepares the method flow schematic diagram of resilient coating.
What Fig. 5 A to 5B showed is the generalized section of the various alternate configurations of grid.
Embodiment
See Fig. 1, illustrate one and be usually referred to as SOI(Silicon-on-insulator) generalized section of wafer, in the present invention, the upper surface of substrate 101 is formed with an oxide skin(coating) such as SiO
2, be normally defined buried oxide layer 102, and have a soi layer 103 at buried oxide layer 102 Epitaxial growth.In some Alternate embodiments, substrate 101 can be a substrate comprising Si substrate, or above Si substrate the substrate of epitaxial growth Ge or SiGe epitaxial loayer, and soi layer 103 can be the SiC layer of a thickness at 20nm ~ 0.2um.In some optional execution modes, can in the epitaxial process of soi layer 103, alloy is implanted at soi layer 103 in the mode that original position (In-situ) is adulterated, or again with the mode of ion implantation implanting dopants in soi layer 103 after forming soi layer 103 in advance.The present invention is follow-up will be launched to describe for NMOS unit, therefore setting the alloy be infused in soi layer 103 is N-type dopant, as phosphorus and/or arsenic etc., but it should be noted that, if change the material of soi layer 103 after reading the present invention, as Si etc., or the type of ion is injected in adjustment, all should regard as the intent and scope of the present invention.In addition, it is also understood that, when research object of the present invention is transplanted to CMOS, be commonly used to the conventional device architectures such as fleet plough groove isolation structure STI or PMOS of the respective active well region of isolation NMOS and PMOS and all can utilize known standard technology preparation, for simplicity, these conventional devices do not represent one by one in the present invention is graphic.
See Figure 1B, soi layer 103 forms an insulating barrier 104, existing the present invention is described for the single layer structure depositing a SiN layer, but the lamination layer structure of insulating barrier 104 also multilayer dielectric substrate.Then spin coating photoresist (not shown) above insulating barrier 104, and perform photoetching technique, utilize thereafter photoresist to carry out etching insulating layer 104 as etch mask, form an opening 104a in insulating barrier 104, then ashing removes photoresist.See Fig. 1 C, continue using insulating barrier 104 as hard mask dry etching buried oxide layer 102 and soi layer 103, by them, the partial etching be positioned at separately below opening 104a falls, and forms the groove structure 150 being arranged in buried oxide layer 102, soi layer 103, to expose substrate 101.A kind of situation is that etching just terminates in the upper surface of substrate 101, and substrate 101 is almost without any loss; Another kind of situation is, after etching runs through buried oxide layer 102, soi layer 103, continue etched substrate 101 until a part for substrate 101 is also etched away, haply, the degree of depth that substrate 101 is etched can reach tens nanometers or darker.Clearly, groove structure 150 by opening 104a by etching transfer and formed, if observed downwards from the direction orthogonal with wafer place plane, the sectional dimension being positioned at horizontal plane both them and shape substantially completely the same.According to aforementioned etching mode, the bottom of groove structure 150 can with the upper surface flush of substrate 101, or the bottom of groove structure 150 also can extend downward in substrate 101.
See Fig. 1 D-1, docked by groove structure 150 and the opening 104a overlapped on above it and define a gate trench, in gate trench, optionally carry out epitaxial growth to form a strained epilayer (Strain epitaxial layer) 105 as follow-up strained channel region, such as, grow the epitaxial loayer of Ge or SiGe.In the step of growth strain epitaxial loayer 105, namely its thickness of adjustable, also control the height and position of its upper surface, can form the slightly discrepant semiconductor device of structure like this, and produce the electrical effect be not quite similar.For the ease of understanding, we define short transverse and refer to the direction orthogonal with SOI wafer or substrate place plane, Fig. 1 D-1 shows the roughly coplanar situation of the upper surface of the upper surface of epitaxial loayer 105 and soi layer 103, and Fig. 1 D-2 shows the situation of height and position a little more than the upper surface of soi layer 103 of epitaxial loayer 105 upper surface.Fig. 1 E is the subsequent step of example based on Fig. 1 D-1, and after forming strained epilayer 105, form a grid oxic horizon 106 in its surface, if epitaxial loayer 105 comprises Ge, then grid oxic horizon 106 is GeO
2if epitaxial loayer 105 comprises SiGe, then grid oxic horizon 106 comprises GeO
2and SiO
2.
Due to the bottom grown epitaxial loayer that Fig. 1 D-1 is only at gate trench, then in the step of Fig. 1 F, form a grid 107 at the top of gate trench, grid 107 is positioned at the top of grid oxic horizon 106.The step of formation grid 107 can be above first cover gate material layer to insulating barrier 104 and make a part for gate material layers be filled in the headroom of gate trench, and then dry etchback or cmp gate material layers, the part only gate material layers being filled in gate trench top is retained as grid 107.As shown in Figure 1 G, the mask with opening (not illustrating) etching insulating layer 104 above insulating barrier 104 is positioned at one, now the soi layer 103 of groove structure 150 both sides is respectively respectively as source area and the drain region of NMOS unit, then etching insulating layer 104 at least forms the some through holes 108 aiming at source area and drain region respectively, through hole 108 runs through insulating barrier 104, then by injecting ion in the soi layer 103 of through hole 108 below through hole 108, as the N-type dopant such as phosphorus and/or arsenic, usually the ion implantation sayed is toward the step of contact along with high annealing and diffusion, to form the heavily doped region 103a be positioned at bottom through hole 108 in soi layer 103, the doping content of heavily doped region 103a is much larger than the original doping content of soi layer 103, heavily doped region 103a is made to have less resistance.Then as Fig. 1 H, the region that soi layer 103 upper surface is exposed to bottom through hole 108 is formed the metal silicide 103b between the 103a of heavily doped region with less contact resistance, and then filling metal material 108a and metal silicide 103b forms and interconnects through hole 108 in.
In Fig. 1 H, in surface region near the upper surface regarding as the strained epilayer 105 of body zone, a lateral channel district between source-drain area is formed along grid oxic horizon 106, a kind of reasonable dismissal of the present invention is, strain is produced when lattice is subject to stress, the effective mass of transmission charge carrier can be reduced, mobility and saturated velocity all increase, therefore under same size of components, strain gauge material is as the transmission channel of charge carrier, because the carrier mobility in its electronics and hole increases, the target increasing transistor unit speed and drive current can be reached, on the whole, strain gauge technique stretches to strain gauge material, thus accelerate the flowing of electronics in chip, miniaturization need not be carried out just can improve performance and reduce power consumption.
In the device of Fig. 1 D-1 and Fig. 1 H, the upper surface of strained epilayer 105 and the upper surface flush of soi layer 103.And in the device of Fig. 1 D-2, the height and position of the upper surface of strained epilayer 105 is higher than the height and position of the plane at the upper surface place of soi layer 103, consider once the distance between the upper surface of strained epilayer 105 and the upper surface of soi layer 103 is excessive, easily bring out the inversion layer formed in the upper epidermis of strained epilayer 105 diminish with the contact point in drain/source interval or do not contact and effective conducting channel cannot be formed, so should the upper surface of limit strain epitaxial loayer 105 to the interplanar distance of soi layer 103 upper surface, such as be set as 0 ~ 10 ran.
In one embodiment, the flow process of Fig. 1 G ~ 1H is not performed after completing the step of Fig. 1 F, but perform the flow process of Fig. 2 A ~ 2B, namely after forming grid 107, insulating barrier 104 corrosion is removed, then on the sidewall of the stack grid structure be made up of grid 107 and grid oxic horizon 106, side wall 110 is formed, the preparation of side wall 110 is generally first such as, by deposition side wall layer, SiO
2, cover on stack grid structure and soi layer 103, then return side wall layer at quarter, only retain the part that is attached on stack grid structure sidewall as side wall 110.In fig. 2, as optional but nonessential step, can before preparing side wall 103, perform lightly doped drain LDD district (Lightly Doped Drain) technique, be injected into the N-type dopant on soi layer 103 top layer as phosphorus, arsenic can diffuse laterally into below stack grid structure under the high temperature conditions, upper epidermis as being diffused into strained epilayer 105 lays respectively in two regional areas below grid oxic horizon 106 two ends, form LDD district 105a, 105b, LDD district 105a near and adjacent trench structure side such as the soi layer 103 of source area, the soi layer 103 as drain region of the close also opposite side that adjacent trench structure is relative of LDD district 105b, now LDD district 105a, 105b mainly relies on diffusion and completes doping.Or, in fig. 2, as optional but nonessential step, first prepare side wall 103, and then in the mode that angle-tilt ion is injected, namely the angle that between the direction of ion implantation and the central shaft of wafer, existence one is non-vanishing is set, upper epidermis N-type dopant being implanted to strained epilayer 105 is arranged in two regional areas below grid oxic horizon 106 two ends, tilt to inject and to be formed after LDD district 105a and can to tilt injection LDD district 105b around central shaft rotating wafer 180 ° again, now LDD district 105a, 105b mainly relies on ion and has directly injected doping.Wherein, with in-situ doped and the doping content diffuseing to form LDD district may be selected to be 1e19cm
-3~ 1e21cm
-3, and form LDD district in the mode directly injecting ion, then can, under Implantation Energy is 500KeV ~ 2000KeV condition, select to be roughly 3e14cm
-3~ 1e15cm
-3doping content.The region that just can expose at the upper surface of soi layer 103 afterwards forms metal silicide 103a, as the metal silicide 103a of Ti, Ni etc., as shown in Figure 2 B, deposit an interlayer dielectric layer 115 afterwards again and cover NMOS unit, as covered above soi layer 103, stack grid structure and side wall 110, and with the mask etching interlayer dielectric layer 115 do not illustrated, form aligning soi layer 103 respectively and be positioned at the drain region of groove structure both sides and several through hole 108' of source area, in through hole 108', fill metal material 108'a more afterwards.
In the device architecture of Fig. 2 B, can see the step of Fig. 1 D-1, the upper surface of strained epilayer 105 and the upper surface flush of soi layer 103, can be learned by its preparation technology, wherein the bottom face of side wall 110 and the upper surface flush of soi layer 103.And in the device architecture of Fig. 2 C, can see the step of Fig. 1 D-2, the upper surface of strained epilayer 105 is higher than the upper surface of soi layer 103, can be learned by its preparation technology, the bottom being wherein attached to the side wall 110 on the sidewall of stack grid structure both sides is along the sidewall of stack grid structure to downward-extension, until its bottom face lower than grid oxic horizon 106 lower surface and with the upper surface flush of soi layer 103, now side wall 110 also covers on the sidewall protruding from the part of soi layer 103 upper surface on strained epilayer 105 top.With Fig. 2 category-A seemingly, the device of Fig. 2 C also can be selected to prepare LDD district 105a, 105b, although this not necessarily, but consider and mentioned above, should distance between the upper surface of limit strain epitaxial loayer 105 and the upper surface of soi layer 103, in this case, LDD district 105a, 105b can be with the advantage of serving, when upper surface a little more than soi layer 103 of the upper surface of epitaxial loayer 105, LDD district 105a can connect the source area of NMOS unit, when LDD district 105b can connect the drain region of NMOS unit, this is useful to the effective conducting channel that cannot be formed being avoided the device of Fig. 2 C.
In the method flow of Fig. 3 A ~ 3B, identical with the flow process major part of Fig. 2 A ~ 2B, maximum difference is exactly, after forming side wall 110, need the extra silica-based resilient coating 103' of Epitaxial growth one at soi layer 103, and also need in resilient coating 103', to inject N-type dopant in in-situ doped mode in its epitaxial process, to improve the doping content of resilient coating 103', because resilient coating 103' lays respectively at two parts of stack grid structure both sides, using the part as source area and the part as drain region, so the conductivity that doping improves them is necessary.In this epitaxially grown step, require that the height and position of the upper surface of resilient coating 103' can not exceed the height of the upper surface of stack grid structure, and resilient coating 103' is coated on the outside of the side wall 110 of stack grid structure both sides, thus realizes insulating by side wall 110 and stack grid structure and isolate.In Fig. 3 A ~ 3B the height and position of strained epilayer 105 and Fig. 2 B ~ 2C similar, also can regulate, although do not illustrate in Fig. 3 B, can select to make the upper surface of strained epilayer 105 and the upper surface flush of soi layer 103, the bottom face of side wall 110 and the upper surface flush of soi layer 103; Or select to make the upper surface of strained epilayer 105 a little more than the upper surface of soi layer 103, the bottom of side wall 110 then along the sidewall of stack grid structure to downward-extension, until its bottom face lower than strained epilayer 105 upper surface and with the upper surface flush of soi layer 103.Equally, alternately, LDD district 105a, 105b can also be applied in the device of Fig. 3 A ~ 3B, it is worth emphasizing that, the doping in LDD district preferably just completed before preparing resilient coating 103', otherwise the Doped ions forming LDD district needs additionally to penetrate this resilient coating 103', and this has higher requirement to Implantation Energy or doping content.Therefore, the subsequent step of Fig. 3 B is roughly the same with Fig. 2 B, need on the upper surface of resilient coating 103', form metal silicide 103a, deposit an interlayer dielectric layer 115 and cover resilient coating 103', on stack grid structure and side wall 110, thereafter interlayer dielectric layer 115 is etched, formation runs through multiple through hole 108' in interlayer dielectric layer 115, these through holes 108' aims at two parts that resilient coating 103' is positioned at stack grid structure both sides respectively, need afterwards to fill metal material 108'a in through hole 108', because Fig. 2 B elaborates this, so these steps do not repeat in Fig. 3 A ~ 3B.Note in the device of Fig. 3 B, resilient coating 103' and the lamination both soi layer 103 lay respectively at two parts of groove structure both sides, using as the drain region of NMOS unit and source area.
In some other execution modes, the flow process of Figure 1A ~ 1C can be utilized to form the device architecture of Fig. 4 A, but different from a part of space that strained epilayer 105 is just filled into bottom gate trench by Fig. 1 D-1 and Fig. 1 D-2, in Fig. 4 A, strained epilayer 105' then will be filled full completely by opening 104a and groove structure 150.And, can select to make the upper surface of strained epilayer 105' and the upper surface flush of insulating barrier 104, also can select the height and position of the upper surface making the height and position of strained epilayer 105' upper surface higher than insulating barrier 104.When the top of strained epilayer 105' overflow and exceed the upper surface of insulating barrier 104 too much time, the pattern that roughly can be rendered as segment on strained epilayer 105' top, or cap-like structure, this is to preparing grid oxic horizon or grid is disadvantageous, so now generally need controlled strain epitaxial loayer 105' top to exceed the height value of the part of the upper surface of insulating barrier 104, such as control when 0 ~ 10 nanometer, to overcome this problem to greatest extent.Then on strained epilayer 105', a grid oxic horizon 106' is formed, and continue formation gate material layers 107' and cover on insulating barrier 104 and grid oxic horizon 106', as Fig. 4 B, and patterning gate material layers 107' is to form the grid 107'a be positioned on grid oxic horizon 106', as Fig. 4 C.Here the gate material layers 107' adopted can single layer structure also can be the polysilicon layer of sandwich construction, such as individual layer, or adopts sandwich construction preparation as stacked gate 207, the 207' of Fig. 5 A ~ 5B, and subsequent content will be introduced in detail.
In Fig. 4 D-1, the upper surface of strained epilayer 105' and the upper surface of insulating barrier 104 substantially flush, then after performing such as Fig. 2 A and forming the step of side wall 110', the bottom face of side wall 110' and the upper surface flush of insulating barrier 104.In Fig. 4 D-2, the height of the upper surface of strained epilayer 105' is higher than the upper surface of insulating barrier 104, then after the step performing such as Fig. 2 A formation side wall 110', the bottom of side wall 110' by the sidewall along the stack grid structure be made up of grid 107'a and grid oxic horizon 106' to downward-extension, until the bottom face of side wall 110' lower than strained epilayer 105' upper surface and with the upper surface flush of insulating barrier 104.What Fig. 4 E-1 showed is insulating barrier 104 corrosion in Fig. 4 D-1 removed, and what Fig. 4 E-2 showed is insulating barrier 104 corrosion in Fig. 4 D-2 removed.Based on spirit of the present invention, after insulating barrier 104 is removed, need again at the epitaxial buffer layer 103'' that soi layer 103 Epitaxial growth thickness is controlled, Fig. 4 F-1 is that soi layer 103 Epitaxial growth resilient coating 103'', Fig. 4 F-2 are soi layer 103 Epitaxial growth resilient coating 103'' in Fig. 4 E-2 in Fig. 4 E-1.
In a kind of execution mode of Fig. 4 F-1, in the step of epitaxial growth buffer 103'', the height and position of the upper surface of resilient coating 103'' can be controlled, make the thickness of resilient coating 103'' be equal to or greater than the original thickness of insulating barrier 104, but the height and position controlling the upper surface of resilient coating 103'' can not exceed the height and position of stack grid structure upper surface.The upper surface being equivalent to resilient coating 103'' can flush with the bottom face of the upper surface of strained epilayer 105' or side wall 110'; Or the upper surface of resilient coating 103'' higher than strained epilayer 105' upper surface but be no more than the height of stack grid structure upper surface, now resilient coating 103'' is coated on the outside of the side wall 110' of stack grid structure both sides, thus realizes insulating by side wall 110' and stack grid structure and isolate.In a kind of execution mode of Fig. 4 F-2, in the step of epitaxial growth buffer 103'', make the thickness of resilient coating 103'' be equal to or greater than the original thickness of insulating barrier 104, but the height and position controlling the upper surface of resilient coating 103'' is no more than the height and position of stack grid structure upper surface.The upper surface being equivalent to resilient coating 103'' can to flush with the bottom face of side wall 110' lower than the upper surface of strained epilayer 105'; Or the upper surface of resilient coating 103'' can not exceed the height of stack grid structure upper surface higher than the bottom face of side wall 110', now resilient coating 103'' is coated on the outside of the side wall 110' of stack grid structure both sides, thus realizes insulating by side wall 110' and stack grid structure and isolate.The in-situ doped of the alloy such as phosphorus and/or arsenic carrying out N-type is also needed while usual grown buffer layer 103''.
In the embodiment of Fig. 4 F-1, in the amplitude of variation of resilient coating 103'' thickness, when the thickness of resilient coating 103'' equals the original thickness of insulating barrier 104, when being also the upper surface flush of its upper surface and strained epilayer 105', the most favourable to formation LDD district 105a, 105b, be readily appreciated that, when resilient coating 103'' thickening to the upper surface of its upper surface higher than strained epilayer 105' time, formed LDD district ion need in resilient coating 103'' through distance or thickness larger, and this needs larger Implantation Energy or concentration support.For the embodiment of Fig. 4 F-2, like this too, the original thickness of insulating barrier 104 is equaled at the thickness of resilient coating 103'', also when namely the upper surface of resilient coating 103'' flushes with the bottom face of side wall 110', to formation, LDD district is the most favourable, even when height less than or equal to the upper surface of strained epilayer 105' of the height of the upper surface of resilient coating 103'', also can prepare LDD district under Implantation Energy or concentration not too exacting terms.These are all preferred versions, as long as but the thickness meeting resilient coating 103'' is equal to or greater than the original thickness of insulating barrier 104 but its upper surface is no more than stack grid structure upper surface, equal acceptable for purposes of the invention, because LDD district inherently option but not essential feature.
Fig. 4 G to Fig. 4 H-1, it is the follow-up flow process based on Fig. 4 F-1, roughly the same with Fig. 2 B, need on the upper surface of resilient coating 103'', form metal silicide 103a, an interlayer dielectric layer 115 of deposition will cover on resilient coating 103'', stack grid structure and side wall 110, thereafter utilize the mask etching interlayer dielectric layer 115 do not illustrated, formed in interlayer dielectric layer 115 and aim at the through hole 108' that resilient coating 103'' is positioned at two parts of strained epilayer 105' both sides respectively.In NMOS unit, resilient coating 103'' and the lamination both soi layer 103 lay respectively at two parts of strained epilayer 105' both sides, using as the drain region of NMOS and source area.Need afterwards in through hole 108', to fill metal material 108'a, as Fig. 4 H-1.The step of Fig. 4 H-2, it is the follow-up flow process of Fig. 4 F-2, be with the difference of Fig. 4 F-1, the bottom face of side wall 110' and the upper surface flush of strained epilayer 105' in Fig. 4 F-1, and the bottom of side wall 110' extends downward the upper surface of its bottom face lower than strained epilayer 105', so now side wall 110' also covers on the sidewall of the part of the low end face above side wall 110' on strained epilayer 105' top along the sidewall of stack grid structure in Fig. 4 F-2.The common ground of Fig. 4 F-2 and Fig. 4 F-1 is that the thickness of resilient coating 103'' all can regulate, the height of resilient coating 103'' upper surface can change between the bottom face of side wall 110' and the upper surface of stack grid structure, but can not exceed the upper surface of stack grid structure.Discussed above, should distance between the upper surface of limit strain epitaxial loayer 105' and the bottom face place plane of side wall 110', large about 10 ran, if select preparation LDD district 105a, 105b, when bottom face a little more than side wall 110' of the upper surface of epitaxial loayer 105', LDD district 105a can be connected on the resilient coating 103'' of epitaxial loayer 105' side, LDD district 105b can be connected on the resilient coating 103'' of epitaxial loayer 105' opposite side, and this is useful to the effective conducting channel that cannot be formed being avoided the device of Fig. 4 H-2.
Foregoing teachings disclosed prepare grid 107, the gate material layers of 107'a can be single layer structure also can be sandwich construction, except typical single level polysilicon, Fig. 5 A ~ 5B also show the stacked gate 207, the 207' that are come by sandwich construction patterning, they can be used as the GeO in the grid 107 of this case, 107'a, figure below stacked gate 207,207'
2be equivalent to grid oxic horizon 106 of the present invention, 106'.Stacked gate 207 comprises an Al
2o
3layer and be positioned at Al
2o
3al layer on layer, stacked gate 207' comprises one by ald ALD(Atomic layer deposition) the standby HfO of legal system
2layer and be positioned at HfO
2the tungsten nitride WN layer prepared by ALD on layer, Fig. 5 A discloses the P type Ge substrate in (100) and (111) crystal orientation, and the substrate of Fig. 5 B comprises the N+ type Si base substrate being positioned at bottom and the Si be positioned on base substrate
1-xge
xlayer (x=0 ~ 0.44) and be positioned at Si
1-xge
xa lax Si on layer
0.56ge
0.44layer, strained ge layer is arranged on Si
0.56ge
0.44on layer.In addition, can find, in the present invention, the combination of any one strained epilayer and substrate is all rendered as inverse-T-shaped structure, and any one drain/source district is all separated by a buried oxide layer 102 and the substrate below it, the probability that unnecessary electronics leaks in wafer substrate reduces, waste electric energy owing to not having electronics seepage, therefore power consumption is less.
Above, by illustrating and accompanying drawing, give the exemplary embodiments of the ad hoc structure of embodiment, foregoing invention proposes existing preferred embodiment, but these contents are not as limitation.For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.
Claims (20)
1. there is a preparation method for the semiconductor device of strained-channel, be disposed with a buried oxide layer and a soi layer in a substrate, it is characterized in that, comprise the following steps:
Forming an insulating barrier covers on soi layer;
Etching insulating layer forms an opening;
Nationality etches soi layer below it, buried oxide layer form the groove structure being arranged in soi layer, buried oxide layer by opening, and exposes substrate in groove structure;
A strained epilayer is formed in the bottom of the gate trench formed by described groove structure and described open butt joint;
A grid oxic horizon is formed on strained epilayer;
The grid on grid oxic horizon is positioned in the top of gate trench formation one.
2. the method for claim 1, is characterized in that, after forming described grid, etches the through hole that described insulating barrier forms the soi layer aiming at gate trench both sides; And
The region being exposed to via bottoms at soi layer upper surface forms metal silicide, and then fill metal material in through hole.
3. method as claimed in claim 2, is characterized in that, before forming metal silicide, the part first utilizing through hole to be arranged in via bottoms at soi layer implants alloy, forms the heavily doped region that a doping content is greater than soi layer doping content.
4. the method for claim 1, is characterized in that, is removed by described insulating barrier, then on the sidewall of the stack grid structure be made up of grid and grid oxic horizon, form side wall, and implement following steps after forming grid:
The region that soi layer upper surface exposes forms metal silicide;
Depositing an interlayer dielectric layer covers above soi layer, stack grid structure and side wall;
Etching interlayer dielectric layer forms the through hole of the soi layer of alignment grooves structure both sides;
Metal material is filled in through hole.
5. method as claimed in claim 4, it is characterized in that, before forming metal silicide, and before or after the step forming side wall, two regional areas of the soi layer respectively near groove structure both sides be arranged in below grid oxic horizon two ends at the upper epidermis of strained epilayer adulterate, and form Liang Ge LDD district respectively.
6. the method for claim 1, is characterized in that, is removed by described insulating barrier, then on the sidewall of the stack grid structure be made up of grid and grid oxic horizon, form side wall, and implement following steps after forming grid:
On soi layer, form a resilient coating, the maximum height controlling its upper surface is no more than the upper surface of stack grid structure, and resilient coating is insulated by side wall and stack grid structure and isolates;
The upper surface of resilient coating forms metal silicide;
Depositing an interlayer dielectric layer covers above resilient coating, stack grid structure and side wall;
Etching interlayer dielectric layer forms the through hole of the resilient coating of aligned stack formula grid structure both sides;
Metal material is filled in through hole.
7. method as claimed in claim 6, it is characterized in that, before forming resilient coating, and before or after the step forming side wall, two regional areas of the soi layer respectively near groove structure both sides be arranged in below grid oxic horizon two ends at the upper epidermis of strained epilayer adulterate, and form Liang Ge LDD district respectively.
8. method as claimed in claim 6, is characterized in that, in the step forming resilient coating, with in-situ doped mode implanting dopants in resilient coating, to improve the doping content of resilient coating.
9. the method for claim 1, it is characterized in that, formed before insulating barrier, in the epitaxial process of soi layer, be implanted into alloy in in-situ doped mode at soi layer, or at soi layer, alloy is implanted into the mode that established soi layer carries out ion implantation.
10. the method for claim 1, is characterized in that, in the step forming groove structure, also implement over etching to described substrate, and etching stops in the substrate to make the bottom of described groove structure extend downward in described substrate.
11. the method for claim 1, is characterized in that, in the step of strained epilayer described in epitaxial growth, the height and position of the upper surface of controlled strain epitaxial loayer, comprising:
The upper surface of controlled strain epitaxial loayer higher than soi layer upper surface height and position but lower than the height and position of insulating barrier upper surface; Or
The upper surface of controlled strain epitaxial loayer and the upper surface flush of soi layer.
12. the method for claim 1, is characterized in that, described substrate be comprise Si substrate substrate or for comprising Si substrate and being arranged on the substrate of Ge or the SiGe epitaxial loayer on substrate, described strained epilayer is Ge or SiGe.
13. 1 kinds of semiconductor device with strained-channel, are disposed with a buried oxide layer and a soi layer in a substrate, it is characterized in that, comprising:
Be arranged on the insulating barrier of one on soi layer with opening;
Be formed in the groove structure in soi layer, buried oxide layer, wherein said groove structure and overlapping described open butt joint above it form a gate trench;
Be filled in the strained epilayer bottom gate trench;
Be formed in the grid oxic horizon on strained epilayer;
Be filled in one of gate trench top and be positioned at grid on grid oxic horizon;
In strained epilayer wherein between the source area that nationality is made up of respectively the soi layer of gate trench both sides and drain region, be formed with a lateral channel district.
14. semiconductor device as claimed in claim 13 with strained-channel, it is characterized in that, described groove structure is to downward-extension until extend in substrate bottom it.
15. semiconductor device as claimed in claim 13 with strained-channel, is characterized in that, are provided with the through hole of the soi layer aiming at gate trench both sides respectively in described insulating barrier; And
The part implantation that described soi layer is arranged in via bottoms has alloy, forms the heavily doped region that a doping content is greater than soi layer doping content;
The region that described soi layer upper surface is positioned at via bottoms is formed with metal silicide, and in through hole, is filled with the metal material of metal silicide in electrical contact.
16. semiconductor device as claimed in claim 13 with strained-channel, it is characterized in that, the upper surface of strained epilayer is higher than the upper surface of described soi layer or the upper surface flush with described soi layer.
17. 1 kinds of semiconductor device with strained-channel, are disposed with a buried oxide layer and a soi layer in a substrate, it is characterized in that, comprising:
Be formed in the groove structure in soi layer, buried oxide layer;
Be filled in the strained epilayer in gate trench;
Be formed in the grid oxic horizon on strained epilayer;
Be arranged on the grid on grid oxic horizon;
Cover the side wall on the sidewall of the stack grid structure be made up of grid and grid oxic horizon;
In strained epilayer wherein between the source area that nationality is made up of respectively the soi layer of groove structure both sides and drain region, be formed with a lateral channel district.
18. semiconductor device as claimed in claim 17 with strained-channel, it is characterized in that, on soi layer, be provided with a resilient coating, the height and position of its upper surface is no more than the upper surface of stack grid structure, and resilient coating is insulated by side wall and stack grid structure and isolates.
19. semiconductor device as claimed in claim 18 with strained-channel, is characterized in that, described soi layer is SiC and doped with the alloy of N-type, and described resilient coating is SiC or Si and doped with N-type dopant.
20. semiconductor device as claimed in claim 17 with strained-channel, it is characterized in that, be arranged in two regional areas of the soi layer respectively near groove structure both sides below grid oxic horizon two ends doped with alloy at the upper epidermis of strained epilayer, form Liang Ge LDD district.
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| CN107546178B (en) * | 2016-06-28 | 2020-06-09 | 西安电子科技大学 | PMOS device based on direct band gap modified Ge channel and preparation method thereof |
| CN114038758A (en) * | 2022-01-07 | 2022-02-11 | 广州粤芯半导体技术有限公司 | Method for forming NMOS (N-channel metal oxide semiconductor) capable of improving hot carrier injection |
| CN114038758B (en) * | 2022-01-07 | 2022-04-15 | 广州粤芯半导体技术有限公司 | Method for forming NMOS (N-channel metal oxide semiconductor) capable of improving hot carrier injection |
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