CN104659170A - Light emitting diode epitaxial wafer and preparation method thereof - Google Patents

Light emitting diode epitaxial wafer and preparation method thereof Download PDF

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Publication number
CN104659170A
CN104659170A CN201510044593.6A CN201510044593A CN104659170A CN 104659170 A CN104659170 A CN 104659170A CN 201510044593 A CN201510044593 A CN 201510044593A CN 104659170 A CN104659170 A CN 104659170A
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layer
current extending
successively
component
growth
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CN104659170B (en
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赵刚
韩杰
胡加辉
魏世祯
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HC Semitek Suzhou Co Ltd
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HC Semitek Suzhou Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

The invention discloses a light emitting diode epitaxial wafer and a preparation method thereof, and belongs to the technical field of semiconductors. The epitaxial wafer comprises a substrate, and a buffering layer, an N-type layer, a stress release layer, a multi-quantum-well layer and a P-type layer which are stacked on the substrate in sequence, further comprises a first current extending layer stacked between the stress release layer and the multi-quantum-well layer, and a second current extending layer stacked between the multi-quantum-well layer and the P-type layer, wherein each of the first current extending layer and the second current extending layer comprises a plurality of AlxGa(1-x)N layers and InyGa(1-y)N layers which grow alternately, wherein x is greater than 0 and smaller than 1, and y is greater than or equal to 0 and smaller than 1; the AlxGa(1-x)N layers and the InyGa(1-y)N layers in the first current extending layer are doped with N types, and the AlxGa(1-x)N layers and the InyGa(1-y)N layers in the second current extending layer are not doped. The light emitting diode epitaxial wafer can prevent a light emitting diode from failing.

Description

A kind of LED epitaxial slice and preparation method thereof
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of LED epitaxial slice and preparation method thereof.
Background technology
LED (Light Emitting Diode, light-emitting diode) is a kind of semiconductor electronic component that can be luminous, has high efficiency, the life-span is long, volume is little, the advantage such as low-power consumption, may be used for indoor and outdoor lighting, screen display, backlight etc.
Epitaxial wafer is the vitals manufacturing light-emitting diode.Existing epitaxial wafer comprises Sapphire Substrate and stacks gradually unadulterated GaN layer, N-type GaN layer, multiple quantum well layer and P type GaN layer on a sapphire substrate.
Realizing in process of the present invention, inventor finds that prior art at least exists following problem:
There is larger lattice mismatch between sapphire and GaN, growing GaN can produce lattice defect on a sapphire substrate, and lattice defect extends along the direction of growth of epitaxial wafer.Electronics and hole are easily gathered in fault location, when electronics and hole accumulation can puncture multiple quantum well layer to a certain extent, cause LED failure.
Summary of the invention
Causing the problem of LED failure in order to solve prior art, embodiments providing a kind of LED epitaxial slice and preparation method thereof.Described technical scheme is as follows:
On the one hand, embodiments provide a kind of LED epitaxial slice, described epitaxial wafer comprises substrate and stacks gradually resilient coating, N-type layer, stress release layer, multiple quantum well layer and P-type layer over the substrate, and described epitaxial wafer also comprises the first current extending be layered between described stress release layer and described multiple quantum well layer and the second current extending be layered between described multiple quantum well layer and described P-type layer; Described first current extending and described second current extending include the Al of some alternating growths xga 1-xn layer and In yga 1-yn layer, 0 < x < 1,0≤y < 1, the Al in described first current extending xga 1-xn layer and In yga 1-yn layer is N-type doping, the Al in described second current extending xga 1-xn layer and In yga 1-yn layer does not all adulterate.
In a kind of possible implementation of the present invention, the Al in described first current extending xga 1-xn layer and In yga 1-ytotal number of plies of N layer is 6-40 layer;
Al in described second current extending xga 1-xn layer and In yga 1-ytotal number of plies of N layer is 6-40 layer.
In the another kind of possible implementation of the present invention, the Al in described first current extending xga 1-xthe Al component of N layer first successively increases along the direction of growth of described epitaxial wafer and successively reduces;
Al in described second current extending xga 1-xthe Al component of N layer first successively increases along the direction of growth of described epitaxial wafer and successively reduces.
In another possible implementation of the present invention, the In in described first current extending yga 1-ythe In component of N layer successively increases along the direction of growth of described epitaxial wafer, and the In in described first current extending yga 1-ythe In component of N layer is not higher than the In component of described multiple quantum well layer;
In in described second current extending yga 1-ythe In component of N layer successively reduces along the direction of growth of described epitaxial wafer, and the In in described second current extending yga 1-ythe In component of N layer is not higher than the In component of described multiple quantum well layer.
In another possible implementation of the present invention, the Al of described first current extending xga 1-xn layer and In yga 1-ythe N-type doping content of N layer all successively increases along the direction of growth of described epitaxial wafer or successively reduces or first successively increase successively to reduce or first successively reduce and successively increases, and the Al of described first current extending xga 1-xn layer and In yga 1-ythe N-type doping content of N layer is lower than the N-type doping content of described N-type layer.
On the other hand, embodiments provide a kind of preparation method of LED epitaxial slice, described preparation method comprises:
Successively in Grown resilient coating, N-type layer, stress release layer, the first current extending, multiple quantum well layer, the second current extending and P-type layer;
Wherein, described first current extending and described second current extending include the Al of some alternating growths xga 1-xn layer and In yga 1-yn layer, 0 < x < 1,0≤y < 1, the Al in described first current extending xga 1-xn layer and In yga 1-yn layer is N-type doping, the Al in described second current extending xga 1-xn layer and In yga 1-yn layer does not all adulterate.
In a kind of possible implementation of the present invention, the Al in described first current extending xga 1-xn layer and In yga 1-ytotal number of plies of N layer is 6-40 layer;
Al in described second current extending xga 1-xn layer and In yga 1-ytotal number of plies of N layer is 6-40 layer.
In the another kind of possible implementation of the present invention, the Al in described first current extending xga 1-xthe Al component of N layer first successively increases along the direction of growth of described epitaxial wafer and successively reduces;
Al in described second current extending xga 1-xthe Al component of N layer first successively increases along the direction of growth of described epitaxial wafer and successively reduces.
In another possible implementation of the present invention, the In in described first current extending yga 1-ythe In component of N layer successively increases along the direction of growth of described epitaxial wafer, and the In in described first current extending yga 1-ythe In component of N layer is not higher than the In component of described multiple quantum well layer;
In in described second current extending yga 1-ythe In component of N layer successively reduces along the direction of growth of described epitaxial wafer, and the In in described second current extending yga 1-ythe In component of N layer is not higher than the In component of described multiple quantum well layer.
In another possible implementation of the present invention, the Al of described first current extending xga 1-xn layer and In yga 1-ythe N-type doping content of N layer all successively increases along the direction of growth of described epitaxial wafer or successively reduces or first successively increase successively to reduce or first successively reduce and successively increases, and the Al of described first current extending xga 1-xn layer and In yga 1-ythe N-type doping content of N layer is lower than the N-type doping content of described N-type layer.
The beneficial effect that the technical scheme that the embodiment of the present invention provides is brought is:
By arranging the first current extending and the second current extending respectively in multiple quantum well layer both sides, the first current extending and the second current extending include the Al of some alternating growths xga 1-xn layer and In yga 1-yn layer, 0 < x < 1,0≤y < 1, due to Al xga 1-xthere is tensile stress in N layer, In yga 1-ythere is compression in N layer, therefore the Al of rational alternating growth xga 1-xn layer and In yga 1-ythe superlattice structure of N layer composition can discharge stress and dislocation is merged, turn to or make dislocation to stop, improve crystal mass, reduce electronics and the gathering of hole at Multiple Quantum Well two ends, improve the antistatic effect (improving 15%) of light-emitting diode and reduce forward voltage, preventing LED failure.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structural representation of a kind of LED epitaxial slice that the embodiment of the present invention one provides;
Fig. 2 a-Fig. 2 e is the conduction band schematic diagram of the Al change of component that the embodiment of the present invention one provides;
Fig. 3 a-Fig. 3 e is the conduction band schematic diagram of the In change of component that the embodiment of the present invention one provides;
Fig. 4 is the flow chart of the preparation method of a kind of LED epitaxial slice that the embodiment of the present invention two provides.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, embodiment of the present invention is described further in detail.
Embodiment one
Embodiments provide a kind of LED epitaxial slice, see Fig. 1, this epitaxial wafer comprises substrate 1 and stacks gradually resilient coating 2, N-type layer 3, stress release layer 4, first current extending 5, multiple quantum well layer 6, second current extending 7 and P-type layer 8 on substrate 1.
In the present embodiment, the first current extending 5 comprises the Al of some alternating growths xga 1-xn layer 51 and In yga 1-yn layer 52, and the Al in the first current extending 5 xga 1-xn layer 51 and In yga 1-yn layer 52 is N-type doping.Second current extending 7 comprises the Al of some alternating growths xga 1-xn layer 71 and In yga 1-yn layer 72, and the Al in the second current extending 7 xga 1-xn layer 71 and In yga 1-yn layer 72 does not all adulterate.Wherein, 0 < x < 1,0≤y < 1.
In a kind of implementation of the present embodiment, the Al in the first current extending 5 xga 1-xn layer 51 and In yga 1-ytotal number of plies of N layer 52, with the Al in the second current extending 7 xga 1-xn layer 71 and In yga 1-ytotal number of plies of N layer 72 can be identical or different.
Alternatively, the Al in the first current extending 5 xga 1-xn layer 51 and In yga 1-ytotal number of plies of N layer 52 can be 6-40 layer.
Preferably, the Al in the first current extending 5 xga 1-xn layer 51 and In yga 1-ytotal number of plies of N layer 52 can be 10-30 layer.
Alternatively, the Al in the second current extending 7 xga 1-xn layer 71 and In yga 1-ytotal number of plies of N layer 72 can be 6-40 layer.
Preferably, the Al in the second current extending 7 xga 1-xn layer 71 and In yga 1-ytotal number of plies of N layer 72 can be 10-30 layer.
In the another kind of implementation of the present embodiment, the Al in the first current extending 5 xga 1-xthe thickness of N layer 51, with the Al in the second current extending 7 xga 1-xthe thickness of N layer 71 can be identical or different; In in first current extending 5 yga 1-ythe thickness of N layer 52, with the In in the second current extending 7 yga 1-ythe thickness of N layer 72 can be identical or different.
Alternatively, the Al in the first current extending 5 xga 1-xthe thickness of N layer 51 can be 2-15nm, the In in the first current extending 5 yga 1-ythe thickness of N layer 52 can be 2-15nm.
Preferably, the Al in the first current extending 5 xga 1-xthe thickness of N layer 51 can be 10-15nm, the In in the first current extending 5 yga 1-ythe thickness of N layer 52 can be 10-15nm.
Alternatively, the Al in the second current extending 7 xga 1-xthe thickness of N layer 71 can be 2-15nm, the In in the second current extending 7 yga 1-ythe thickness of N layer 72 can be 2-15nm.
Preferably, the Al in the second current extending 7 xga 1-xthe thickness of N layer 71 can be 10-15nm, the In in the second current extending 7 yga 1-ythe thickness of N layer 72 can be 10-15nm.
In specific implementation, because growth pressure affects Al xga 1-xn layer, In yga 1-ythe speed of growth of N layer and thickness, therefore can use the mode control Al changing growth pressure xga 1-xn layer, In yga 1-ythe thickness of N layer.
It should be noted that, (comprise total number of plies, the Al of sublayer in total number of plies of sublayer in the first current extending 5, the second current extending 7 in parameter xga 1-xthe thickness of N layer 51, In yga 1-ythe thickness of N layer 52, Al xga 1-xthe thickness of N layer 71, In yga 1-ythe thickness of N layer 72) design under the condition of optimum, the AlGaN/InGaN superlattice structure of the first current extending and the second current extending can make the stress of material and compression cancel out each other, and alleviate the internal stress of material, growth quality is good.Such as, in the first current extending 5, in total number of plies of sublayer and the second current extending 7, total number of plies of sublayer is 10 layers, Al xga 1-xthe thickness of N layer 51, In yga 1-ythe thickness of N layer 52, Al xga 1-xthe thickness of N layer 71, In yga 1-ythe thickness of N layer 72 is 10nm.If the numerical value of parameter exceedes suitable scope, then the internal stress of material is comparatively large, and growth quality is deteriorated, and affects the expansion effect of electric current.
In another implementation of the present embodiment, the growth temperature of the first current extending 5, can be identical or different with the growth temperature 7 of the second current extending 7.
Alternatively, the growth temperature of the first current extending 5 can be 800-1200 DEG C.If the growth temperature of the first current extending 5 lower than 800 DEG C, is then unfavorable for Al xga 1-xthe growth (the optimal growth temperature of AlN is greater than 1200 DEG C) of N layer 51; If the growth temperature of the first current extending 5 is higher than 1200 DEG C, then can bursting stress releasing layer 4, make the In segregation in stress release layer 4, and there is thermal mismatching with the low-temperature epitaxy of multiple quantum well layer 6, thermal stress increases, and causes multiple quantum well layer 6 second-rate.
Preferably, the growth temperature of the first current extending 5 can be 800-950 DEG C.
Alternatively, the growth temperature of the second current extending 7 can be 800-1200 DEG C.If the growth temperature of the second current extending 7 lower than 800 DEG C, is then unfavorable for Al xga 1-xthe growth (the optimal growth temperature of AlN is greater than 1200 DEG C) of N layer 71; If the growth temperature of the second current extending 7 higher than 1200 DEG C, then can destroy multiple quantum well layer 6, make the In segregation in multiple quantum well layer 6.
Preferably, the growth temperature of the second current extending 7 can be 800-950 DEG C.
In another implementation of the present embodiment, the growth pressure of the first current extending 5, can be identical or different with the growth pressure of the second current extending 7.
Alternatively, the growth pressure of the first current extending 5 can be 50-600torr.Because the side reaction of Al increases with the rising of chamber pressure, if the growth pressure of the first current extending 5 is higher than 600torr, then the epitaxial wafer impurity grown is more.
Preferably, the growth pressure of the first current extending 5 can be 50-200torr.The growth pressure of the first current extending 5, lower than 200torr, is conducive to Al xga 1-xthe growth of N layer 51.
Alternatively, the growth pressure of the second current extending 7 can be 50-600torr.Because the side reaction of Al increases with the rising of chamber pressure, if the growth pressure of the second current extending 7 is higher than 600torr, then the epitaxial wafer impurity grown is more.
Preferably, the growth pressure of the second current extending 7 can be 50-200torr.The growth pressure of the second current extending 7, lower than 200torr, is conducive to Al xga 1-xthe growth of N layer 71.
In another implementation of the present embodiment, the Al in the first current extending 5 xga 1-xthe Al component of N layer 51, with the Al in the second current extending 7 xga 1-xthe Al component of N layer 71 can be identical or different.
Wherein, Al component is that Al is at Al xga 1-xn layer 51 or Al xga 1-xmass content in N layer 71.
Alternatively, the Al in the first current extending 5 xga 1-xthe Al component of N layer 51 can be 2%-35%.
Preferably, the Al in the first current extending 5 xga 1-xthe Al component of N layer 51 can be 5%-20%.If the Al in the first current extending 5 xga 1-xthe Al component of N layer 51 is lower than 5%, then the blocking effect of the first current extending 5 pairs of defects reduces, and reduces, current expansion limited use to the diffusion of assembling electronics; If the Al in the first current extending 5 xga 1-xthe Al component of N layer 51 is higher than 20%, then most of electronics is all blocked by the first current extending 5, and the electronics injecting multiple quantum well layer 6 is less, reduces the luminous efficiency of light-emitting diode.
Alternatively, the Al in the first current extending 5 xga 1-xthe Al component of N layer 51 can remain unchanged (as shown in Figure 2 a) along the direction of growth of epitaxial wafer or successively increase (as shown in Figure 2 b) or successively reduce (as shown in Figure 2 c) or first successively increase successively to reduce (as shown in Figure 2 d) again or first successively reduce successively increases (as shown in Figure 2 e) again.
Preferably, the Al in the first current extending 5 xga 1-xthe Al component of N layer 51 first successively can increase along the direction of growth of epitaxial wafer and successively reduce.Al in first current extending 5 xga 1-xthe Al component of N layer 51 first increases gradually from 0 of stress release layer 4, then reduces to 0 of multiple quantum well layer 6 gradually, reduces the lattice mismatch between the GaN layer in AlGaN layer and stress release layer 4, multiple quantum well layer 6, improves crystal mass.
Alternatively, the Al in the second current extending 7 xga 1-xthe Al component of N layer 71 can be 2%-35%.
Preferably, the Al in the second current extending 7 xga 1-xthe Al component of N layer 71 can be 5%-20%.
Alternatively, the Al in the second current extending 7 xga 1-xthe Al component of N layer 71 can remain unchanged along the direction of growth of epitaxial wafer or successively increase or successively reduce or first successively increase successively to reduce or first successively reduce and successively increase.
Preferably, the Al in the second current extending 7 xga 1-xthe Al component of N layer 71 first successively can increase along the direction of growth of epitaxial wafer and successively reduce.Al in second current extending 7 xga 1-xthe Al component of N layer 71 first increases gradually from 0 of Multiple Quantum Well 6, then reduces to 0 of P-type layer 8 gradually, reduces the lattice mismatch between the GaN layer in AlGaN layer and multiple quantum well layer 6, P-type layer 8, improves crystal mass.
In another implementation of the present embodiment, the In in the first current extending 5 yga 1-ythe In component of N layer 52, with the In in the second current extending 7 yga 1-ythe In component of N layer 52 can be identical or different.
Wherein, In component is that In is at In yga 1-yn layer 52 or In yga 1-ymass content in N layer 52.
Alternatively, the In in the first current extending 5 yga 1-ythe In component of N layer 52 can be 0-30%.
Preferably, the In in the first current extending 5 yga 1-ythe In component of N layer 52 can be 0-20%.
Alternatively, the In in the first current extending 5 yga 1-ythe In component of N layer 52 can remain unchanged (as shown in Figure 3 a) along the direction of growth of epitaxial wafer or successively increase (as shown in Figure 3 b) or successively reduce (as shown in Figure 3 c) or first successively increase successively to reduce (as shown in Figure 3 d) again or first successively reduce successively increases (as shown in Figure 3 e) again, and the In in described first current extending 5 yga 1-ythe In component of N layer 52 is not higher than the In component of multiple quantum well layer 6.
Preferably, the In in the first current extending 5 yga 1-ythe In component of N layer 52 successively can increase along the direction of growth of epitaxial wafer.
Preferably, the In in the first current extending 5 yga 1-ythe absolute value of the difference of the growth temperature of the InGaN layer in the growth temperature of N layer 52 and multiple quantum well layer 6 successively can reduce along the direction of growth of epitaxial wafer.
Alternatively, the In in the second current extending 7 yga 1-ythe In component of N layer 72 can be 0-30%.
Preferably, the In in the second current extending 7 yga 1-ythe In component of N layer 72 can be 0-20%.
Alternatively, the In in the second current extending 7 yga 1-ythe In component of N layer 72 can remain unchanged along the direction of growth of epitaxial wafer or successively increase or successively reduce or first successively increase successively to reduce or first successively reduce and successively increase, and the In in the second current extending 7 yga 1-ythe In component of N layer 72 is not higher than the In component of multiple quantum well layer 6.
Preferably, the In in the second current extending 7 yga 1-ythe In component of N layer 72 successively can reduce along the direction of growth of epitaxial wafer.
Preferably, the In in the second current extending 7 yga 1-ythe absolute value of the difference of the growth temperature of the InGaN layer in the growth temperature of N layer 72 and multiple quantum well layer 6 successively can increase along the direction of growth of epitaxial wafer.
Understandably, the In in the first current extending 5 yga 1-ythe In component of N layer 52 successively increases along the direction of growth of epitaxial wafer, the In in the second current extending 7 yga 1-ythe In component of N layer 72 successively reduces along the direction of growth of epitaxial wafer, in epitaxial wafer, In component first can be increased to the size of the In component of the InGaN layer multiple quantum well layer 6 gradually from 0 of stress release layer 4,0 of P-type layer 8 is reduced to gradually again from the size of the In component of the InGaN layer multiple quantum well layer 6, that is, In component gradually changes, thus the lattice mismatch effectively reduced between InGaN layer and GaN layer, improve crystal mass.And, the closer to the In of multiple quantum well layer 6 yga 1-yn layer (In yga 1-yn layer 52 or In yga 1-yn layer 72) In component higher, In yga 1-yn layer and Al xga 1-xpotential well between N layer is darker, is more conducive to current expansion.
In in first current extending 5 yga 1-ythe absolute value of the difference of the growth temperature of the InGaN layer in the growth temperature of N layer 52 and multiple quantum well layer 6 successively reduces along the direction of growth of epitaxial wafer, the In in the second current extending 7 yga 1-ythe absolute value of the difference of the growth temperature of the InGaN layer in the growth temperature of N layer 72 and multiple quantum well layer 6 successively increases along the direction of growth of epitaxial wafer, in epitaxial wafer, the growth temperature of InGaN layer first tapers to the growth temperature of multiple quantum well layer 6 from the growth temperature of stress release layer 4, the growth temperature of P-type layer 8 is tapered to again from the growth temperature of multiple quantum well layer 6, effectively reduce the thermal mismatching in epitaxial wafer growth course, improve crystal mass.
In another implementation of the present embodiment, the Al in the first current extending 5 xga 1-xn layer 51 and In yga 1-ythe N-type of N layer 52 is doped to Si doping.
Alternatively, the Al in the first current extending 5 xga 1-xn layer 51 and In yga 1-ythe N-type doping content of N layer 52 is 1*10 17-1*10 19cm -3.If the Al in the first current extending 5 xga 1-xn layer 51 or In yga 1-ythe N-type doping content of N layer 52 is higher than 1*10 19cm -3, reverse leakage increases; If the Al in the first current extending 5 xga 1-xn layer 51 or In yga 1-ythe N-type doping content of N layer 52 is lower than 1*10 17, then cause resistance to increase, forward voltage increases.
Preferably, the Al in the first current extending 5 xga 1-xn layer 51 and In yga 1-ythe N-type doping content of N layer 52 is 1*10 17-5*10 18cm -3.
Alternatively, the Al in the first current extending 5 xga 1-xn layer 51 and In yga 1-ythe N-type doping content of N layer 52 all successively increases along the direction of growth of epitaxial wafer or successively reduces or first successively increase successively to reduce or first successively reduce and successively increases, and the Al in the first current extending 5 xga 1-xn layer 51 and In yga 1-ythe N-type doping content of N layer 52 is lower than the N-type doping content of N-type layer 3.If the Al in the first current extending 5 xga 1-xn layer 51 and In yga 1-ythe N-type doping content of N layer 52 is high low-doped (successively increasing or successively reduce or first successively increase successively to reduce or first successively reduce successively increases again), then form parasitic capacitance in epitaxial wafer, the antistatic effect of epitaxial wafer can be improved.
Particularly, substrate 1 can be Sapphire Substrate.
Particularly, resilient coating 2 can comprise low temperature buffer layer, 3D layer, amalgamation layer, high temperature buffer layer.Low temperature buffer layer, three-dimensional 3D layer, amalgamation layer, high temperature buffer layer are GaN layer, the growth temperature of low temperature buffer layer is 550 DEG C, the growth temperature of 3D layer is 1030-1040 DEG C, and the growth temperature of amalgamation layer is 1100 DEG C, and the growth temperature of high temperature buffer layer is 1100 DEG C.
Particularly, N-type layer 3 can comprise high temperature N-type GaN layer and low temperature N-type GaN layer, and the growth temperature of high temperature N-type GaN layer is 1000-1100 DEG C, and the growth temperature of low temperature N-type GaN layer is 800-850 DEG C.Due to the growth temperature of high temperature N-type GaN layer higher (1100 DEG C can be reached), the growth temperature of multiple quantum well layer 6 is lower (as 750 DEG C), the low temperature N-type GaN layer that the long growth temperature of Mr. is lower in high temperature N-type GaN layer, regrowth multiple quantum well layer 6, the effect of buffering and transition can be played, avoid the growth temperature difference due to adjacent two layers to produce larger thermal stress comparatively greatly.
More specifically, the N-type doping content of high temperature N-type GaN layer is higher than the N-type doping content of low temperature N-type GaN layer.
Particularly, stress release layer 4 can comprise InGaN layer and the GaN layer of some alternating growths, and the In component of stress release layer 4 is less than the In component of multiple quantum well layer 6.
More specifically, the growth temperature of stress release layer 4 is 800-850 DEG C.
Particularly, multiple quantum well layer 6 can comprise InGaN layer and the GaN layer of some alternating growths.
More specifically, the growth temperature of multiple quantum well layer 6 is 700-750 DEG C.
Particularly, P-type layer 8 can comprise low temperature P-type layer, P-type electron barrier layer, high temperature P-type layer, P type contact layer.Low temperature P-type layer, high temperature P-type layer, P type contact layer are GaN layer, and P-type electron barrier layer is AlGaN layer.The growth temperature of low temperature P-type layer is 750-770 DEG C, and the growth temperature of P-type electron barrier layer is 950 DEG C, and the growth temperature of high temperature P-type layer is 950 DEG C, and the growth temperature of P type contact layer is 950 DEG C.
More specifically, the P type doping content of low temperature P-type layer, high temperature P-type layer, P type contact layer is higher, and the P type doping content of P-type electron barrier layer is lower.The thickness of P type contact layer is less than the thickness of high temperature P-type layer.
The embodiment of the present invention is by arranging the first current extending and the second current extending respectively in multiple quantum well layer both sides, and the first current extending and the second current extending include the Al of some alternating growths xga 1-xn layer and In yga 1-yn layer, 0 < x < 1,0≤y < 1, due to Al xga 1-xthere is tensile stress in N layer, In yga 1-ythere is compression in N layer, therefore the Al of rational alternating growth xga 1-xn layer and In yga 1-ythe superlattice structure of N layer composition can discharge stress and dislocation is merged, turn to or make dislocation to stop, improve crystal mass, reduce electronics and the gathering of hole at quantum well two ends, improve the antistatic effect (improving 15%) of light-emitting diode and reduce forward voltage, preventing LED failure.And, first current extending can stop portions electron injection multiple quantum well layer, slow down the speed of electron injection Multiple Quantum Well, the overflow of the further block electrons of the second current extending one side energy, allow to better expand hole on the other hand, improve hole injection efficiency, first current extending and the second current extending acting in conjunction, make electronics and hole at the abundant recombination luminescence of multiple quantum well layer, improve the internal quantum efficiency of light-emitting diode, and then improve the luminous efficiency (improving 10%) of light-emitting diode.
Embodiment two
Embodiments provide a kind of preparation method of LED epitaxial slice, see Fig. 4, this preparation method comprises:
Step 201: at Grown resilient coating.
In actual applications, adopt metallo-organic compound chemical gaseous phase deposition (Metal-Organic ChemicalVapor Deposition, be called for short MOCVD) method, using trimethyl (or triethyl group) gallium as gallium source, high-purity N H3 is as nitrogenous source, and trimethyl indium is as indium source, and trimethyl aluminium is as aluminium source, silane is selected in N-type doping, and two luxuriant magnesium are selected in the doping of P type.
Particularly, substrate can be Sapphire Substrate.
Particularly, resilient coating can comprise low temperature buffer layer, three-dimensional 3D layer, amalgamation layer, high temperature buffer layer.Low temperature buffer layer, three-dimensional 3D layer, amalgamation layer, high temperature buffer layer are GaN layer, the growth temperature of low temperature buffer layer is 550 DEG C, the growth temperature of 3D layer is 1030-1040 DEG C, and the growth temperature of amalgamation layer is 1100 DEG C, and the growth temperature of high temperature buffer layer is 1100 DEG C.
Step 202: grow N-type layer on the buffer layer.
Particularly, N-type layer can comprise high temperature N-type GaN layer and low temperature N-type GaN layer, and the growth temperature of high temperature N-type GaN layer is 1000-1100 DEG C, and the growth temperature of low temperature N-type GaN layer is 800-850 DEG C.Due to the growth temperature of high temperature N-type GaN layer higher (1100 DEG C can be reached), the growth temperature of multiple quantum well layer is lower (as 750 DEG C), the low temperature N-type GaN layer that the long growth temperature of Mr. is lower in high temperature N-type GaN layer, regrowth multiple quantum well layer, the effect of buffering and transition can be played, avoid the growth temperature difference due to adjacent two layers to cause thermal mismatching comparatively greatly.
More specifically, the N-type doping content of high temperature N-type GaN layer is higher than the N-type doping content of low temperature N-type GaN layer.
Step 203: growth stress releasing layer in N-type.
Particularly, stress release layer can comprise InGaN layer and the GaN layer of some alternating growths, and the In component of stress release layer is less than the In component of multiple quantum well layer.
More specifically, the growth temperature of stress release layer is 800-850 DEG C.
Step 204: grow the first current extending on stress release layer.
In the present embodiment, the first current extending comprises the Al of some alternating growths xga 1-xn layer and In yga 1-yn layer, and the Al in the first current extending xga 1-xn layer and In yga 1-yn layer is N-type doping.Wherein, 0 < x < 1,0≤y < 1.
Alternatively, the Al in the first current extending xga 1-xn layer and In yga 1-ytotal number of plies of N layer can be 6-40 layer.
Preferably, the Al in the first current extending xga 1-xn layer and In yga 1-ytotal number of plies of N layer can be 10-30 layer.
Alternatively, the Al in the first current extending xga 1-xthe thickness of N layer can be 2-15nm, the In in the first current extending yga 1-ythe thickness of N layer can be 2-15nm.
Preferably, the Al in the first current extending xga 1-xthe thickness of N layer can be 10-15nm, the In in the first current extending yga 1-ythe thickness of N layer can be 10-15nm.
Alternatively, the growth temperature of the first current extending can be 800-1200 DEG C.
Preferably, the growth temperature of the first current extending can be 800-950 DEG C.
Alternatively, the growth pressure of the first current extending can be 50-600torr.
Preferably, the growth pressure of the first current extending can be 50-200torr.
Alternatively, the Al in the first current extending xga 1-xthe Al component of N layer can be 2%-35%.
Preferably, the Al in the first current extending xga 1-xthe Al component of N layer can be 5%-20%.
Alternatively, the Al in the first current extending xga 1-xthe Al component of N layer can remain unchanged along the direction of growth of epitaxial wafer or successively increase or successively reduce or first successively increase successively to reduce or first successively reduce and successively increase.
Preferably, the Al in the first current extending xga 1-xthe Al component of N layer first successively can increase along the direction of growth of epitaxial wafer and successively reduce.
Alternatively, the In in the first current extending yga 1-ythe In component of N layer can be 0-30%.
Preferably, the In in the first current extending yga 1-ythe In component of N layer can be 0-20%.
Alternatively, the In in the first current extending yga 1-ythe In component of N layer can remain unchanged along the direction of growth of epitaxial wafer or successively increase or successively reduce or first successively increase successively to reduce or first successively reduce and successively increase, and the In in described first current extending yga 1-ythe In component of N layer is not higher than the In component of multiple quantum well layer.
Preferably, the In in the first current extending yga 1-ythe In component of N layer successively can increase along the direction of growth of epitaxial wafer.
Preferably, the In in the first current extending yga 1-ythe absolute value of the difference of the growth temperature of the InGaN layer in the growth temperature of N layer and multiple quantum well layer successively can reduce along the direction of growth of epitaxial wafer.
Alternatively, the Al in the first current extending xga 1-xn layer and In yga 1-ythe N-type doping content of N layer is 1*10 17-1*10 19cm -3.
Preferably, the Al in the first current extending xga 1-xn layer and In yga 1-ythe N-type doping content of N layer is 1*10 17-5*10 18cm -3.
Alternatively, the Al in the first current extending xga 1-xn layer and In yga 1-ythe N-type doping content of N layer all successively increases along the direction of growth of epitaxial wafer or successively reduces or first successively increase successively to reduce or first successively reduce and successively increases, and the Al in the first current extending xga 1-xn layer and In yga 1-ythe N-type doping content of N layer is lower than the N-type doping content of N-type layer.
Step 205: grow multiple quantum well layer on the first current extending.
Particularly, multiple quantum well layer can comprise InGaN layer and the GaN layer of some alternating growths.
More specifically, the growth temperature of multiple quantum well layer is 700-750 DEG C.
Step 206: grow the second current extending on multiple quantum well layer.
In the present embodiment, the second current extending comprises the Al of some alternating growths xga 1-xn layer and In yga 1-yn layer, and the Al in the second current extending xga 1-xn layer and In yga 1-yn layer does not all adulterate.Wherein, 0 < x < 1,0≤y < 1.
Alternatively, the Al in the second current extending xga 1-xn layer and In yga 1-ytotal number of plies of N layer can be 6-40 layer.
Preferably, the Al in the second current extending xga 1-xn layer and In yga 1-ytotal number of plies of N layer can be 10-30 layer.
Alternatively, the Al in the second current extending xga 1-xthe thickness of N layer can be 2-15nm, the In in the second current extending yga 1-ythe thickness of N layer can be 2-15nm.
Preferably, the Al in the second current extending xga 1-xthe thickness of N layer can be 10-15nm, the In in the second current extending yga 1-ythe thickness of N layer can be 10-15nm.
Alternatively, the growth temperature of the second current extending can be 800-1200 DEG C.
Preferably, the growth temperature of the second current extending can be 800-950 DEG C.
Alternatively, the growth pressure of the second current extending can be 50-600torr.
Preferably, the growth pressure of the second current extending can be 50-200torr.
Alternatively, the Al in the second current extending xga 1-xthe Al component of N layer can be 2%-35%.
Preferably, the Al in the second current extending xga 1-xthe Al component of N layer can be 5%-20%.
Alternatively, the Al in the second current extending xga 1-xthe Al component of N layer can remain unchanged along the direction of growth of epitaxial wafer or successively increase or successively reduce or first successively increase successively to reduce or first successively reduce and successively increase.
Preferably, the Al in the second current extending xga 1-xthe Al component of N layer first successively can increase along the direction of growth of epitaxial wafer and successively reduce.
Alternatively, the In in the second current extending yga 1-ythe In component of N layer can be 0-30%.
Preferably, the In in the second current extending yga 1-ythe In component of N layer can be 0-20%.
Alternatively, the In in the second current extending yga 1-ythe In component of N layer can remain unchanged along the direction of growth of epitaxial wafer or successively increase or successively reduce or first successively increase successively to reduce or first successively reduce and successively increase, and the In in the second current extending yga 1-ythe In component of N layer is not higher than the In component of multiple quantum well layer.
Preferably, the In in the second current extending yga 1-ythe In component of N layer successively can reduce along the direction of growth of epitaxial wafer.
Preferably, the In in the second current extending yga 1-ythe absolute value of the difference of the growth temperature of the InGaN layer in the growth temperature of N layer and multiple quantum well layer successively can increase along the direction of growth of epitaxial wafer.
Step 207: growing P-type layer on the second current extending.
Particularly, P-type layer can comprise low temperature P-type layer, P-type electron barrier layer, high temperature P-type layer, P type contact layer.Low temperature P-type layer, high temperature P-type layer, P type contact layer are GaN layer, and P-type electron barrier layer is AlGaN layer.The growth temperature of low temperature P-type layer is 750-770 DEG C, and the growth temperature of P-type electron barrier layer is 950 DEG C, and the growth temperature of high temperature P-type layer is 950 DEG C, and the growth temperature of P type contact layer is 950 DEG C.
More specifically, the P type doping content of low temperature P-type layer, high temperature P-type layer, P type contact layer is higher, and the P type doping content of P-type electron barrier layer is lower.The thickness of P type contact layer is less than the thickness of high temperature P-type layer.
The embodiment of the present invention is by arranging the first current extending and the second current extending respectively in multiple quantum well layer both sides, and the first current extending and the second current extending include the Al of some alternating growths xga 1-xn layer and In yga 1-yn layer, 0 < x < 1,0≤y < 1, due to Al xga 1-xthere is tensile stress in N layer, In yga 1-ythere is compression in N layer, therefore the Al of rational alternating growth xga 1-xn layer and In yga 1-ythe superlattice structure of N layer composition can discharge stress and dislocation is merged, turn to or make dislocation to stop, improve crystal mass, reduce electronics and the gathering of hole at quantum well two ends, improve the antistatic effect (improving 15%) of light-emitting diode and reduce forward voltage, preventing LED failure.And, first current extending can stop portions electron injection multiple quantum well layer, slow down the speed of electron injection Multiple Quantum Well, the overflow of the further block electrons of the second current extending one side energy, allow to better expand hole on the other hand, improve hole injection efficiency, first current extending and the second current extending acting in conjunction, make electronics and hole at the abundant recombination luminescence of multiple quantum well layer, improve the internal quantum efficiency of light-emitting diode, and then improve the luminous efficiency (improving 10%) of light-emitting diode.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (10)

1. a LED epitaxial slice, described epitaxial wafer comprises substrate and stacks gradually resilient coating, N-type layer, stress release layer, multiple quantum well layer and P-type layer over the substrate, it is characterized in that, described epitaxial wafer also comprises the first current extending be layered between described stress release layer and described multiple quantum well layer and the second current extending be layered between described multiple quantum well layer and described P-type layer; Described first current extending and described second current extending include the Al of some alternating growths xga 1-xn layer and In yga 1-yn layer, 0 < x < 1,0≤y < 1, the Al in described first current extending xga 1-xn layer and In yga 1-yn layer is N-type doping, the Al in described second current extending xga 1-xn layer and In yga 1-yn layer does not all adulterate.
2. epitaxial wafer according to claim 1, is characterized in that, the Al in described first current extending xga 1-xn layer and In yga 1-ytotal number of plies of N layer is 6-40 layer;
Al in described second current extending xga 1-xn layer and In yga 1-ytotal number of plies of N layer is 6-40 layer.
3. epitaxial wafer according to claim 1 and 2, is characterized in that, the Al in described first current extending xga 1-xthe Al component of N layer first successively increases along the direction of growth of described epitaxial wafer and successively reduces;
Al in described second current extending xga 1-xthe Al component of N layer first successively increases along the direction of growth of described epitaxial wafer and successively reduces.
4. epitaxial wafer according to claim 1 and 2, is characterized in that, the In in described first current extending yga 1-ythe In component of N layer successively increases along the direction of growth of described epitaxial wafer, and the In in described first current extending yga 1-ythe In component of N layer is not higher than the In component of described multiple quantum well layer;
In in described second current extending yga 1-ythe In component of N layer successively reduces along the direction of growth of described epitaxial wafer, and the In in described second current extending yga 1-ythe In component of N layer is not higher than the In component of described multiple quantum well layer.
5. epitaxial wafer according to claim 1 and 2, is characterized in that, the Al of described first current extending xga 1-xn layer and In yga 1-ythe N-type doping content of N layer all successively increases along the direction of growth of described epitaxial wafer or successively reduces or first successively increase successively to reduce or first successively reduce and successively increases, and the Al of described first current extending xga 1-xn layer and In yga 1-ythe N-type doping content of N layer is lower than the N-type doping content of described N-type layer.
6. a preparation method for LED epitaxial slice, is characterized in that, described preparation method comprises:
Successively in Grown resilient coating, N-type layer, stress release layer, the first current extending, multiple quantum well layer, the second current extending and P-type layer;
Wherein, described first current extending and described second current extending include the Al of some alternating growths xga 1-xn layer and In yga 1-yn layer, 0 < x < 1,0≤y < 1, the Al in described first current extending xga 1-xn layer and In yga 1-yn layer is N-type doping, the Al in described second current extending xga 1-xn layer and In yga 1-yn layer does not all adulterate.
7. preparation method according to claim 6, is characterized in that, the Al in described first current extending xga 1-xn layer and In yga 1-ytotal number of plies of N layer is 6-40 layer;
Al in described second current extending xga 1-xn layer and In yga 1-ytotal number of plies of N layer is 6-40 layer.
8. the preparation method according to claim 6 or 7, is characterized in that, the Al in described first current extending xga 1-xthe Al component of N layer first successively increases along the direction of growth of described epitaxial wafer and successively reduces;
Al in described second current extending xga 1-xthe Al component of N layer first successively increases along the direction of growth of described epitaxial wafer and successively reduces.
9. the preparation method according to claim 6 or 7, is characterized in that, the In in described first current extending yga 1-ythe In component of N layer successively increases along the direction of growth of described epitaxial wafer, and the In in described first current extending yga 1-ythe In component of N layer is not higher than the In component of described multiple quantum well layer;
In in described second current extending yga 1-ythe In component of N layer successively reduces along the direction of growth of described epitaxial wafer, and the In in described second current extending yga 1-ythe In component of N layer is not higher than the In component of described multiple quantum well layer.
10. the preparation method according to claim 6 or 7, is characterized in that, the Al of described first current extending xga 1-xn layer and In yga 1-ythe N-type doping content of N layer all successively increases along the direction of growth of described epitaxial wafer or successively reduces or first successively increase successively to reduce or first successively reduce and successively increases, and the Al of described first current extending xga 1-xn layer and In yga 1-ythe N-type doping content of N layer is lower than the N-type doping content of described N-type layer.
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