CN104658989A - 形成封装件衬底的机制 - Google Patents

形成封装件衬底的机制 Download PDF

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Publication number
CN104658989A
CN104658989A CN201410436288.7A CN201410436288A CN104658989A CN 104658989 A CN104658989 A CN 104658989A CN 201410436288 A CN201410436288 A CN 201410436288A CN 104658989 A CN104658989 A CN 104658989A
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China
Prior art keywords
layer
semiconductor element
moulding compound
redistribution layer
package structure
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CN201410436288.7A
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CN104658989B (zh
Inventor
林俊成
蔡柏豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明根据一些实施例提供了一种封装件结构和用于形成封装件结构的方法。该封装件结构包括半导体管芯和部分或全部密封半导体管芯的模塑料。该封装件结构还包括位于模塑料中的贯通封装过孔。该封装件结构还包括位于贯通封装过孔和模塑料之间的界面层。该界面层包括绝缘材料且与模塑料直接接触。

Description

形成封装件衬底的机制
技术领域
本发明涉及半导体领域，更具体地，涉及形成封装件衬底的机制。
背景技术
半导体器件用于各种电子产品中，诸如个人电脑、手机、数码相机或其他电子设备。通过在半导体衬底上方依次沉积绝缘层或介电层、导电层和半导体层，然后使用光刻和蚀刻工艺以在半导体衬底上形成电路组件和元件，从而制造半导体器件。
半导体工业通过不断地减小最小部件的尺寸不断地提高各种电子部件(例如，晶体管、二极管、电阻器、电容器等)的集成密度，以允许更多的组件能够集成到给定的区域内。在一些产品中，这些较小的电子部件还需要比过去的封装件使用更少面积的较小的封装件。
诸如堆叠封装(PoP)的新的封装技术已经开始发展，其中，具有器件管芯的顶部封装件接合至具有另一器件管芯的底部封装件。通过采用这种新的封装技术，将各种具有不同或相同功能的封装件集成到一起。这些用于半导体器件的相对新型的封装技术在制造上面临着挑战。
发明内容
为解决上述问题，提供了一种封装件结构，包括：半导体管芯；模塑料，至少部分地密封半导体管芯；贯通封装通孔，位于模塑料中；以及界面层，位于贯通封装通孔和模塑料之间，其中，界面层包括绝缘材料且与模塑料直接接触。
其中，界面层包括聚苯并恶唑(PBO)、聚酰亚胺(PI)或它们的组合。
该封装件结构进一步包括位于模塑料和半导体管芯的背侧上方的重分布层。
其中，重分布层电连接到贯通封装过孔。
该封装件结构进一步包括晶种层，其中，重分布层位于晶种层和贯通封装过孔之间，且晶种层与重分布层的厚度比率在约0.8％到约30％的范围内。
其中，界面层包括位于半导体管芯的背侧和重分布层之间的平坦部分，且平坦部分基本平行于半导体管芯的背侧。
该封装件结构进一步包括第二重分布层，其中，半导体管芯位于重分布层和第二重分布层之间，且第二重分布层电连接到半导体管芯的导电焊盘。
该封装件结构进一步包括位于第二重分布层上方的至少一个连接件。
该封装件结构进一步包括位于模塑料和半导体管芯的背侧上方的晶种层和重分布层，其中，晶种层直接接触贯通封装过孔。
该封装件结构进一步包括位于半导体管芯上方的第二半导体管芯，且第二半导体管芯电连接至贯通封装过孔。
该封装件结构进一步包括堆叠在半导体管芯和模塑料上方的管芯封装件。
此外，还提供了一种封装件结构，包括：半导体管芯；模塑料，至少部分地密封半导体管芯；多个贯通封装通孔，位于模塑料中；以及界面层，位于贯通封装通孔和模塑料之间，其中，界面层包括聚合物材料且与模塑料直接接触。
该封装件结构进一步包括：第一重分布层，位于贯通封装过孔和半导体管芯的背侧上方，且电连接至贯通封装过孔的一个；以及第二重分布层，位于贯通封装过孔和半导体管芯的前侧上方，且电连接至贯通封装过孔的一个和半导体管芯的导电焊盘。
其中，界面层共形地覆盖贯通封装过孔的侧壁。
其中，半导体管芯位于界面层的平坦部分上方，且平坦部分基本平行于半导体管芯的背侧。
此外，还提供了一种形成封装件结构的方法，包括：在载体衬底上方形成基层、重分布层和多个导电列；在导电列的侧壁上方沉积界面层，其中，界面层包括绝缘材料；在重分布层上方设置半导体管芯；形成模塑料，以至少部分地密封半导体管芯、导电列和界面层，其中，模塑料直接接触界面层；在导电列和半导体管芯上方形成第二重分布层；以及去除载体衬底。
其中，将导电列直接电镀到重分布层上。
该方法进一步包括：去除基层的部分以暴露重分布层的部分；以及通过形成在第二半导体管芯和重分布层之间的连接件将第二半导体管芯堆叠在重分布层上方。
该方法进一步包括在堆叠第二半导体管芯之后，通过形成在管芯封装件和重分布层之间的连接件将管芯封装件接合至重分布层。
该方法进一步包括在导电列和半导体管芯上方形成第二重分布层之前，研磨模塑料以暴露导电列。
附图说明
为了更全面地理解本发明及其优势，现将结合附图所进行的以下描述作为参考，其中：
图1A是根据一些实施例的封装件结构的透视图。
图1B是根据一些实施例的两个接合的管芯封装件的截面图。
图2A至图2R是根据一些实施例的在形成封装件结构的工艺的各个阶段的截面图。
具体实施方式
下面，详细讨论本发明各实施例的制造和使用。然而，应该理解，各个实施例可以在多种具体环境中实施。所讨论的具体实施例仅仅是示例性的，而不用于限制本发明的范围。
以下公开内容提供了许多用于实施所提供的主题的不同特征的不同实施例或实例。以下描述组件和布置的具体实例以简化本发明。当然，这仅仅是实例，并不是用于限制本发明。此外，在以下描述中，第一工艺在第二工艺之前实施可以包括在第一工艺之后立即实施第二工艺的实施例，还可以包括在第一工艺和第二工艺之间实施额外的工艺的实施例。为了简单和清楚的目的，各个部件可以以不同的尺寸任意绘制。而且，在以下描述中，第一部件形成在第二部件上方或者上可以包括第一部件和第二部件直接接触的实施例，还可以包括在第一部件和第二部件之间形成有额外的部件，从而使得第一部件和第二部件不直接接触的实施例。
图1A根据一些实施例示出了封装件结构100的透视图，其中，管芯封装件110接合到另一管芯封装件120，管芯封装件120还接合到衬底130。管芯封装件110通过接合结构115接合到管芯封装件120，且管芯封装件120通过接合结构125接合到衬底130。每个管芯封装件(诸如管芯封装件110或管芯封装件120)都包括一个或多个半导体管芯。半导体管芯包括在半导体集成电路制造中使用的半导体衬底，并且集成电路可以在半导体衬底中或半导体衬底上形成。在各个实施例中，半导体衬底包括具有半导体材料(诸如，体硅、半导体晶圆、绝缘体上硅(SOI)衬底、硅锗衬底等)的结构。也可以使用包括III族、IV族、和V族元素的其他半导体材料。
半导体衬底还可以包括隔离部件(未示出)，诸如浅沟槽隔离(STI)部件或硅的局部氧化(LOCOS)部件。隔离部件可以限定和隔离形成在半导体衬底中的各种器件元件。各种器件元件的实例包括晶体管(例如，金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极结型晶体管(BJT)、高电压晶体管、高频率晶体管、p沟道和/或n沟道场效应晶体管(PFET/NFET)等)、二极管、或其他合适的元件。实施各种工艺(包括沉积、蚀刻、注入、光刻、退火和/或其他合适的工艺)以形成各种器件元件。将器件元件互连以形成集成电路器件，诸如，逻辑器件、存储器件(例如，静态随机存取存储器，SRAM)、射频(RF)器件、输入/输出(I/O)器件、***芯片(SoC)器件、它们的组合或其他应用类型的器件。
衬底130可以是半导体晶圆或晶圆的部分。在一些实施例中，衬底130包括硅、砷化镓、绝缘体上硅(“SOI”)或其他合适的材料。在一些实施例中，衬底130还包括无源器件(诸如，电阻器、电容器、电感器等)或有源器件(诸如，晶体管)。在一些实施例中，衬底130包括额外的集成电路。衬底130还包括直通衬底通孔(TSV)且可以是***件。
可选地，衬底130可以由其他材料制成。在一些实施例中，衬底130是诸如多层电路板的封装件衬底。在一些实施例中，封装件衬底还包括双马来酰亚胺三嗪(BT)树脂、FR-4(由具有耐火的环氧树脂粘结剂的编织玻璃纤维布组成的合成材料)、陶瓷、玻璃、塑料、胶带、薄膜或其他可以承载用于接收导电终端的导电焊盘或接合盘(land)的支撑材料。
在一些实施例中，使用球对球(ball-to-ball)接合工艺在管芯封装件110和管芯封装件120之间形成接合结构115的每一个。将形成在管芯封装件110和管芯封装件120上的两个焊球回流焊接到一起以形成接合结构115的一个。同样地，可以使用参考接合结构115描述的球对球接合工艺形成管芯封装件120和衬底130之间的接合结构125。
图1是根据一些实施例的与管芯封装件120接合的管芯封装件110的截面图。如图1B所示，管芯封装件110包括两个半导体管芯112和113，其中，半导体管芯113位于半导体管芯112上方。然而，管芯封装件110可以包括一个半导体管芯或两个以上半导体管芯。在一些实施例中，在半导体管芯112和113之间具有粘合层(未示出)。如上文对半导体管芯的描述，半导体管芯112和113可以包括各种器件元件。将半导体管芯112接合到衬底105。衬底105可以包括上文关于衬底130描述的各种材料和/或组件。
根据一些实施例，半导体管芯112通过接合线114电连接且相应地连接到衬底105中的导电元件119。同样地，半导体管芯113通过接合线116电连接且相应地连接到衬底105中的导电元件119。管芯封装件110还包括覆盖半导体管芯112和113以及接合线114和116的模塑料111。在管芯封装件110的底部上方形成许多用于连接的连接件117。在金属焊盘118上形成连接件117，金属焊盘118通过管芯封装件110的导电元件119电连接至接合线114和116。连接件117和金属焊盘118可以是如图1A所示的接合结构115的部分。
根据一些实施例，如图1B所示，管芯封装件120包括半导体管芯121和穿透模塑料131的贯通封装过孔(TPV)122。TPV 122环绕半导体管芯121。管芯封装件120还包括重分布结构126，重分布结构126包括一层或多层重分布层(RDL)123。RDL 123是金属互连层，其可以包括金属线和通孔，以及由介电材料环绕。RDL 123使能半导体管芯121的扇出。例如，RDL 123将连接件127电连接到TPV 122。对半导体管芯121的电连接横向延伸到半导体管芯121轮廓的外侧。可以将RDL 123重分布到比半导体管芯121的管芯区域大的区域上方。如图1B所示，将RDL 123重分布到模塑料131和TPV 122的上方。
如图1B所示，将诸如球栅阵列(BGA)的连接件129连接到重分布结构126上的金属焊盘(未示出)。连接件129可以是如图1A所示的接合结构125的部分。如图1B所示，TPV 122电连接到管芯封装件110的连接件117。半导体管芯121和连接件129位于重分布结构126的相对两侧上。半导体管芯121通过连接件127电连接到重分布结构126。
如图1B所示，通过模塑料131密封TPV 122。根据一些实施例，如图1B所示，界面层132形成在TPV 122和模塑料131之间。界面层132配置为改善TPV 122和模塑料131之间的粘合力。界面层132可以包括诸如聚合物材料的绝缘材料。在一些实施例中，绝缘材料包括聚苯并恶唑(PBO)、聚酰亚胺(PI)、其他合适的聚合物材料或它们的组合。界面层132对模塑料131和TPV 122都具有好的粘合力。因此，可以避免在TPV 122和模塑料131之间形成裂缝且避免裂缝在TPV 122和模塑料131之间传播。因为避免了裂缝的形成，也避免了RDL 123被裂缝破坏和/或打开，所以改善了电产率和可靠性条件。在一些其他方法中，没有形成界面层132。因此，在那些方法中，由于TPV 122和模塑料131之间的热膨胀系数(CTE)不匹配，所以在TPV 122和模塑料131之间会形成裂缝且裂缝可沿TPV 122和模塑料131之间的界面传播。
本发明的实施例具有许多变化。对本发明的实施例的一些变化进行了描述。根据一些实施例，图2A至图2R是形成封装件结构的工艺的各个阶段的截面图。
根据一些实施例，在图2A中，在载体衬底200上方依次沉积或层压粘合层202和基层204。载体衬底200用作临时支撑衬底。可以由半导体材料、陶瓷材料、聚合物材料、金属材料、其他合适的材料或它们的组合形成载体衬底200。在一些实施例中，载体衬底200是玻璃衬底。在一些其他实施例中，载体衬底200是诸如硅晶圆的半导体衬底。
粘合层202可以由胶制成，或可以是诸如箔的层压材料。在一些实施例中，粘合层202是光敏的，且易于通过载体衬底200上的闪亮的紫外线(UV)或激光从载体衬底200分离。例如，粘合层202是光热转换(LTHC)涂层。在一些其他实施例中，粘合层202是热敏的。在一些实施例中，基层204是聚合物层。基层204可以是PBO层、PI层、阻焊(SR)层、干膜式增层膜(ABF)、管芯附着膜(DAF)、其他应用材料或它们的组合。
如图2A所示，根据一些实施例，在基层204上方沉积晶种层206。在一些实施例中，晶种层206由铜制成，且通过物理汽相沉积(PVD)进行沉积。然而，本发明的实施例不限于此。也可以使用其他导电膜。例如，可以由Ti、Ti合金、Cu、Cu合金或它们的组合形成晶种层206。Ti合金或Cu合金可以包括银、铬、镍、锡、金、钨、其他合适的材料或它们的组合。
晶种层206的厚度为T1。在一些实施例中，厚度T1在约0.1μm到约0.6μm的范围内。在一些实施例中，形成较薄的晶种层206。在一些实施例中，在沉积晶种层206之前沉积扩散阻挡层(未示出)。可以由Ti或其他合适的材料制成扩散阻挡层，且其厚度在约0.01μm到约0.2μm的范围内。可选地，可以由诸如TaN或其他应用材料的其他材料制成扩散阻挡层，且其厚度范围不限于上述范围内。在一些实施例中，通过PVD沉积扩散阻挡层。在一些实施例中，没有形成扩散阻挡层。
根据一些实施例，如图2B所示，在沉积晶种层206之后，在晶种层206上方形成重分布层208。可以由Cu、Ni、Ti、其他应用材料或它们的组合制成重分布层208。重分布层208的厚度T2大于晶种层206的厚度T1。在一些实施例中，厚度T2在约2μm到约12μm的范围内。在一些实施例中，厚度T1对厚度T2的比率(T1/T2)在约0.8％到约30％的范围内。晶种层206可以考虑为重分布层208的部分。本发明的实施例具有许多变化。在一些其他实施例中，厚度T1对厚度T2的比率(T1/T2)是其他合适的范围，诸如从约0.5％到约40％。
在一些实施例中，通过电镀形成重分布层208。在晶种层206上方沉积光刻胶层(未示出)。在沉积光刻胶层之前，清洗晶种层206以确保沉积的光刻胶层对晶种层206具有好的粘合力。因此，可以改善随后图案化工艺的质量。可以通过诸如旋涂工艺的湿工艺或通过诸如干膜的干工艺沉积光刻胶层。然后，图案化光刻胶层以形成开口从而暴露晶种层206。涉及的工艺包括光刻和光刻胶显影工艺。也可以实施预处理工艺。然后，通过光刻胶层的开口将一种或多种导电材料电镀到暴露的晶种层206上以便完全或部分地填充开口且形成重分布层208。形成重分布层208之后，剥去光刻胶层。
根据一些实施例，如图2C所示，在晶种层206和重分布层208上方形成掩模层210。掩模层210具有暴露重分布层208的部分的开口。在一些实施例中，掩模层210还具有暴露晶种层206的部分的开口。掩模层210的开口限定随后形成的贯通封装过孔的位置。在一些实施例中，掩模层210由光刻胶材料制成。通过光刻工艺形成掩模层210的开口。光刻工艺可以包括曝光和显影工艺。在显影工艺中，在掩模层210上施加合适的溶液以部分去除掩模层210，使得形成开口。例如，在显影工艺之后，在曝光工艺期间，使用合适的辐射(诸如，UV光)对掩模层210的部分进行辐射以去除掩模层210的部分。
根据一些实施例，如图2D所示，形成掩模层210之后，形成导电列212以填充掩模层210的开口。在一些实施例中，将诸如铜的导电材料电镀到晶种层206和重分布层208的上方以填充掩模层210的开口且形成导电列212。位于晶种层206上方的重分布层208还用作喷镀晶种层。在这些情况下，在重分布层208上方没有形成额外的晶种层和钝化层以形成导电列212。将导电列212直接电镀到重分布层208上。
导电列212的一些位于由掩模层210的开口暴露的晶种层206上方。导电列212可以直接接触晶种层206。在导电列212和晶种层206之间形成界面214。导电列212的一些位于由掩模层210的开口暴露的重分布层208上方。导电列212可以直接接触重分布层208。在导电列212和重分布层208之间形成界面216。在晶种层206和重分布层208之间形成界面218。在导电列212和晶种层206之间具有两个界面(界面216和界面218)。在一些实施例中，在导电列212和晶种层206之间至多形成两个界面。
根据一些实施例，如图2E所示，去除掩模层210。然后，去除没有被重分布层208和导电列212覆盖的晶种层206的部分。可以使用蚀刻工艺以部分去除晶种层206。蚀刻工艺之后，暴露基层204的部分。
根据一些实施例，如图2F所示，在基层204、导电列212、晶种层206和重分布层208的上方形成界面层220。在一些实施例中，界面层220是连续的且没有分隔的部分。界面层220对导电列212和随后形成的模塑料具有好的粘合力。在一些实施例中，界面层220由诸如聚合物材料的绝缘材料形成。可以由聚苯并恶唑(PBO)、聚酰亚胺(PI)、其他应用材料或它们的组合制成界面层220。在一些其他实施例中，由氧化物材料、氮化物材料、氮氧化物材料或它们的组合形成界面层220。
通过使用合适的工艺沉积界面层220，诸如，旋涂工艺、汽相沉积聚合(VDP)工艺、汽相沉积工艺等。在一些实施例中，界面层220共形地覆盖导电列212的侧壁和顶部。在一些实施例中，界面层220包括位于重分布层208上方和导电列212之间的平坦部分221。平坦部分221的每一部分都具有基本平坦的顶面。
根据一些实施例，如图2G所示，半导体管芯222通过粘合层224连接到界面层220的平坦部分221。在一些实施例中，半导体管芯222的背侧222b面对平坦部分221，半导体管芯222的前侧222a面向上方。半导体管芯222的每一个可以包括位于半导体管芯222的前侧222a的钝化层226、导电焊盘228、保护层230和连接件232。在一些实施例中，半导体管芯222的背侧222b基本平行于平坦部分221。因此，可以将连接件232放置在相同的水平面或相同的高度处。连接件232的顶端可以基本位于相同的水平面。在一些实施例中，随后易于在具有基本相同高度的连接件232上方形成诸如重分布层的接触元件。
粘合层224可以直接接触半导体管芯222的背侧222b和平坦部分221。根据一些实施例，由管芯附着膜(DAF)形成粘合层224。可以由环氧树脂、酚树脂、丙烯酸橡胶、硅填料等或它们的组合形成DAF。在一些实施例中，界面层220是粘性的。在这些情况下，不使用粘合层224。将半导体管芯222直接设置且固定在界面层220的平坦部分221上。
根据一些实施例，如图2H所示，在图2G示出的结构上方形成模塑料234。模塑料234填充导电列212之间的空间且部分或全部密封半导体管芯222。在一些实施例中，将液体模塑料材料施加到界面层220和半导体管芯222上方以密封导电列212和半导体管芯222。然后，施加热工艺以使模塑料材料***，且将其变成模塑料234。现在导电列212成为贯通封装过孔(TPV)212’。在一些实施例中，TPV 212’环绕半导体管芯222。
如图2H所示，界面层220位于模塑料234和TPV 212’之间。界面层220对TPV 212’和模塑料234都具有高粘合力。在一些实施例中，界面层220直接接触模塑料234。在模塑料234和界面层220之间基本没有形成空隙或间隙。总的来说，界面层220的上面可以直接接触模塑料234。在一些实施例中，模塑料234通过界面层220与TPV 212’完全分隔。因为界面层220对模塑料234和TPV 212’都具有好的粘合力，所以在模塑料234和TPV 212’之间基本没有裂缝形成。大大减少或解决了诸如图1B所描述的裂缝问题。
根据一些实施例，如图2I所示，形成模塑料234之后，减薄模塑料234以暴露半导体管芯222的TPV 212’和连接件232。可以实施研磨工艺灯以减薄模塑料234。在一些实施例中，在减薄工艺期间，也去除位于TPV 212’顶部上方的界面层220的部分。在一些实施例中，实施金属凹进工艺以去除TPV 212’和连接件232上的残留物。残留物来自于模塑料234。可以通过使用蚀刻工艺等实现金属凹进工艺。然而，在一些其他实施例中，没有实施金属凹进工艺。
之后，根据一些实施例，如图2J所示，在图2I中示出的结构上方形成包括重分布层235和钝化层236的重分布结构。重分布层235形成至TPV212’和连接件232的多个电连接。例如，通过连接件232的一个将重分布层235的部分电连接至导电焊盘228的一个。重分布层235的部分将连接件232的一个电连接至TPV 212’的一个。重分布层235的部分电连接至TPV 212’的一个。可以一些说明可以调节重分布层235的图案。例如，如果使用不同的电路布局建立TPV 212’和导电焊盘228之间的连接，就可以因此改变重分布层235的图案。重分布层235的材料和形成方法可以类似于重分布层208。
由于界面层220提供了TPV 212’和模塑料234之间的高粘合力，所以在TPV 212’和模塑料234之间基本没有形成裂缝。因此，由于减少了裂缝问题，所以避免了重分布层235受到破坏。因此改善了重分布层235的质量和可靠性。
钝化层236可以包括一层或多层。钝化层236可以具有暴露重分布层235的部分的开口(未示出)。在暴露的重分布层235上方可以形成接合焊盘(未示出)。钝化层236由介电材料制成，且在随后的接合工艺期间，提供用于引发的接合应力的应力消除。在一些实施例中，由聚合物(诸如，聚酰亚胺、PBO等或它们的组合)形成钝化层236。可选地或额外地，钝化层236可以包括苯并环丁烯(BCB)。
根据一些实施例，如图2K所示，在钝化层236上方形成连接件238。可以通过钝化层236的开口(未示出)将连接件238安装(或接合)到重分布结构的接合焊盘(未示出)。通过重分布层235将连接件238的一些电连接到半导体管芯222的一个。通过重分布层235和TPV 212’的一个将连接件238的一些电连接到其他元件。连接件238可以包括焊料凸块。在连接件238下方可以形成凸块下金属(UBM)层(未示出)。
在一些实施例中，如图2L所示，形成连接件238之后，将图2K中示出的结构翻转且连接至载体240，以及去除载体衬底200。载体240包括光敏或热敏的且易于从连接件238分离的带。将载体衬底200和粘合层202都去除。可以提供合适的光以去除粘合层202，以便也去除载体衬底200。
根据一些实施例，如图2M所示，在基层204上方连接保护膜242。在去除载体衬底200之后，可发生图2L中示出的翘曲结构。保护膜242可以用于防止翘曲，使得随后的封装工艺可以平滑地实施。保护膜242可以包括阻焊膜、干膜式增层膜(ABF)、背侧层压膜(诸如芯片背侧涂层带)或其他合适的膜。然而，在一些实施例中，没有形成保护膜242。
根据一些实施例，如图2N所示，去除保护膜242和基层204的部分以形成暴露重分布层(诸如，晶种层206)的开口244。在一些实施例中，实施激光钻孔工艺以形成开口244。也可以使用诸如蚀刻工艺的其他合适的工艺形成开口。
根据一些实施例，形成开口244之后，实施蚀刻工艺以去除暴露的晶种层206的上部。在一些实施例中，晶种层206包括诸如Cu层和Ti层的多层。使用上文提到的蚀刻工艺以部分去除Ti层，使得Cu层暴露。然而，在一些实施例中，没有实施上文提到的蚀刻工艺。
之后，根据一些实施例，实施切割工艺以形成许多彼此隔开的管芯封装件，且图2O中示出了管芯封装件的一个。将载体240也去除。在一些实施例中，在暴露的晶种层206上方形成焊膏、焊剂、有机可焊性保护(OSP)层等用于保护焊盘。
根据一些实施例，如图2P所示，将半导体管芯246堆叠在图2O中示出的结构上方以形成管芯封装件320(或封装件结构)。半导体管芯246包括钝化层248、导电焊盘250和连接件252。在一些实施例中，连接件252是诸如Cu柱的导电柱。可以通过焊接材料254将半导体管芯246接合到晶种层206。可以实施回流焊接工艺以实现接合。在一些实施例中，在焊接材料254和晶种层206之间形成金属间化合物(IMC)256。
根据一些实施例，如图2Q所示，管芯封装件310接合至管芯封装件320。管芯封装件310可以类似于图1B中示出的管芯封装件110。管芯封装件310包括两个半导体管芯262和264，其中，半导体管芯262位于半导体管芯264上方。如上文所描述的半导体管芯，半导体管芯262和264可以包括各种器件元件。在一些实施例中，半导体管芯262和264是DRAM管芯。管芯264接合至衬底270，其中，衬底270类似于图1B中示出的衬底105。
根据一些实施例，通过接合线266和导电元件268将半导体管芯262和264电连接和相应地连接到衬底270中的导电元件272。管芯封装件310还包括模塑料258，模塑料258覆盖半导体管芯262和264，也覆盖接合线266。在管芯封装件310和320之间可以形成许多用于连接的连接件260。连接件260形成在金属焊盘274上。连接件260包括通过使用回流焊接工艺形成的焊料凸块。
根据一些实施例，如图2R所示，将底部填充胶276填充到管芯封装件310和320之间。底部填充胶276可以由树脂材料形成，且用于保护连接件260。
根据一些实施例，提供了一种封装件结构和用于形成封装件结构的方法。封装件结构包括穿透密封一个或多个半导体管芯的模塑料的贯通封装过孔。在模塑料和贯通封装过孔之间形成界面层以确保在模塑料和贯通封装过孔之间基本没有形成裂缝。因此，大大改善了封装件结构的性能和可靠性。
根据一些实施例，提供了一种封装件结构。该封装件结构包括半导体管芯和部分或全部密封半导体管芯的模塑料。封装件结构还包括位于模塑料中的贯通封装过孔。封装件结构还包括位于贯通封装过孔和模塑料之间的界面层。该界面层包括绝缘材料且与模塑料直接接触。
根据一些实施例，提供了一种封装结构。该封装结构包括半导体管芯和至少部分密封半导体管芯的模塑料。封装件结构还包括位于模塑料中的多个贯通封装过孔。封装件结构还包括位于贯通封装过孔和模塑料直接的界面层。该界面层包括聚合物材料且与模塑料直接接触。
根据一些实施例，提供了一种形成封装件结构的方法。该方法包括在载体衬底上方形成基层、重分布层和多个导电列。该方法还包括在导电列的侧壁上方沉积界面层，以及在重分布层上方设置半导体管芯。界面层包括绝缘材料。该方法还包括形成部分或全部密封半导体管芯、导电列和界面层的模塑料。模塑料与界面层直接接触。此外，该方法包括在导电列和半导体管芯上方形成第二重分布层且去除载体衬底。
尽管已经详细地描述了本发明的实施例及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、手段、方法和步骤的特定实施例。作为本领域普通技术人员应理解，根据本发明，可以使用现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造、材料组分、手段、方法或步骤。因此，附加的权利要求意指包括这些工艺、机器、制造、材料组分、手段、方法或步骤的范围。此外，每个权利要求构成一个独立的实施例，并且不同权利要求及实施例的组合均在本公开的范围之内。

Claims (10)

1.一种封装件结构，包括：
半导体管芯；
模塑料，至少部分地密封所述半导体管芯；
贯通封装通孔，位于所述模塑料中；以及
界面层，位于所述贯通封装通孔和所述模塑料之间，其中，所述界面层包括绝缘材料且与所述模塑料直接接触。
2.根据权利要求1所述的封装件结构，其中，所述界面层包括聚苯并恶唑(PBO)、聚酰亚胺(PI)或它们的组合。
3.根据权利要求1所述的封装件结构，进一步包括位于所述模塑料和所述半导体管芯的背侧上方的重分布层。
4.根据权利要求3所述的封装件结构，其中，所述重分布层电连接到所述贯通封装过孔。
5.根据权利要求4所述的封装件结构，进一步包括晶种层，其中，所述重分布层位于所述晶种层和所述贯通封装过孔之间，且所述晶种层与所述重分布层的厚度比率在约0.8％到约30％的范围内。
6.根据权利要求3所述的封装件结构，其中，所述界面层包括位于所述半导体管芯的背侧和所述重分布层之间的平坦部分，且所述平坦部分基本平行于所述半导体管芯的背侧。
7.根据权利要求3所述的封装件结构，进一步包括第二重分布层，其中，所述半导体管芯位于所述重分布层和所述第二重分布层之间，且所述第二重分布层电连接到所述半导体管芯的导电焊盘。
8.根据权利要求7所述的封装件结构，进一步包括位于所述第二重分布层上方的至少一个连接件。
9.一种封装件结构，包括：
半导体管芯；
模塑料，至少部分地密封所述半导体管芯；
多个贯通封装通孔，位于所述模塑料中；以及
界面层，位于所述贯通封装通孔和所述模塑料之间，其中，所述界面层包括聚合物材料且与所述模塑料直接接触。
10.一种形成封装件结构的方法，包括：
在载体衬底上方形成基层、重分布层和多个导电列；
在所述导电列的侧壁上方沉积界面层，其中，所述界面层包括绝缘材料；
在所述重分布层上方设置半导体管芯；
形成模塑料，以至少部分地密封所述半导体管芯、所述导电列和所述界面层，其中，所述模塑料直接接触所述界面层；
在所述导电列和所述半导体管芯上方形成第二重分布层；以及
去除所述载体衬底。
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US10128226B2 (en) 2018-11-13
US20170301663A1 (en) 2017-10-19
CN104658989B (zh) 2018-08-31
US9252065B2 (en) 2016-02-02
KR20150059635A (ko) 2015-06-01
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