CN104638014A - Junction-free multi-doped field effect transistor - Google Patents
Junction-free multi-doped field effect transistor Download PDFInfo
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- CN104638014A CN104638014A CN201510070234.8A CN201510070234A CN104638014A CN 104638014 A CN104638014 A CN 104638014A CN 201510070234 A CN201510070234 A CN 201510070234A CN 104638014 A CN104638014 A CN 104638014A
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Abstract
The invention relates to a junction-free multi-doped field effect transistor and belongs to the field of semiconductor device manufacturing. The junction-free multi-doped field effect transistor comprises a substrate, a source region, a channel region, a drain region, a gate dielectric layer and a gate electrode layer; the substrate is positioned at the lowest layer of the structure, and the source region, the channel region and the drain region are positioned on the substrate; the source region and the drain region are respectively formed at the two sides of the channel region; the source region, the channel region and the drain region are consistent in thickness; the doping type and concentration of the source region and the drain region are the same; the doping type of the channel region is the same with the doping type of the source region and the drain region; the junction-free multi-doped field effect transistor is characterized in that the doping concentration of the channel region is different from that of the source region and the drain region; the transistor also comprises spacer regions formed at the side surfaces of the gate dielectric layer and the gate electrode layer. The technological method provided by the invention is applicable to manufacturing ultra-short channel transistors, so that the short channel effect of devices can be effectively restrained, the driving capacity of the devices is improved, and the sensitivity of the devices on technological shift is reduced. The device forming method can be compatible with common CMOS (complementary metal oxide semiconductor) process, the manufacturing process is simple, and the production cost is low.
Description
Technical field
The invention belongs to field of manufacturing semiconductor devices, be specifically related to a kind of without the many doped field effect transistors of junction type.
Background technology
Along with the development of semiconductor technology, the size of semiconductor device constantly reduces, and the performances such as drive current constantly promote, and power consumption constantly reduces, also face more and more serious short channel effect, the semiconductor fabrication process become increasingly complex and higher production cost simultaneously.
A kind of effective ways of short channel effect are suppressed to strengthen grid-control ability exactly, the grid structures such as double grid, three grid, cylinder ring grid are constantly proposed, compare traditional single grid structure devices, multi-gate structure device can control raceway groove in multiple directions, grid-control ability significantly strengthens, so can the short ditch performance of effective boost device.
After device channel length enters dark nanoscale, the doping content of the source and drain abrupt PN junction of tradition transoid channel device needs to change several order of magnitude within a few nanometer, realize this large concentration gradient and all can bring very large difficulty for doping techniques and thermal margin design, and the manufacturing cost of these complicated technologies is very high, affect the mass production of semiconductor device.In addition, the dimension limit of abrupt PN junction space charge region is nanometer scale, so the existence of abrupt PN junction defines reducing further of channel length from physical essence.In order to overcome these difficulties, source-drain area and without junction field effect transistor be suggested consistent with concentration of channel region doping type.Because source-drain area and channel region intersection do not exist concentration gradient, device channel size enters dark nanometer and still can normally work later, and manufacturing process realizes simple, and production cost reduces.
Conventional nodeless mesh body pipe backing material is silicon or SOI, above substrate be the semi-conducting materials such as silicon formed source region, drain region and channel region, source region, drain region lay respectively at the both sides of channel region, and source region, drain region are all the same with doping content with the doping type of channel region.For P type doping nodeless mesh body pipe, impurity is generally the impurity such as boron, and typical doping content is 1*10
19cm
-3to 1*10
20cm
-3.Be coated with gate dielectric layer above raceway groove, above gate dielectric layer, be coated with gate electrode layer.
For conventional nodeless mesh body pipe, source region, drain region and channel region doping type and concentration are all the same, if doping content is higher, the short ditch performance of device can decline rapidly; If doping content is lower, source and drain resistance increases rapidly and causes drive current to decline.So under single doping content, device performance can not reach desirable state.
Summary of the invention
Object of the present invention is intended to solve the problem, propose a kind of without the many doped field effect transistors of junction type, be applicable to manufacture pole short-channel transistor, can effective suppression device short channel effect, improve the driving force of device, reduce the sensitiveness that device floats for technique.This device formation method is compatible with stand CMOS, and manufacturing process is simple, and production cost is low.
What the present invention proposed comprises without the many doped field effect transistors of junction type: substrate, source region, channel region, drain region, gate dielectric layer, gate electrode layer: described substrate is positioned at structure bottom, and described source region, channel region, drain region are positioned at substrate; Described source region and drain region are formed at both sides, channel region respectively; Described source region is identical with drain structure, and with channel region Central Symmetry; Described source region, channel region, drain region thickness uniformity; Described source region, channel region, drain region are silicon materials; Described source region is identical with concentration with drain region doping type; The doping type of described channel region is identical with drain region with source region; It is characterized in that; The doping content of described channel region is not identical with drain region with source region; Also comprise the spacer region being formed at gate dielectric layer and gate electrode layer side.
The doping content of described channel region is at 5*10
16cm
-3to 5*10
17cm
-3between.
The doping content in described source region and drain region is 100 times of channel region doping content, at 5*10
18cm
-3to 5*10
19cm
-3between.
Described gate dielectric layer covers the outer surface of whole channel region; Described gate dielectric layer is high k hafnium oxide material dielectric layer;
Described gate dielectric layer thickness is 1 nanometer.
Described gate electrode layer covers the outer surface of whole gate dielectric layer; Described gate electrode layer is titanium nitride material; Described gate electrode layer work function is 4.6 electron-volts.
Described spacer region is silicon nitride material.
Feature of the present invention and beneficial effect:
The present invention propose without the many doped field effect transistors of junction type, be have employed many doping with the topmost difference of conventional nodeless mesh body pipe, namely channel region and source region, drain region adopt different doping contents, and need increase isolated area to realize adulterate more.Channel region doping content is different from source region and drain region, can carry out independent adjustment respectively according to performance need.Reduce channel region doping content, can the short ditch performance of significantly boost device, particularly reduce threshold voltage rolloff and leakage and cause potential barrier and reduce, reduce device subthreshold swing, reduce the sensitiveness that device floats for technique; Increase the doping content in source region and drain region, the source and drain resistance of device can be effectively reduced, and then the driving force of significantly boost device.Because channel region doping type is consistent with source region and drain region, abrupt PN junction is there is not between raceway groove and source and drain, so the present invention propose still maintain the simple feature of technique without the many doped field effect transistors of junction type, production cost is lower, and after channel length enters dark nanoscale, transistor still can work.What the present invention proposed adopts high k hafnium oxide material without junction type many doped field effect transistors gate dielectric layer, when keeping dielectric layer physical thickness constant, can obtain less equivalent dielectric thickness, effectively can promote the short ditch performance of transistor.The present invention propose without the many doped field effect transistors of junction type be very small dimensions of future generation, high performance device mass production and application provide a kind of effectively scheme.
Accompanying drawing explanation
The embodiment that Fig. 1 the present invention proposes is without the three-dimensional structure schematic diagram of junction type many doping three grid field effect transistor.
The embodiment that Fig. 2 the present invention proposes is without the XY schematic cross-section of junction type many doping three grid field effect transistor.
Fig. 3 is the contrast that embodiment transistor AND gate conventional transistors roll-offs in different channel lengths threshold voltages.
Fig. 4 is that embodiment transistor AND gate conventional transistors leaks the contrast causing potential barrier and reduce under different channel lengths.
Fig. 5 is the contrast of embodiment transistor AND gate conventional transistors subthreshold swing under different channel lengths.
Fig. 6 is that embodiment transistor AND gate conventional transistors threshold voltage is to the contrast of channel width sensitiveness.
Fig. 7 is that the leakage of embodiment transistor AND gate conventional transistors causes the contrast of potential barrier reduction to channel width sensitiveness.
Fig. 8 is that embodiment transistor AND gate conventional transistors subthreshold swing is to the contrast of channel width sensitiveness.
Embodiment
Below in conjunction with accompanying drawing, and by specific embodiment, the present invention is described in further detail.
As shown in Figure 1, in embodiment, transistor has three grid structures to the three-dimensional structure schematic diagram of the embodiment without the many doped field effect transistors of junction type that the present invention proposes.For convenience of description, according to reference axis definition direction: X-axis negative direction be " on ", X-axis positive direction is D score, and Y-axis negative direction is " front ", and Y-axis positive direction is " afterwards ", and Z axis negative direction is " left side ", and Z axis positive direction is " right side ".Embodiment foot is substrate 101; Substrate is source region 102, channel region, drain region 105 from front to back successively, channel region length is in X direction called channel thickness, channel region is called channel length along the length of Y-direction, channel region is called channel width along the length of Z-direction, whole channel region cover by the gate dielectric layer 103 outside it, therefore do not show channel region in Fig. 1; Cover outside gate dielectric layer is gate electrode layer 104; In order to diagram is clear, spacer region does not show in FIG.
Figure 2 shows that the schematic cross-section of embodiment in XY plane in Fig. 1, sectional position is in the center of channel width.Fig. 2 foot is substrate 201; Substrate is source region 202, channel region 206, drain region 205 respectively; It is gate dielectric layer 203 above channel region; It is gate electrode layer 204 above gate dielectric layer; Gate dielectric layer and gate electrode layer both sides are spacer region 207 and spacer region 208 respectively.
The design parameter of each composition of the present embodiment further illustrates as follows:
Substrate 201 is the silicon (SOI) in dielectric substrate, and wherein silicon dioxide insulating layer thickness is 0.3um.
Source region 202 and drain region 205 are all highly doped silicon materials, and doping type is P type, and impurity is boron, and doping content is 1*10
19cm
-3.Channel region 206 is low-doped silicon materials, and doping type is P type, and impurity is boron, and doping content is 1*10
17cm
-3.Source region 202, drain region 205, channel region 206 are cube, and thickness is 10nm, and width is 10nm, and source region 202 and drain region 205 length are 30nm, and channel region 206 length is 20nm.
Gate dielectric layer 203 is hafnium oxide material, and it covers on the lateral surface of three, channel region, and thickness is 1nm.
Gate electrode layer 204 is titanium nitride material, and it covers outside gate dielectric layer, and work function is 4.6 electron-volts.
Spacer region 207 and 208 is silicon nitride material, and it is formed at gate dielectric layer 203 and gate electrode layer 204 both sides, and cover the part in source region 202 and drain region 205 respectively, overlay length is 4nm.The impurity that the effect of spacer region is mainly used for source region and drain region injects, formed source region, drain region highly doped.
The present embodiment and stand CMOS technical compatibility, available common process realizes.
The parameter of above embodiment and performance are all obtain based on TCAD software emulation.
The performance comparison of the present embodiment and existing device is described as follows:
Transistor as a comparison, the substrate of conventional nodeless mesh body pipe is SOI, and the channel region above substrate, source region, drain region doping type are P type, and dopant material is boron, and doping content is 1*10
19cm
-3, covered completely by gate dielectric layer hafnium oxide outside channel region, covered completely by gate electrode layer titanium nitride outside gate dielectric layer.More the present embodiment and the topmost difference of conventional nodeless mesh body pipe have employed adulterate, and namely channel region and source region, drain region adopt different doping contents, and need to increase isolated area to realize many doping.
Keeping under the prerequisite that embodiment is consistent with contrast transistor off-state current, embodiment transistor ON state current is 0.45 milliampere, and contrast transistor ON state current is 0.46 milliampere, and the driving force of two devices is identical.
Transistor channel region in the present embodiment and source region, drain region doping type are the same, and it is accumulation devices.When source region and drain region doping content constant, when channel region doping content reduces, device suppresses the performance of short channel effect significantly to improve, and subthreshold swing reduces; By selecting suitable spacer lengths, driving force can be made substantially constant.When channel region, doping content is constant, and when source region and drain region doping content increase, device source ohmic leakage reduces, and driving force improves, and suppresses the performance of short channel effect slightly to reduce.In sum, by reducing the doping content of transistor channel region, increasing the doping content in source region and drain region, when keeping driving force substantially constant, significantly can improve the performance that device suppresses short channel effect, reducing the subthreshold swing of device.When the doping content in transistor source region and drain region is 100 times of channel region doping content, above-mentioned target can be realized.
Figure 3 shows that the contrast that two transistor threshold voltages roll-off, square mark represents embodiment transistor, circle marker representative contrast transistor.Under various channel length, embodiment transistor threshold voltage roll-offs and is all less than contrast transistor, and along with channel length reduction, both gaps are increasing, special under extremely short 8nm channel length, embodiment transistor threshold voltage roll-offs for-0.023 volt, only has 25% of contrast transistor.So embodiment transistor suppresses the ability of short channel effect to be obviously greater than contrast transistor.
Figure 4 shows that two transistors leak the contrast causing potential barrier and reduce, square mark represents embodiment transistor, circle marker representative contrast transistor.Embodiment transistor leak under each channel length cause potential barrier reduce all be less than contrast transistor, and along with channel length reduce, both gaps are increasing.Special under extremely short 8nm channel length, embodiment transistor leaks and causes potential barrier and be reduced to-65.7 millivolts/volt, and the leakage contrasting transistor causes potential barrier and is reduced to-123 millivolts/volt.So embodiment transistor suppresses the ability of short channel effect to be obviously greater than contrast transistor.
Figure 5 shows that the contrast of two transistor sub-threshold amplitudes of oscillation, square mark represents embodiment transistor, circle marker representative contrast transistor.Embodiment transistor under each channel length subthreshold swing all comparison is less than transistor 4 ~ 5 millivolts/ten times, so embodiment transistor can provide better subthreshold value performance.
Transistor performance is an important indicator of transistor stability to the sensitiveness that technique is floated, and in small size tri-gate transistors manufacture process, floating of device channel width is larger, so device performance needs to pay close attention to the sensitiveness of channel width.
Figure 6 shows that the threshold voltage of embodiment transistor AND gate contrast transistor is to the contrast of channel width sensitiveness, square mark represents embodiment transistor, circle marker representative contrast transistor.Embodiment transistor is all less than contrast transistor in the change of each channel width threshold voltages, and along with channel width increase, both gaps are increasing.Under 15nm channel width, embodiment transistor threshold voltage is changed to-0.08 volt, and contrasts the threshold voltage variation of transistor for-0.26 volt.
Figure 7 shows that the leakage of embodiment transistor AND gate contrast transistor causes the contrast of potential barrier reduction to channel width sensitiveness, square mark represents embodiment transistor, circle marker representative contrast transistor.Embodiment transistor leak under each channel width cause potential barrier reduce all be less than contrast transistor, and along with channel width increase, both gaps are increasing.Under 15nm channel width, embodiment transistor leak cause potential barrier be reduced to-26.4 millivolts/volt, and the leakage contrasting transistor cause potential barrier be reduced to-81.4 millivolts/volt.
Figure 8 shows that the subthreshold swing of embodiment transistor AND gate contrast transistor is to the contrast of channel width sensitiveness, square mark represents embodiment transistor, circle marker representative contrast transistor.Embodiment transistor subthreshold swing under each channel width is all less than contrast transistor.Under 15nm channel width, the embodiment transistor sub-threshold amplitude of oscillation is-70.5 millivolts/ten times, and the subthreshold swing contrasting transistor is-78.3 millivolts/ten times.
To sum up can obtain, embodiment transistor suppresses the ability of short channel effect to be obviously greater than contrast transistor, declines to a great extent to channel width sensitiveness simultaneously, so embodiment transistor has better performance and stability, is applicable to manufacture pole short channel device.
Claims (7)
1. without the many doped field effect transistors of junction type, comprising: substrate, source region, channel region, drain region, gate dielectric layer, gate electrode layer: described substrate is positioned at structure bottom, described source region, channel region, drain region are positioned at substrate; Described source region and drain region are formed at both sides, channel region respectively; Described source region is identical with drain structure, and with channel region Central Symmetry; Described source region, channel region, drain region thickness uniformity; Described source region, channel region, drain region are silicon materials; Described source region is identical with concentration with drain region doping type; The doping type of described channel region is identical with drain region with source region; It is characterized in that; The doping content of described channel region is not identical with drain region with source region; Also comprise the spacer region being formed at gate dielectric layer and gate electrode layer side.
2. as claimed in claim 1 a kind of without the many doped field effect transistors of junction type, it is characterized in that, the doping content of described channel region is at 5*10
16cm
-3to 5*10
17cm
-3between.
3. as claimed in claim 1 a kind of without the many doped field effect transistors of junction type, it is characterized in that, described source region is identical with the doping content in drain region, at 5*10
18cm
-3to 5*10
19cm
-3between.
4. as claimed in claim 1 a kind of without the many doped field effect transistors of junction type, it is characterized in that, described gate dielectric layer covers the outer surface of whole channel region; Described gate dielectric layer is high k hafnium oxide material dielectric layer.
5. as claimed in claim 4 a kind of without the many doped field effect transistors of junction type, it is characterized in that, described gate dielectric layer thickness is 1 nanometer.
6. as claimed in claim 1 a kind of without the many doped field effect transistors of junction type, it is characterized in that, described gate electrode layer covers the outer surface of whole gate dielectric layer; Described gate electrode layer is titanium nitride material; Described gate electrode layer work function is 4.6 electron-volts.
7. as claimed in claim 1 a kind of without the many doped field effect transistors of junction type, it is characterized in that, described spacer region is silicon nitride material.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111883579A (en) * | 2020-08-10 | 2020-11-03 | 北京大学深圳研究生院 | Junction-free field effect transistor and manufacturing method thereof |
| CN113169221A (en) * | 2020-07-17 | 2021-07-23 | 北京大学深圳研究生院 | Junction-free nanowire field effect transistor and manufacturing method thereof |
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| CN103915342A (en) * | 2013-01-08 | 2014-07-09 | 中芯国际集成电路制造(上海)有限公司 | Junction-free transistor and complementary forming method of junction-free transistor |
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2015
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Patent Citations (4)
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| US20070040221A1 (en) * | 2005-08-19 | 2007-02-22 | Harald Gossner | Electrostatic discharge protection element |
| CN101740618A (en) * | 2008-11-10 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | Metal-semiconductor field effect transistor |
| CN102983171A (en) * | 2012-12-11 | 2013-03-20 | 哈尔滨工程大学 | Structure and manufacturing method of vertical junctionless gate-all-round MOSFET device |
| CN103915342A (en) * | 2013-01-08 | 2014-07-09 | 中芯国际集成电路制造(上海)有限公司 | Junction-free transistor and complementary forming method of junction-free transistor |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113169221A (en) * | 2020-07-17 | 2021-07-23 | 北京大学深圳研究生院 | Junction-free nanowire field effect transistor and manufacturing method thereof |
| WO2022011679A1 (en) * | 2020-07-17 | 2022-01-20 | 北京大学深圳研究生院 | Junctionless nanowire field effect transistor and method for manufacturing same |
| CN113169221B (en) * | 2020-07-17 | 2023-06-27 | 北京大学深圳研究生院 | Junction-free nanowire field effect transistor and manufacturing method thereof |
| CN111883579A (en) * | 2020-08-10 | 2020-11-03 | 北京大学深圳研究生院 | Junction-free field effect transistor and manufacturing method thereof |
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