CN104637537B - A kind of flush memory device and its programmed method - Google Patents
A kind of flush memory device and its programmed method Download PDFInfo
- Publication number
- CN104637537B CN104637537B CN201410654597.1A CN201410654597A CN104637537B CN 104637537 B CN104637537 B CN 104637537B CN 201410654597 A CN201410654597 A CN 201410654597A CN 104637537 B CN104637537 B CN 104637537B
- Authority
- CN
- China
- Prior art keywords
- memory device
- flush memory
- substrate
- floating gate
- applies
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The present invention provides a kind of flush memory device and programmed method, including substrate, in cylindrical structure, the end of substrate is respectively source and drain terminal；Grid is coated on the middle section of substrate, the first insulating layer is equipped between grid and substrate, wherein grid includes control gate and floating gate arranged side by side；Contact line is drawn from two ends respectively, for applying underlayer voltage.The thermoelectron generation mechanism that the programmed method of flush memory device of the present invention utilizes backgate bias to assist, drain terminal can be made plus lower voltage, it effectively shortens a point critical size for column grid floating gate flash memory, increases the cell density of flash array, that is, increase the memory capacity and density of flash memory；The present invention assists thermionic movement by being biased, and provides the energy of enough more layers to complete to compile, improves the compiling efficiency of flash memory, reduces compiling current power dissipation.
Description
Technical field
The present invention relates to semiconductor integrated circuit and its manufacturing field more particularly to a kind of flush memory device and its programming sides
Method.
Background technique
In semiconductor storage, flash memory (flash memory) is a kind of non-volatile (non-volatile) storage
Device, and belong to Erasable Programmable Read Only Memory EPROM (erasable programmable read-onlymemory, EPROM).
In general, flash memory tool is there are two grid (floating grid and a control grid), wherein floating grid is controlled to store charge
Grid processed is then to control the input and output of data.The position of floating grid control grid under, due to external circuit
There is no connections, are at floating state.The advantages of flash memory is that it can be wiped for whole memory block, and wipe speed
Degree is fast, about only needs 1 to 2 second.In general, flash memory is grid dividing structure or the combination for stacking grid structure or two kinds of structures.It is sub-gate
Flash memory is due to its special structure, and compared to flash memory in grating is stacked, that its unique performance is all embodied when programmed and erased is excellent
Gesture, in recent years, gate-division type flash memory have been widely used on various electronic consumer products.
When making highdensity semiconductor element on an integrated circuit die, it is necessary to consider how to reduce each storage list
The size and power consumption of first (memory cell), so that its service speed is accelerated.However existing flash memory is in higher deposit of marching toward
When storing up density, due to being limited by program voltage, it will be faced very by reducing device size to improve storage density
Big challenge.Traditional flash memory, due to being limited by structure, realizes the programming of device when marching toward more high storage density
Voltage, which further decreases, will be faced with very big challenge.
A kind of code generation of the U.S. Patent Publication of Publication No. US5300803 A is SSI (Source Side
Injection nonvolatile memory structure), the patent solve the inefficient injection of floating gate flash memory device and asking for high power consumption
Topic.The background technique of the patent describes traditional floating gate flash memory device, to guarantee high channel hot electron generation rate and high
Thermoelectron injection efficiency applies high voltage in drain terminal and grid, and electronics flows to drain electrode from source electrode and makees in vicinity high electric field
Thermoelectron is generated with lower acceleration, the oxide layer that part thermoelectron passes through below floating gate enters floating gate, completes programming operation.But it is this
Traditional floating gate flash memory device brings the big problem of low and current power dissipation of channel hot electron injection efficiency, for solve should
Problem, the patent proposes one kind to divide column flash memory in grating device, and the grid on the left side is control gate, and the grid on right side is floating gate, floating gate
It is spatially staggered with control gate, wherein floating gate applies high voltage, and control gate applies low-voltage, and drain terminal applies high voltage.
Due to reducing control-grid voltage, causes the inversion charge number of induction less, shorten the distance of electronics acceleration, reduce heat
The number of electronics, so that program current is reduced, while increasing the electronics of injection floating gate, this improves channel hot electron notes
Enter efficiency, and reduces current power dissipation.
But the technical solution in above-mentioned patent has other one: since the voltage that drain terminal is applied is relatively high, causing
The depletion width that drain terminal extends to substrate is bigger, and source and depletion region are easy to touch one in the case where high voltage
It rises, leads to device break-through and failure, i.e. generation channel punchthrough effect (Channel punchthrough effect), be source
A kind of phenomenon being connected with the depletion region of drain terminal, this defect often limit flush memory device and carry out technology node in technique
The diminution of upgrading and critical size.
Summary of the invention
The object of the present invention is to provide a kind of flush memory device and its programmed methods, can effectively avoid the occurrence of channel and wear
Logical defect reduces the critical size of flush memory device, improves the reliability of flush memory device.
To solve the above problems, the present invention provides a kind of flush memory device, comprising:
Substrate, in cylindrical structure, the substrate includes middle section and positioned at two of middle section two sides
End, the end are respectively source and drain terminal；
Grid is coated on the middle section of the substrate, and the first insulating layer is equipped between the grid and the substrate；Its
In, the grid includes control gate and floating gate arranged side by side, is formed with second insulating layer between the control gate and the floating gate；
Contact line is drawn respectively from two ends, for applying underlayer voltage.
Preferably, the material of first insulating layer is silica, with a thickness of 2nm~3nm；The second insulating layer
Material is silica, and length is 2.5nm~3.5nm.
Preferably, the material of the floating gate is polysilicon, and height is 60~80nm, and length is 30~50nm.
Preferably, the material of the control gate is polysilicon, and height is 80~95nm, and length is 5~15nm.
Preferably, the material of the contact line is tungsten.
The present invention also provides a kind of programmed methods of flush memory device, are programmed operation to flush memory device described above
When, the voltage value that the control gate applies is equal with the threshold voltage value of the flush memory device, the voltage value that the floating gate applies
Greater than the threshold voltage value of the flush memory device, it is 3V~4V that the drain terminal, which applies voltage range, and the substrate applies voltage model
It encloses for 5V~6V.
Preferably, the voltage value that the control gate applies is equal with the threshold voltage value of the flush memory device, the floating gate
The voltage value of application is twice of the threshold voltage value of the flush memory device, and it is 4V that the drain terminal, which applies voltage, and the substrate is applied
Making alive is 5V.
Preferably, the source applies 0V voltage.
It can be seen from the above technical proposal that columned substrat structure is used in flush memory device provided by the invention,
Thereon by grid cladding, end is drawn by contact line, for applying underlayer voltage.Compared with prior art, use is cylindric
Structure enables to the voltage of control gate and floating gate that can preferably control channel, and reduce that the broadening of source and drain depletion region occupies is total
The percentage of depletion region size inhibits short-channel effect, resists threshold voltage shift, reduces the readout error of flash memory.The present invention
The thermoelectron generation mechanism that the programmed method of flush memory device utilizes backgate bias to assist can make drain terminal add lower voltage,
It effectively shortens a point critical size for column grid floating gate flash memory, increases the cell density of flash array, that is, increase the storage of flash memory
Capacity and density；The present invention assists thermionic movement by being biased, and the energy for providing enough more layers comes
Compiling is completed, the compiling efficiency of flash memory is improved, reduces compiling current power dissipation.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of flush memory device of the present invention；
Fig. 2 is the cross-sectional view of the structure of flush memory device of the present invention.
Specific embodiment
To keep the contents of the present invention more clear and easy to understand, below in conjunction with Figure of description, the contents of the present invention are made into one
Walk explanation.Certainly the invention is not limited to the specific embodiment, general replacement known to those skilled in the art
It is included within the scope of protection of the present invention.Secondly, the present invention has carried out detailed statement using schematic diagram, it is real the present invention is described in detail
When example, for ease of description, schematic diagram is not partially enlarged in proportion to the general scale, should not be in this, as limitation of the invention.
Above and other technical characteristic and beneficial effect, by conjunction with the embodiments and attached drawing 1 to Fig. 2 to flash memories of the invention
The programmed method of part is described in detail.Fig. 1 is the structural schematic diagram of flush memory device of the present invention；Fig. 2 is flush memory device of the present invention
Cross-sectional view of the structure.
Fig. 1,2 are please referred to, in the present embodiment, the present invention provides a kind of flush memory device, including substrate 10, grid and connects
Touch line 80；Wherein, substrate 10 is in cylindrical structure, and substrate 10 includes middle section and positioned at two of middle section two sides
End, end are respectively source 20 and drain terminal 30；Grid is coated on the middle section of substrate, and first is equipped between grid and substrate
Insulating layer 40, grid include control gate 50 and floating gate 60 arranged side by side, and the second insulation is formed between control gate 50 and floating gate 60
Layer 70；Contact line 80 is drawn from two ends respectively, for applying 10 voltage of substrate.
Specifically, the material of floating gate 60 is preferably polysilicon, height is 60~80nm, and length is 30~50nm, control
The material of grid 50 is preferably polysilicon, and height is 80~95nm, and length is 5~15nm.The material of first insulating layer 40 is two
Silica, with a thickness of 2nm~3nm；The material of second insulating layer 70 is silica, and length is 2.5nm~3.5nm.
Embodiment one
In this implementation, the material of control gate 50 and floating gate 60 is all made of polysilicon, 50 length 10nm of control gate, height
90nm, floating gate 60 height 70nm, length 40nm；First insulating layer 40 and 70 material of second insulating layer are silica, and first
Insulating layer 40 with a thickness of 2.5nm, the length of second insulating layer 70 is 3nm.The manufacturing process of the device can be selected top-down
The technology compatible with standard CMOS process.
Flash memories provided by the invention use columned substrat structure, and thereon by grid cladding, end is logical
Contact line extraction is crossed, for applying underlayer voltage.Compared with prior art, control gate and floating gate are enabled to using cylindrical-shaped structure
Voltage can preferably control channel, reduce the percentage for total depletion region size that the broadening of source and drain depletion region occupies, inhibit
Short-channel effect resists threshold voltage shift, reduces the readout error of flash memory；In addition, contact line extends from two ends respectively
Out, convenient for substrate application high voltage.
The present invention also provides a kind of programmed methods of flush memory device, when being programmed operation to above-mentioned flush memory device, control
The voltage value that grid 50 apply is equal with the threshold voltage value of flush memory device, and the voltage value that floating gate 60 applies is greater than the threshold of flush memory device
Threshold voltage value, it is 3V~4V that drain terminal 30, which applies voltage range, and it is 5V~6V that substrate 10, which applies voltage range,.
Embodiment two
The voltage value that control gate 50 applies is equal with the threshold voltage value of flush memory device, and the voltage value that floating gate 60 applies is to dodge
Twice of the threshold voltage value of memory device, it is 4V that drain terminal 30, which applies voltage, and it is 5V that substrate 10, which applies voltage, and source 20 applies 0V electricity
Pressure.
Fundamentals of Compiling of the invention are as follows: the voltage value that control gate 50 applies is equal with the threshold voltage value of flush memory device,
Its lower substrate area induces relatively thin channel electrons layer.The voltage value that floating gate 60 applies is the two of the threshold voltage value of flush memory device
Times, it induces in its lower channel electronic shell compared with thick-channel electronic shell.10 high voltage of substrate accelerates the electricity of relatively thin channel electrons layer
Son generates the thermoelectron with enough energy and injects floating gate under floating gate action of high voltage and completes compiling.
The thermoelectron generation mechanism that the present invention utilizes backgate bias to assist can make drain terminal plus lower voltage, effectively
Shorten the critical size for dividing column grid floating gate flash memory, increases the cell density of flash array, that is, increase the memory capacity of flash memory
And density；The present invention assists thermionic movement by being biased, and provides the energy of enough more layers to complete
Compiling improves the compiling efficiency of flash memory, reduces compiling current power dissipation.
Above is merely a preferred embodiment of the present invention, the scope of patent protection that embodiment is not intended to limit the invention,
Therefore all to change with equivalent structure made by specification and accompanying drawing content of the invention, it similarly should be included in of the invention
In protection scope.
Claims (7)
1. a kind of flush memory device characterized by comprising
Substrate, in cylindrical structure, the substrate includes middle section and two ends positioned at middle section two sides,
The end is respectively source and drain terminal；
Grid is coated on the middle section of the substrate, and the first insulating layer is equipped between the grid and the substrate；Wherein,
The grid includes control gate and floating gate arranged side by side, is formed with second insulating layer between the control gate and the floating gate；When
When the flush memory device is programmed operation, the threshold voltage value phase of voltage value and the flush memory device that the control gate applies
Deng the voltage value that the floating gate applies is greater than the threshold voltage value of the flush memory device, and it is 3V that the drain terminal, which applies voltage range,
~4V, it is 5V~6V that the substrate, which applies voltage range, so that inducing in control gate lower substrate region compared with thin channel
Electronic shell induces in floating gate lower substrate region compared with thick-channel electronic shell, and the high voltage on substrate accelerates relatively thin channel electrons
The electronics of layer generates the thermoelectron with enough energy and injects floating gate under floating gate action of high voltage and completes compiling；
Contact line is drawn respectively from two ends, for applying underlayer voltage.
2. flush memory device as described in claim 1, which is characterized in that the material of first insulating layer is silica, thick
Degree is 2nm~3nm；The material of the second insulating layer is silica, and length is 2.5nm~3.5nm.
3. flush memory device as described in claim 1, which is characterized in that the material of the floating gate is polysilicon, height 60
~80nm, length are 30~50nm.
4. flush memory device as described in claim 1, which is characterized in that the material of the control gate is polysilicon, and height is
80~95nm, length are 5~15nm.
5. flush memory device as described in claim 1, which is characterized in that the material of the contact line is tungsten.
6. flush memory device as described in claim 1, which is characterized in that the voltage value and the flash memories that the control gate applies
The threshold voltage value of part is equal, and the voltage value that the floating gate applies is twice of the threshold voltage value of the flush memory device, described
It is 4V that drain terminal, which applies voltage, and it is 5V that the substrate, which applies voltage,.
7. flush memory device as described in claim 1, which is characterized in that the source applies 0V voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410654597.1A CN104637537B (en) | 2014-11-17 | 2014-11-17 | A kind of flush memory device and its programmed method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410654597.1A CN104637537B (en) | 2014-11-17 | 2014-11-17 | A kind of flush memory device and its programmed method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104637537A CN104637537A (en) | 2015-05-20 |
| CN104637537B true CN104637537B (en) | 2019-02-19 |
Family
ID=53216187
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410654597.1A Active CN104637537B (en) | 2014-11-17 | 2014-11-17 | A kind of flush memory device and its programmed method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104637537B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4882707A (en) * | 1986-10-27 | 1989-11-21 | Kabushiki Kaisha Toshiba | Non-volatile semi-conductor memory device with double gate structure |
| EP1508926A1 (en) * | 2003-08-19 | 2005-02-23 | Hitachi, Ltd. | Nanotube transistor device |
| CN1938785A (en) * | 2003-11-07 | 2007-03-28 | 桑迪士克股份有限公司 | Flash memory programming using gate induced junction leakage current |
| CN103915442A (en) * | 2014-04-08 | 2014-07-09 | 上海华力微电子有限公司 | Flash memorizer |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW578271B (en) * | 2002-12-18 | 2004-03-01 | Ememory Technology Inc | Fabrication method for flash memory having single poly and two same channel type transistors |
-
2014
- 2014-11-17 CN CN201410654597.1A patent/CN104637537B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4882707A (en) * | 1986-10-27 | 1989-11-21 | Kabushiki Kaisha Toshiba | Non-volatile semi-conductor memory device with double gate structure |
| EP1508926A1 (en) * | 2003-08-19 | 2005-02-23 | Hitachi, Ltd. | Nanotube transistor device |
| CN1938785A (en) * | 2003-11-07 | 2007-03-28 | 桑迪士克股份有限公司 | Flash memory programming using gate induced junction leakage current |
| CN103915442A (en) * | 2014-04-08 | 2014-07-09 | 上海华力微电子有限公司 | Flash memorizer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104637537A (en) | 2015-05-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Li et al. | NAND flash memory: Challenges and opportunities | |
| US9406685B2 (en) | Flash memory unit and memory array, and programming, erasing and reading method thereof | |
| CN103413786A (en) | Storage unit, forming method of storage unit and driving method of storage unit | |
| TW201637018A (en) | Electrically-Erasable Programmable Read-Only Memory of reducing voltage difference and operation method thereof | |
| CN104377248B (en) | A kind of floating gate flash memory device and its programmed method | |
| CN104637537B (en) | A kind of flush memory device and its programmed method | |
| US10964391B2 (en) | Programming circuit and programming method of flash memory and flash memory | |
| Cho et al. | Adaptive multi-pulse program scheme based on tunneling speed classification for next generation multi-bit/cell NAND flash | |
| CN101740120A (en) | Programming method for shared-word line split-gate type flash memory | |
| CN104332471B (en) | A kind of SONOS flush memory devices and its Compilation Method | |
| TWI571880B (en) | Effective programming method for non-volatile flash memory | |
| CN101494087B (en) | Operating method of multi-level memory cell | |
| CN103811060A (en) | EEPROM (Electrically Erasable Programmable Read Only Memory) and memory array thereof | |
| CN104733045A (en) | Double-bit flash memory, and programming, erasing and reading method thereof | |
| CN104183273B (en) | Programming method of flash memory device | |
| CN102789812A (en) | NOR memory cell based on resistance-changeable gate dielectric, its array and its operation method | |
| CN106935261A (en) | A kind of programmed method of memory cell | |
| CN101800226B (en) | Polysilicon storage unit | |
| CN102034539A (en) | Method for programming/erasing nanocrystalline device | |
| TWI695489B (en) | Low-voltage fast erasing method of electronic writing erasing type rewritable read-only memory | |
| CN102117656B (en) | Memory method for nanocrystalline floating gate structure-based multi-value nonvolatile memory | |
| Kim et al. | Effect of field oxide structure on endurance characteristics of NAND flash memory | |
| CN101819978B (en) | Non-contact nano-crystalline split-gate flash memory for sharing word line | |
| CN106653080A (en) | Flash memory and method for improving reliability of flash memory | |
| CN105428270B (en) | A kind of domain structure of test flash memory accumulation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |