CN104619118A - Circuit layout structure and layout method thereof - Google Patents
Circuit layout structure and layout method thereof Download PDFInfo
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- CN104619118A CN104619118A CN201310489142.4A CN201310489142A CN104619118A CN 104619118 A CN104619118 A CN 104619118A CN 201310489142 A CN201310489142 A CN 201310489142A CN 104619118 A CN104619118 A CN 104619118A
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- circuit board
- piezoelectric element
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- copper foil
- depressed area
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Abstract
The invention relates to a circuit layout structure and a layout method thereof. The circuit layout structure comprises a circuit board and at least one piezoelectric element. The circuit board comprises a substrate, a copper foil layer, and a solder mask layer. The copper foil layer is clamped between the substrate and the solder mask layer. The circuit board further has a recessed region which is formed by removing part of the copper foil layer and part of the solder mask layer. The piezoelectric element is electrically arranged on the surface of the circuit board, the position of the piezoelectric element corresponds to the recessed region, and a gap is left between the piezoelectric element and the recessed region of the circuit board. Therefore, no friction is generated between the piezoelectric element and the circuit board, and an effect of noise reduction is achieved.
Description
[technical field]
The present invention relates to a kind of circuit layout structure and layout method thereof, particularly relate to a kind of circuit layout structure and the layout method thereof with the circuit board of ceramic capacitor.
[background technology]
Monolithic ceramic capacitor (Multi-layer Ceramic Capacitor, MLCC) be the one of ceramic capacitor, due to the progress of ceramic membrane stacking, make the content of capacitance more and more higher, and low electric capacity in gradually replacing, the market application of such as electrochemical capacitor and tantalum matter electric capacity, in addition, MLCC directly can be sticked together on circuit boards by SMT, makes production and processing more quick.And along with the miniaturization of electronic product, make MLCC be easy to chip, advantage that volume is little, gradually become the main product of capacitor industry.
The dielectric material of the monolithic ceramic capacitor of general high-capacitance utilizes ferroelectricity (Ferroelectric) material to form, after extra electric field, ceramic body can be caused to have structural distortion, the electrostriction effect (ElectrostrictiveEffect) that this phenomenon causes for piezoelectric effect (Piezoelectric Effect), just can produce noise (Acoustic emission or Noise) with its resonance.And when ceramic capacitor sticks together at circuit board (Printed Circuit Board, PCB) time above, its mechanical energy produced just can be delivered to circuit board by solder joint, now circuit board just produces expansion effect as same loud speaker and produces sharp-pointed noise, also can the damaged slight crack of generation component internal structure when sometimes shaking too violent.
Therefore, for reducing this noise, just dealer is had to develop at the surface of circuit board and the back side in a symmetrical manner, or the structure of a pair ceramic capacitor is installed in spaced mode, make it mutually suppress the resonance that ceramic capacitor is produced on circuit boards, reach the effect reducing noise by this.
But the mounting structure of above-mentioned known ceramic capacitor can reduce the decibel of its noise really, but on the surface that ceramic capacitor must be arranged on circuit board in a symmetrical manner respectively and the back side, or spaced setting.Therefore, the design freedom installing the circuit board of ceramic capacitor just can be subject to great restriction, causes the difficulty on circuit layout design, meanwhile, also need reach with larger circuit board, and then cause the increase of production cost.Dealer is separately had to be the ceramic capacitor selecting frame height foot pad to design, avoid the resonance with circuit board by this, reach the effect reducing noise, but the unit price of this kind of ceramic capacitor is too high, and the restriction that can be subject on height, be not suitable for being arranged on and have on the circuit board of limitation in height.
Therefore, how to make ceramic capacitor can reduce its noise in the work environment, also can not cause the inconvenience in circuit design, reach the demand reduced costs is the problem that the creator of this technical field desires most ardently solution simultaneously.
[summary of the invention]
In view of above problem, the invention provides a kind of circuit layout structure and layout method thereof, thus solve commonly use ceramic capacitor easily and circuit board produce and resonate and send the problem of sharp-pointed noise.
In order to solve the problems of the technologies described above, the invention provides a kind of circuit layout structure, include a circuit board and at least one piezoelectric element, wherein circuit board includes a substrate, a copper foil layer and a welding resisting layer, copper foil layer is stacking on substrate, and welding resisting layer covers copper foil layer, makes copper foil layer be folded between substrate and welding resisting layer, and circuit board also has a depressed area, be remove copper foil layer and welding resisting layer.Piezoelectric element, is electrically arranged on one of circuit board on the surface, and the position of piezoelectric element is corresponding to depressed area, makes between piezoelectric element and the depressed area of circuit board and there is a gap.
Further, the circuit layout structure of the invention described above, wherein piezoelectric element has two weld pads, and piezoelectric element is electrically connected on the surface of circuit board with two weld pads.
Further, the circuit layout structure of the invention described above, wherein piezoelectric element is a monolithic ceramic capacitor (MLCC) or a single-layer type ceramic capacitor.
Further, the circuit layout structure of the invention described above, wherein the profile that formed of depressed area is corresponding with the shape of the bottom surface of piezoelectric element.
The present invention also provides a kind of layout method of circuit structure, and comprising the following steps: provides a circuit board, and circuit board includes a substrate, a copper foil layer and a welding resisting layer, and copper foil layer is folded between substrate and welding resisting layer; Remove copper foil layer and welding resisting layer, and form the surface of a depressed area at circuit board; The surface of at least one piezoelectric element at circuit board is electrically set, and piezoelectric element is corresponding to depressed area, makes between piezoelectric element and the depressed area of circuit board and there is a gap.
Further, the layout method of the circuit structure of the invention described above, wherein electrically arranges the step of piezoelectric element on the surface of circuit board, is the surface that two weld pads that are arranged on piezoelectric element are electrically connected at circuit board.
Effect of the present invention is, circuit layout structure and layout method thereof not only utilize circuit board to have the structural design of depressed area, makes the vibration amplitude of circuit board be unlikely to expand, and then reaches the effect reducing noise.Meanwhile, what the gap between piezoelectric element and depressed area also can provide piezoelectric element to be out of shape is installed with space, make piezoelectric element can not because shape distortion and the circuit board that rubs, the squeal-noise produced because of friction can be prevented, and avoid the damage of piezoelectric element.
Feature for the present invention, implementation and effect, hereby coordinate and to be graphicly described in detail as follows as most preferred embodiment.
[accompanying drawing explanation]
Fig. 1 is the generalized section of the circuit board of the circuit layout structure of one embodiment of the invention.
Fig. 2 is the schematic diagram after the copper foil layer of the circuit board of the circuit layout structure of one embodiment of the invention and welding resisting layer remove.
Fig. 3 is the circuit board of the circuit layout structure of one embodiment of the invention and the decomposing schematic representation of piezoelectric element.
Fig. 4 is the combination schematic diagram that the piezoelectric element of the circuit layout structure of one embodiment of the invention arranges on circuit boards.
Fig. 5 is the flow chart of steps of the circuit structure layout method of one embodiment of the invention.
Primary clustering symbol description:
10 circuit layout structure 110 substrates
100 circuit board 120 copper foil layers
130 welding resisting layer 200 piezoelectric elements
140 depressed area 210 weld pads
150 surperficial G gaps
[embodiment]
Below the present invention, the circuit layout structure 10 of a disclosed embodiment is with the explanation of the circuit layout structure of the circuit board 100 of display card as embodiment, but be not limited with the kenel disclosed by the present embodiment, the person that is familiar with technique, can according to actual design demand or user demand corresponding quantity and the placement position changing the piezoelectric element of circuit layout structure 10 of the present invention.
Chat bright before old, circuit board 100 described in the present embodiment is namely similar to the basic composition commonly using printed circuit board (PCB), can be used as the carrier of electronic building brick equally, and the function of electronic building brick connection is provided, therefore applicant does not add to illustrate at this, is only described in detail for electronic components involved in the present embodiment and structure.
Please refer to the decomposing schematic representation of the circuit layout structure shown in Fig. 1 to Fig. 4 disclosed by one embodiment of the invention and combination schematic diagram, and the flow chart of steps of the circuit structure layout method shown in Fig. 5.The circuit layout structure 10 of the present embodiment includes a circuit board 100 and at least one piezoelectric element 200, wherein circuit board 100 includes substrate 110, copper foil layer 120 and a welding resisting layer 130, copper foil layer 120 is stacking on substrate 110, and welding resisting layer 130 covers copper foil layer 120, copper foil layer 120 is made to be folded between substrate 110 and welding resisting layer 130, as step S101.
Wherein, the material of above-mentioned substrate 110 can be bakelite plate (FR-1), glass mat (FR-4), and various plastic plate (Plastic) etc. is made, but is not confined to this.Copper foil layer 120 is line layer (Pattern), and its material can be cathode copper or calendering copper etc., can be used as the function of turning circuit and ground connection.Welding resisting layer 130 is anti-solder ink layer (Solder mask), its material can be epoxy resin (epoxyresin), pi (polyimide, or polyphenylene oxide (poly phenylene oxide, PPE) etc. PI).
The piezoelectric element 200 of the present embodiment is a ceramic capacitor, such as monolithic ceramic capacitor (MLCC) or single-layer type ceramic capacitor etc., but is not limited with the pattern disclosed by the present invention.Wherein the outer contour shape of piezoelectric element 200 is a cuboid, and piezoelectric element 200 has two weld pads 210 is coated on left and right two end of piezoelectric element 200 respectively, for being electrically connected on circuit board 100.
Illustrate further, the detailed construction of the circuit layout structure 10 of the present embodiment and layout method: as shown in Figure 2, the circuit board 100 of the present embodiment also has a depressed area 140.Step S102 as shown in Figure 5, that the copper foil layer 120 of circuit board 100 part range is removed with welding resisting layer 130, form a depressed area 140 by this on a surface 150 of circuit board 100, the contour shape that wherein depressed area 140 is formed is corresponding with the shape of the bottom surface of piezoelectric element 200.Above-mentioned steps S102 only need adjust the layout scope of copper foil layer 120 and welding resisting layer 130 in the process of circuit layout (LAYOUT), its layout scope is avoided the region of the lower position pre-seting piezoelectric element 200, without the need to again processing, therefore can not increase any cost, also can not affect the function of circuit board 100.
Hold, step S103 as shown in Figure 5, then again piezoelectric element 200 is electrically arranged on the surface 150 of circuit board 100, as shown in Figure 4, the piezoelectric element 200 of the present embodiment is electrically connected with two weld pads 210 surface 150 being combined in circuit board 100, and be electrically connected at circuit board 100, make the corresponding position in depressed area 140, the bottom surface of piezoelectric element 200 simultaneously, make between the depressed area 140 of the bottom surface of piezoelectric element 200 and circuit board 100 and there is a clearance G, making can be spaced apart between the bottom surface of piezoelectric element 200 and circuit board 100, and maintain a segment distance.
It should be noted that the quantity set by piezoelectric element 200 disclosed by the present invention can be 1,2 or multiple, person skilled in the art person can the corresponding configuration quantity changing piezoelectric element 200 of the present invention according to the actual requirements.And above-mentioned piezoelectric element 200 and the combination of circuit board 100, can weld or directly combine with surface mount technology (SMT) by tin cream.
Based on said structure, piezoelectric element 200 materials as ceramic structure of the present embodiment, when extra electric field forms the operational environment of high frequency, piezoelectric element 200 itself can produce shape distortion because of electrostriction effect, produce mechanical vibrations, and this mechanical shock can be delivered on circuit board 100 by two weld pads 210 be electrically connected simultaneously.Now, because of the clearance G that depressed area 140 corresponding below piezoelectric element 200 is formed, the resonance that can effectively suppress circuit board 100 to produce because of piezoelectric element 200, makes the vibration amplitude of circuit board 100 be unlikely to expand, and then reaches the effect reducing noise.Meanwhile, what clearance G also can provide piezoelectric element 200 to be out of shape is installed with space, make piezoelectric element 200 can not because shape distortion and the circuit board 100 that rubs, the squeal-noise produced because of friction can be prevented, and avoid the damage of piezoelectric element 200.
In addition, in application, when circuit layout structure 10 of the present invention is arranged on circuit board 100 with multiple piezoelectric element 200 simultaneously, because circuit board 100 has the structural design of depressed area 140, to be connected except making each piezoelectric element 200 and except part neighbour arranges, the whole height of piezoelectric element 200 also can not increase, therefore not only can the size of significantly reduction circuit plate 100, circuit layout structure 10 also can be made can to meet the requirement of the electronic product with limitation in height, and then improve the applicability of circuit layout structure 10.
Following form is the experimental data of ceramic capacitor (MLCC), be with during ceramic capacitor actual operation on model GV-N660OC-2GD display card the numerical value (having got rid of fan noise value) that measures.
By above-mentioned, data verification after can know and learn, circuit layout structure of the present invention is the display card of above-mentioned numbering D1, D2, its ceramic capacitor, when actual operation, can effectively reduce noise really, and the actual value measured is 17dB, compared to known display card numbering A1, A2, it reduces ratio of level of noise and is approximately the reduction of 10%, therefore, suffices to show that the high frequency noise that circuit layout structure of the present invention really significantly can reduce ceramic capacitor and produces because of mechanical shock.
Embodiment disclosed by the invention described above illustrate and data verification can be known and learns, circuit layout structure of the present invention, by the technological means of the copper foil layer and welding resisting layer that remove circuit board section scope, not only can solve commonly use ceramic capacitor easily and circuit board produce and resonate and send the problem of sharp-pointed noise.
With prior art in comparison, circuit layout structure of the present invention also utilizes multiple piezoelectric element to be connected and part neighbour setting design on circuit boards simultaneously, not only can the size of significantly reduction circuit plate, and the whole height of piezoelectric element also can not increase, make circuit layout structure can meet the requirement of the electronic product with limitation in height, and then improve the applicability of circuit layout structure.
Although embodiments of the invention disclose as mentioned above; so and be not used to limit the present invention; anyly have the knack of relevant art; without departing from the spirit and scope of the present invention; such as work as according to shape, structure, feature and the quantity described in the present patent application scope and can do a little change, therefore scope of patent protection of the present invention must be as the criterion depending on the claim person of defining appended by this specification.
Claims (6)
1. a circuit layout structure, is characterized in that, described circuit layout structure comprises:
One circuit board, includes a substrate, a copper foil layer and a welding resisting layer, and described copper foil layer is folded between described substrate and described welding resisting layer, and described circuit board also has a depressed area, and described depressed area removes described copper foil layer and described welding resisting layer; And
At least one piezoelectric element, is electrically arranged on one of described circuit board on the surface, and the position of described piezoelectric element is corresponding to described depressed area, makes between described piezoelectric element and the described depressed area of described circuit board and there is a gap.
2. circuit layout structure according to claim 1, is characterized in that, described piezoelectric element has two weld pads, and described piezoelectric element is electrically connected on the described surface of described circuit board with described two weld pads.
3. circuit layout structure according to claim 1, is characterized in that, described piezoelectric element is a monolithic ceramic capacitor (MLCC) or a single-layer type ceramic capacitor.
4. circuit layout structure according to claim 1, is characterized in that, the profile that described depressed area is formed is corresponding with the shape of the bottom surface of described piezoelectric element.
5. a layout method for circuit structure, is characterized in that, described layout method comprises the following steps:
There is provided a circuit board, and described circuit board includes a substrate, a copper foil layer and a welding resisting layer, described copper foil layer is folded between described substrate and described welding resisting layer;
Remove described copper foil layer and described welding resisting layer, and form the surface of a depressed area at described circuit board; And
The described surface of at least one piezoelectric element at described circuit board is electrically set, and described piezoelectric element is corresponding to described depressed area, makes between described piezoelectric element and the described depressed area of described circuit board and there is a gap.
6. the layout method of circuit structure according to claim 5, it is characterized in that, electrically arranging the step of described piezoelectric element on the described surface of described circuit board, is the described surface that two weld pads that are arranged on described piezoelectric element are electrically connected at described circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310489142.4A CN104619118A (en) | 2013-10-18 | 2013-10-18 | Circuit layout structure and layout method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310489142.4A CN104619118A (en) | 2013-10-18 | 2013-10-18 | Circuit layout structure and layout method thereof |
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| Publication Number | Publication Date |
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| CN104619118A true CN104619118A (en) | 2015-05-13 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201310489142.4A Pending CN104619118A (en) | 2013-10-18 | 2013-10-18 | Circuit layout structure and layout method thereof |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101102639A (en) * | 2006-07-06 | 2008-01-09 | 三井金属矿业株式会社 | Wiring board and semiconductor device excellent in folding endurance |
| US20080202801A1 (en) * | 2005-06-15 | 2008-08-28 | Imbera Electronics Oy | Circuit Board Structure and Method for Manufacturing a Circuit Board Structure |
| CN101674709A (en) * | 2008-09-08 | 2010-03-17 | 统宝光电股份有限公司 | Layout structure and method for reducing noise generated by flexible printed circuit board |
| CN202262076U (en) * | 2011-10-21 | 2012-05-30 | 京东方科技集团股份有限公司 | Circuit board and display device |
-
2013
- 2013-10-18 CN CN201310489142.4A patent/CN104619118A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080202801A1 (en) * | 2005-06-15 | 2008-08-28 | Imbera Electronics Oy | Circuit Board Structure and Method for Manufacturing a Circuit Board Structure |
| CN101102639A (en) * | 2006-07-06 | 2008-01-09 | 三井金属矿业株式会社 | Wiring board and semiconductor device excellent in folding endurance |
| CN101674709A (en) * | 2008-09-08 | 2010-03-17 | 统宝光电股份有限公司 | Layout structure and method for reducing noise generated by flexible printed circuit board |
| CN202262076U (en) * | 2011-10-21 | 2012-05-30 | 京东方科技集团股份有限公司 | Circuit board and display device |
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Application publication date: 20150513 |