CN104617903A - Programmable gain amplifier-based automatic control device - Google Patents
Programmable gain amplifier-based automatic control device Download PDFInfo
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- CN104617903A CN104617903A CN201510023691.1A CN201510023691A CN104617903A CN 104617903 A CN104617903 A CN 104617903A CN 201510023691 A CN201510023691 A CN 201510023691A CN 104617903 A CN104617903 A CN 104617903A
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Abstract
The invention discloses a programmable gain amplifier (PGA)-based automatic control device. The device comprises a programmable gain amplifier, an analog-digital converter and an SPI (Serial Peripheral Interface) interface, wherein the programmable gain amplifier is used for receiving and amplifying a medium-frequency signal and outputting an analog medium-frequency signal to the analog-digital converter; the analog-digital converter is used for sampling the amplified analog signal to output an eight-digit digital signal to the SPI interface; the SPI interface is used for transmitting the digital signal from the analog-digital converter to a digital baseband, meanwhile receiving a seven-digit PGA control word signal fed back by the digital baseband and transmitting the seven-digit PGA control word signal to the programmable gain amplifier. The conventional automatic gain control is most finished by using a pure analog circuit; a digital-digital hybrid technology is adopted, only the PGA is remained in the analog circuit, so the design difficulty of an analog circuit is greatly reduced.
Description
Technical field
The present invention relates to a kind of based on the auto gain control method of programmable gain amplifier for receiver system, belong to deep-submicron RF CMOS technical field of integrated circuits.
Background technology
Navigation neceiver is made up of radio-frequency front-end and digital baseband two parts.The signal that antenna receives by radio-frequency front-end amplifies, mixing, filtering and analog-to-digital conversion, completes the conversion of radiofrequency signal to baseband signal.Wherein automatic growth control (AutomaticGain Control) module is positioned at the most final stage of radio-frequency front-end, its to need by accurate resonance-amplifier gain to maintain the constant of output amplitude in different strong and weak input signal situation, needs to provide as far as possible large gain variation range to ensure that receiver has enough large dynamic range to process the signal of varying strength simultaneously.
AGC modular structure main at present mainly contains following several:
First is the feed-forward type AGC adopting pure analog circuit to complete, its function completes primarily of power-sensing circuit (i.e. accepted theory, Received Signal Strength Indicator) and variable gain amplifier (VariableGain Amplifier).Intermediate-freuqncy signal inputs to RSSI and VGA simultaneously, and wherein RSSI provides the gain control signal of VGA by the watt level detecting intermediate-freuqncy signal, carrys out the gain size of regulating loop to maintain constant power output.The output signal of VGA is the output of whole AGC module, after analog to digital converter (Analog to Digital Converter), be supplied to digital baseband.Feed-forward type AGC, owing to have employed open loop structure, therefore has the settling time of advantage rapidly, but inevitably has the shortcoming of open loop circuit poor stability.
Second is feedback-type analog closed-loop AGC, and main functional circuit also has loop filter except RSSI and VGA.What be that RSSI detects with the main distinction of feed-forward type is no longer the input signal of VGA but its output signal strength, and compare with a reference level, both error voltages are by producing a control level in order to control the gain of variable gain amplifier after loop filter.Feedback-type AGC has strong robustness, and precision is high, and the advantage that low-frequency noise is lower.But, because loop bandwidth is well below signal bandwidth, so its settling time is long.
3rd is utilize digital signal to control the gain of variable-gain amplifier, and except playing the programmable gain amplifier (Programmable Gain Amplifier) of amplification, other modules all realize in digital field.The output signal of PGA is transformed to digital signal through analog to digital converter, judges signal power at numeric field (base band), and provides digital auto-gain compensative word to the gain of control PGA.Adopt the AGC of numerical model analysis form, the gain of accurate control circuit can be accomplished, and reduce the difficulty of Analog Circuit Design.But just can complete because the process judging signal power at numeric field generally will experience multiple clock, make the settling time of numerical model analysis closed loop AGC longer.
Topmost 2 of AGC loop requires one to be constant output signal power, and one is as far as possible large dynamic range; In addition because navigation neceiver is to the strict demand of resolving time, make to set up the important indicator that the stable time length exported also becomes wherein AGC.Above-mentioned several conventional AGC method for designing existing defects in these three major requirements in various degree.How designing the AGC loop that can be applied to navigation neceiver, the as far as possible short target just becoming research settling time can be had when ensureing great dynamic range and constant output signal power simultaneously.
Summary of the invention
The object of the invention is to solve the problem, proposing a kind of based on the auto gain control method of programmable gain amplifier for receiver system, can be applicable to navigation neceiver and Digital Television.Mainly comprise programmable gain amplifier, analog to digital converter, SPI (Serial Peripheral Interface) interface and baseband processor.Programmable gain amplifier adopts multi-stage cascade pattern, ensure that stable output power and great dynamic range simultaneously.Analog to digital converter adopts 8 forms, in conjunction with the integral algorithm of base band, can judge rapidly that signal is strong and weak, stablizes output time to reach short foundation as far as possible.The control signal that SPI interface is responsible for base band exports passes to programmable gain amplifier quickly and accurately, controls its change in gain.
Based on an automatic control equipment for programmable gain amplifier, comprise programmable gain amplifier, analog to digital converter and SPI interface;
Programmable gain amplifier receiving intermediate frequency signal also amplifies, export analog if signal to analog to digital converter, analog to digital converter is to the analog signal sampling after this amplification, export eight-digit number word signal to SPI interface, SPI interface will be received from the digital data transmission of analog to digital converter to digital baseband, receives seven PGA control word signals of digital baseband feedback simultaneously and is transferred to programmable gain amplifier.
The invention has the advantages that:
(1) traditional automatic growth control is adopt pure analog circuit to complete mostly, present invention employs numerical model analysis technology, in analog circuit, only remains PGA, greatly reduce the design difficulty of analog circuit;
(2) traditional automatic gain control loop is limited to the performance of its variable gain amplifier, dynamic range all can not reach very high, and present invention employs the PGA circuit of the casacade multi-amplifier cascade form of particular design, the dynamic range of whole AGC loop is significantly improved;
(3) present invention employs the AGC loop of feedback form, the gain of PGA circuit simultaneously is accurately controlled by digital control word, ensure that the power stability that agc circuit outputs signal;
(4) present invention employs the method for 8 ADC samplings, the integral and calculating efficiency of digital baseband is significantly improved, adopt the precisely control PGA gain of multidigit control word simultaneously, can ensure once to feed back and PGA output can be made to reach steady state value, substantially reduce whole AGC and set up the stable output time used;
(5) traditional automatic gain control circuit stable output signal and set up stable export swiftness on be difficult to get both, and the present invention can meet this 2 requirements simultaneously, completes to set up stable output signal within the as far as possible short time;
(6) the present invention is convenient to integrated, is applicable to Portable movable terminal.
Accompanying drawing explanation
Fig. 1 is that the present invention is a kind of based on the structured flowchart of programmable gain amplifier for the auto gain control method of receiver system;
Fig. 2 is the structured flowchart of the present invention's programmable gain amplifier used;
Fig. 3 is the circuit structure of fixed gain level in the present invention's programmable gain amplifier used;
Fig. 4 is the circuit structure of variable gain stages in the present invention's programmable gain amplifier used;
Fig. 5 is the concrete structure block diagram of the present invention's digital baseband used.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.
A kind of automatic control equipment based on programmable gain amplifier of the present invention, as shown in Figure 1, comprises programmable gain amplifier 1, analog to digital converter 2 and SPI interface 3.
Programmable gain amplifier 1 receiving intermediate frequency signal also amplifies, export analog if signal to analog to digital converter 2, analog to digital converter 2 is to the analog signal sampling after this amplification, export eight-digit number word signal to SPI interface 3, SPI interface 3 will be received from the digital data transmission of analog to digital converter 2 to digital baseband, receives seven PGA control word signals of digital baseband feedback simultaneously and is transferred to programmable gain amplifier 1.
As shown in Figure 2, programmable gain amplifier (Programmable Gain Amplifier is called for short PGA) 1 comprises four fixed gain amplifiers (Amplifier1 ~ 4), a variable gain amplifier (Amplifier5) and exports buffer stage (buffer).
Amplifier1 ~ 4 are fixed gain amplifiers of gilbert's structure, and the gain of its correspondence is respectively 24dB, 12dB, 6dB and-12dB, are the main gain units of whole PGA.
Whole PGA carrys out ride gain size by seven bit digital control words, and whether the work of front four control word control amplifier Amplifier1 ~ 4, the yield value of rear three control word control amplifier Amplifier5 after decoder.The highest-gain of whole PGA is 24dB+12dB+6dB+5dB=47dB, and lowest gain is-12dB, and dynamic range reaches 59dB.
Wherein, Amplifier1 and Amplifier2 two positive gaining amplifiers are input and output cascade structure, and by the control of control word to switching circuit, can all not work, any one works independently or two each and every one to work simultaneously, provides different postiive gains.Amplifier4 is in parallel with the cascade structure of above-mentioned two amplifiers, provides negative gain, and via the control of control word to switching circuit, input signal only can from leading up to Amplifier1 ~ 2 or Amplifier4.Cascade Amplifier3, Amplifier5 and buffer circuit in order again after parallel-connection structure.Wherein Amplifier3 fixedly provides 6db postiive gain, by the control of control word to switching circuit, has work and does not work two states, providing 6db and 0db gain respectively.Amplifier5 is the variable gain amplifier based on programmable load, can by the direct ride gain size of control word, with 1dB step change between 0-5dB, to complete fine gains function.Buffer exports buffer stage, in order to improve the load capacity of whole PGA circuit and to stablize output signal power, completes the function that differential signal is converted to single-ended signal simultaneously.
The main structure for amplifying of gilbert of fixed gain amplifier (Amplifier1 ~ 4) comprises biasing circuit, amplifying circuit, load circuit and biasing circuit of load, as shown in Figure 3.
Biasing circuit is transistor M
0, by the direct voltage V of input
biasworking direct current is provided, the direct ground connection of source electrode, grid input control voltage V to amplifying return circuit
bias, drain electrode connects differential pair the first transistor M
1with transistor seconds M
2source electrode, for it provides operating current.
Amplifying circuit comprises three differential pairs, and first is the first transistor M
1with transistor seconds M
2, second be third transistor M
3with the 4th transistor M
4, the 3rd be the 5th transistor M
5with the 6th transistor M
6.The gilbert circuit of these three differential pair composition standards, input signal V
in+, V
in-by the first transistor M
1with transistor seconds M
2grid enter, the first transistor M
1with transistor seconds M
2source electrode link together and with bias transistor M
0drain electrode be connected, the first transistor M
1drain electrode and differential pair third transistor M
3, the 4th transistor M
4source electrode be connected, transistor seconds M
2drain electrode and differential pair the 5th transistor M
5, the 6th transistor M
6source electrode be connected, simultaneously third transistor M
3with the 6th transistor M
6grid, the 4th transistor M
4with the 5th transistor M
5grid to be connected to together and by external input voltage signal, third transistor M
3with the 5th transistor M
5drain electrode be connected, the 4th transistor M
4with the 6th transistor M
6drain electrode be connected as output signal two ports, complete enlarging function by these six transistors.
Load circuit comprises the 7th transistor M
7, the 8th transistor M
8, the 9th transistor M
9, the tenth transistor M
10, the first resistance R
1with the second resistance R
2, wherein the 7th transistor M
7, the 8th transistor M
8, the 9th transistor M
9, the tenth transistor M
10composition active load, serves the effect determining gain in amplifying circuit.7th transistor M
7, the 8th transistor M
8, the 9th transistor M
9, the tenth transistor M
10source electrode link together and supply voltage V
dDbe connected; Grid links together and biasing circuit of load the tenth two-transistor M
12, the 14 transistor M
14drain electrode be connected.7th transistor M
7, the 8th transistor M
8drain electrode and third transistor M
3, the 5th transistor M
5drain electrode and the first resistance R
1one end be connected as output signal one end; 9th transistor M
9, the tenth transistor M
10drain electrode and the 4th transistor M
4, the 6th transistor M
6drain electrode and the second resistance R
2one end be connected as output signal the other end.First resistance R
1with the second resistance R
2other one end to link together and to the 11 transistor M in biasing circuit of load
11grid provides voltage.
Biasing circuit of load comprises bias transistor the 15 transistor M
15, differential pair transistors the 11 transistor M
11, the tenth two-transistor M
12with active load transistor the 13 transistor M
13, the 14 transistor M
14, biasing circuit of load is also a simple differential amplifier circuit simultaneously, provides grid voltage in order to give the active load of circuit.Wherein the 15 transistor M
15the direct ground connection of source electrode, grid input control voltage V
bias, drain electrode connects differential pair the 11 transistor M
11with the tenth two-transistor M
12source electrode, for it provides operating current.11 transistor M
11grid and the first resistance R
1with the second resistance R
2connect, drain electrode and the 13 transistor M
13source electrode, grid and the 14 transistor M
14grid be connected.Tenth two-transistor M
12grid connect external voltage V
ref, drain electrode and the 14 transistor M
14drain electrode be connected, and connect the 7th transistor M
7, the 8th transistor M
8, the 9th transistor M
9, the tenth transistor M
10grid.13 transistor M
13, the 14 transistor M
14source electrode link together and supply voltage V
dDbe connected.
As shown in Figure 4, variable gain amplifier (Amplifier5) is the amplifying circuit based on programmable load, is made up of differential amplifier circuit and variable load structure.Differential amplifier circuit is by bias current mirror circuit the first transistor M
1, transistor seconds M
2with differential pair third transistor M
3, the 4th transistor M
4composition, the first transistor M
1with transistor seconds M
2grid voltage V
biasinputted by outside, source electrode is connected and ground connection, and drain electrode connects third transistor M respectively
3with the 4th transistor M
4source electrode, and the 13 resistance R
13two ends.Third transistor M
3with the 4th transistor M
4grid connect the two ends of input signal respectively, drain electrode connects variable load.The primary structure of variable load controls conducting whether Resistor Array Projector (the first ~ ten resistance R by ten by logic switch
1~ R
10), by the 5th, six, seven, eight transistor M
5, M
6, M
7, M
8with the 11,12 resistance R
11, R
12the stable output module of composition, and by the 9th ~ the 16 transistor M
9~ M
16the active load of composition.First resistance R
1, the 3rd resistance R
3, the 5th resistance R
5, the 7th resistance R
7, the 9th resistance R
9direct cascade, and every cascade one-level is all in parallel with a switching circuit.One end (first resistance R of whole cascade structure
1one end) connect third transistor M
3drain electrode, the 9th transistor M
9drain electrode and the 11 transistor M
11, the tenth two-transistor M
12grid; The other end (the 9th resistance R of cascade structure
9one end) connect the 7th transistor M
7drain electrode, the tenth transistor M
10drain electrode, the 11 resistance R
11, as the port that whole amplifier exports.9th transistor M
9with the tenth transistor M
10grid be connected, by external voltage V
bias3control, both source electrode respectively with the 11 transistor M
11with the tenth two-transistor M
12drain electrode be connected.11 transistor M
11with the tenth two-transistor M
12source electrode and supply voltage V
dDbe connected.Second resistance R
2, the 4th resistance R
4, the 6th resistance R
6, the 8th resistance R
8, the tenth resistance R
10direct cascade, and every cascade one-level is all in parallel with a switching circuit.One end (second resistance R of whole cascade structure
2one end) connect the 4th transistor M
4drain electrode, the 14 transistor M
14drain electrode and the 15 transistor M
15, the 16 transistor M
16grid; The other end (the tenth resistance R of cascade structure
10one end) connect the 8th transistor M
8drain electrode, the 13 transistor M
13drain electrode, the 12 resistance R
12, as another port that whole amplifier exports.13 transistor M
13with the 14 transistor M
14grid be connected, by external voltage V
bias3control, both source electrode respectively with the 15 transistor M
15with the 16 transistor M
16drain electrode be connected.15 transistor M
15with the 16 transistor M
16source electrode and supply voltage V
dDbe connected.5th transistor M
5with the 6th transistor M
6the direct ground connection of source electrode, grid be connected and with the 11 resistance R
11with the 12 resistance R
12one end connect, drain electrode respectively connect the 7th transistor M
7with the 8th transistor M
8source electrode.7th transistor M
7with the 8th transistor M
8grid connect External Control Voltage V
bias2, drain electrode is the output of whole amplifier.The folding of rear three each switches of controlling resistance array after decoder of digital control word, thus determine the size of amplifier load and the gain of final control amplifier between 0 ~ 5dB with 1dB step change.
As shown in Figure 2, the input signal of programmable gain amplifier, behind Amplifier1 ~ 2 or Amplifier4 two-way Zhong mono-tunnel, then through the amplification of Amplifier3 and Amplifier5, exports after finally stable by buffer.
The gain of described programmable gain amplifier 1 and output signal power can be enough stable, maintain gain and output signal constant when control word signal is constant.
Analog to digital converter 2 is 8-bit High-Speed analog to digital converter (Analog to Digital Converter, ADC), the two-way communication of described SPI interface 3 load digital-to-analogue, by the signal transmission after analog to digital converter sampling to digital baseband 4, digital baseband completes integral and calculating, judge the power of sampled signal and calculate and produce the control word of programmable gain amplifier, afterwards SPI by control word back transfer to programmable gain amplifier.
As shown in Figure 5, the sampled signal of ADC enters digital baseband through SPI interface 3, and this sampled signal is the real output signal power A of current PGA.The power B that PGA should export when digital baseband inner first register memory systems steady operation, two signals, through subtracter computing, draw the difference of theoretical power output and real output, that is the gain of PGA should changing value C=B-A.This gain knots modification and yield value D (being stored by the second register) are before through adder computing, namely theoretical gain value E=D+C is now obtained, theoretical gain value E mono-tunnel transcoding after decoder is that the control word signal of PGA exports to PGA to regulate gain via SPI interface, another road is then stored, as the yield value D differentiated next time by the second register.The feature of algorithm of the present invention can provide corresponding PGA control word in a computing cycle, do not need iterative cycles to calculate, save locking time.
The invention discloses a kind of based on the auto gain control method of programmable gain amplifier for receiver system, great dynamic range, high output stability can be realized simultaneously and shortly set up stabilization time.And circuit design is simple, can be widely used in navigation neceiver.
Claims (6)
1., based on an automatic control equipment for programmable gain amplifier, comprise programmable gain amplifier, analog to digital converter and SPI interface;
Programmable gain amplifier receiving intermediate frequency signal also amplifies, export analog if signal to analog to digital converter, analog to digital converter is to the analog signal sampling after this amplification, export eight-digit number word signal to SPI interface, SPI interface will be received from the digital data transmission of analog to digital converter to digital baseband, receives seven PGA control word signals of digital baseband feedback simultaneously and is transferred to programmable gain amplifier.
2. a kind of automatic control equipment based on programmable gain amplifier according to claim 1, described programmable gain amplifier comprises four fixed gain amplifiers, a variable gain amplifier and exports buffer stage;
Four fixed gain amplifiers are respectively Amplifier1, Amplifier2, Amplifier3, Amplifier4, all adopt gilbert's structure, variable gain amplifier is Amplifier5, exporting buffer stage is buffer circuit, ride gain size is carried out by seven bit digital control words, whether the work of front four control word control amplifier Amplifier1 ~ 4, the yield value of rear three control word control amplifier Amplifier5 after decoder;
Amplifier1 and Amplifier2 two positive gaining amplifiers are input and output cascade structure, and by the control of control word to switching circuit, can all not work, any one works independently or two each and every one to work simultaneously, provides different postiive gains; Amplifier4 is in parallel with the cascade structure of above-mentioned two amplifiers, provides negative gain, and via the control of control word to switching circuit, input signal is from leading up to Amplifier1 ~ 2 or Amplifier4; Cascade Amplifier3, Amplifier5 and buffer circuit in order again after parallel-connection structure.
3. a kind of automatic control equipment based on programmable gain amplifier according to claim 2, described fixed gain amplifier comprises biasing circuit, amplifying circuit, load circuit and biasing circuit of load;
Biasing circuit is transistor M
0, by the direct voltage V of input
biasworking direct current is provided, the direct ground connection of source electrode, grid input control voltage V to amplifying return circuit
bias, drain electrode connects differential pair the first transistor M
1with transistor seconds M
2source electrode, for it provides operating current;
Amplifying circuit comprises three differential pairs, and first is the first transistor M
1with transistor seconds M
2, second be third transistor M
3with the 4th transistor M
4, the 3rd be the 5th transistor M
5with the 6th transistor M
6; The gilbert circuit of these three differential pair composition standards, input signal V
in+, V
in-by the first transistor M
1with transistor seconds M
2grid enter, the first transistor M
1with transistor seconds M
2source electrode link together and with bias transistor M
0drain electrode be connected, the first transistor M
1drain electrode and differential pair third transistor M
3, the 4th transistor M
4source electrode be connected, transistor seconds M
2drain electrode and differential pair the 5th transistor M
5, the 6th transistor M
6source electrode be connected, simultaneously third transistor M
3with the 6th transistor M
6grid, the 4th transistor M
4with the 5th transistor M
5grid to be connected to together and by external input voltage signal, third transistor M
3with the 5th transistor M
5drain electrode be connected, the 4th transistor M
4with the 6th transistor M
6drain electrode be connected as output signal two ports;
Load circuit comprises the 7th transistor M
7, the 8th transistor M
8, the 9th transistor M
9, the tenth transistor M
10, the first resistance R
1with the second resistance R
2, wherein the 7th transistor M
7, the 8th transistor M
8, the 9th transistor M
9, the tenth transistor M
10composition active load; 7th transistor M
7, the 8th transistor M
8, the 9th transistor M
9, the tenth transistor M
10source electrode link together and supply voltage V
dDbe connected; Grid links together and biasing circuit of load the tenth two-transistor M
12, the 14 transistor M
14drain electrode be connected; 7th transistor M
7, the 8th transistor M
8drain electrode and third transistor M
3, the 5th transistor M
5drain electrode and the first resistance R
1one end be connected as output signal one end; 9th transistor M
9, the tenth transistor M
10drain electrode and the 4th transistor M
4, the 6th transistor M
6drain electrode and the second resistance R
2one end be connected as output signal the other end; First resistance R
1with the second resistance R
2other one end to link together and to the 11 transistor M in biasing circuit of load
11grid provides voltage.
Biasing circuit of load comprises bias transistor the 15 transistor M
15, differential pair transistors the 11 transistor M
11, the tenth two-transistor M
12with active load transistor the 13 transistor M
13, the 14 transistor M
14, biasing circuit of load is also a simple differential amplifier circuit simultaneously, provides grid voltage in order to give the active load of circuit; Wherein the 15 transistor M
15the direct ground connection of source electrode, grid input control voltage V
bias, drain electrode connects differential pair the 11 transistor M
11with the tenth two-transistor M
12source electrode, for it provides operating current; 11 transistor M
11grid and the first resistance R
1with the second resistance R
2connect, drain electrode and the 13 transistor M
13source electrode, grid and the 14 transistor M
14grid be connected; Tenth two-transistor M
12grid connect external voltage V
ref, drain electrode and the 14 transistor M
14drain electrode be connected, and connect the 7th transistor M
7, the 8th transistor M
8, the 9th transistor M
9, the tenth transistor M
10grid; 13 transistor M
13, the 14 transistor M
14source electrode link together and supply voltage V
dDbe connected.
4. a kind of automatic control equipment based on programmable gain amplifier according to claim 2, described variable gain amplifier comprises differential amplifier circuit and variable load structure, and differential amplifier circuit is by bias current mirror circuit the first transistor M
1, transistor seconds M
2with differential pair third transistor M
3, the 4th transistor M
4composition, the first transistor M
1with transistor seconds M
2grid voltage V
biasinputted by outside, source electrode is connected and ground connection, and drain electrode connects third transistor M respectively
3with the 4th transistor M
4source electrode, and the 13 resistance R
13two ends; Third transistor M
3with the 4th transistor M
4grid connect the two ends of input signal respectively, drain electrode connects variable load; The primary structure of variable load controls conducting whether Resistor Array Projector, by the 5th, six, seven, eight transistor M by ten by logic switch
5, M
6, M
7, M
8with the 11,12 resistance R
11, R
12the stable output module of composition, and by the 9th ~ the 16 transistor M
9~ M
16the active load of composition; First resistance R
1, the 3rd resistance R
3, the 5th resistance R
5, the 7th resistance R
7, the 9th resistance R
9direct cascade, and every cascade one-level is all in parallel with a switching circuit; One end of whole cascade structure connects third transistor M
3drain electrode, the 9th transistor M
9drain electrode and the 11 transistor M
11, the tenth two-transistor M
12grid; The other end of cascade structure connects the 7th transistor M
7drain electrode, the tenth transistor M
10drain electrode, the 11 resistance R
11, as the port that whole amplifier exports; 9th transistor M
9with the tenth transistor M
10grid be connected, by external voltage V
bias3control, both source electrode respectively with the 11 transistor M
11with the tenth two-transistor M
12drain electrode be connected; 11 transistor M
11with the tenth two-transistor M
12source electrode and supply voltage V
dDbe connected; Second resistance R
2, the 4th resistance R
4, the 6th resistance R
6, the 8th resistance R
8, the tenth resistance R
10direct cascade, and every cascade one-level is all in parallel with a switching circuit; One end of whole cascade structure connects the 4th transistor M
4drain electrode, the 14 transistor M
14drain electrode and the 15 transistor M
15, the 16 transistor M
16grid; The other end of cascade structure connects the 8th transistor M
8drain electrode, the 13 transistor M
13drain electrode, the 12 resistance R
12, as another port that whole amplifier exports; 13 transistor M
13with the 14 transistor M
14grid be connected, by external voltage V
bias3control, both source electrode respectively with the 15 transistor M
15with the 16 transistor M
16drain electrode be connected; 15 transistor M
15with the 16 transistor M
16source electrode and supply voltage V
dDbe connected; 5th transistor M
5with the 6th transistor M
6the direct ground connection of source electrode, grid be connected and with the 11 resistance R
11with the 12 resistance R
12one end connect, drain electrode respectively connect the 7th transistor M
7with the 8th transistor M
8source electrode; 7th transistor M
7with the 8th transistor M
8grid connect External Control Voltage V
bias2, drain electrode is the output of whole amplifier.
5. a kind of automatic control equipment based on programmable gain amplifier according to claim 1, described analog to digital converter is 8-bit High-Speed analog to digital converter ADC, the two-way communication of SPI interface load digital-to-analogue, by the signal transmission after analog to digital converter sampling to digital baseband, digital baseband completes integral and calculating, judge the power of sampled signal and calculate and produce the control word of programmable gain amplifier, afterwards SPI by control word back transfer to programmable gain amplifier.
6. a kind of automatic control equipment based on programmable gain amplifier according to claim 1, the sampled signal of described analog to digital converter ADC enters digital baseband through SPI interface, and this sampled signal is the real output signal power A of current PGA; The power B that PGA should export when digital baseband inner first register memory systems steady operation, two signals, through subtracter computing, draw the difference of theoretical power output and real output, that is the gain of PGA should changing value C=B-A; This gain knots modification with before by the second register gain value D through adder computing, namely theoretical gain value E=D+C is now obtained, theoretical gain value E mono-tunnel transcoding after decoder is that the control word signal of PGA exports to PGA to regulate gain via SPI interface, another road is then stored, as the yield value D differentiated next time by the second register.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105356897A (en) * | 2015-10-18 | 2016-02-24 | 中国电子科技集团公司第十研究所 | Wireless receiving front-end containing asymmetrical adjustment speed AGC controller |
| CN106207397A (en) * | 2016-09-26 | 2016-12-07 | 江苏天安智联科技股份有限公司 | Vehicle-mounted 4G has resource integrated gain antenna |
| CN106788495A (en) * | 2016-11-25 | 2017-05-31 | 北京航空航天大学 | A kind of AGC system and method for numerical model analysis SOC |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105356897A (en) * | 2015-10-18 | 2016-02-24 | 中国电子科技集团公司第十研究所 | Wireless receiving front-end containing asymmetrical adjustment speed AGC controller |
| CN106207397A (en) * | 2016-09-26 | 2016-12-07 | 江苏天安智联科技股份有限公司 | Vehicle-mounted 4G has resource integrated gain antenna |
| CN106207397B (en) * | 2016-09-26 | 2021-07-09 | 江苏天安智联科技股份有限公司 | Vehicle-mounted 4G active integrated gain antenna |
| CN106788495A (en) * | 2016-11-25 | 2017-05-31 | 北京航空航天大学 | A kind of AGC system and method for numerical model analysis SOC |
| CN113490941A (en) * | 2019-02-28 | 2021-10-08 | 硅谷介入有限公司 | Analog computer with variable gain |
| CN110554389A (en) * | 2019-09-26 | 2019-12-10 | 中国电子科技集团公司第三十八研究所 | 77GHz radar receiver circuit for improving fluctuation of wide-temperature working gain |
| CN110554389B (en) * | 2019-09-26 | 2024-03-15 | 中国电子科技集团公司第三十八研究所 | 77GHz radar receiver circuit for improving wide-temperature working gain fluctuation |
| CN112886934A (en) * | 2021-01-11 | 2021-06-01 | 新郦璞科技(上海)有限公司 | Programmable gain amplifier with adjustable input and output voltage |
| CN112886934B (en) * | 2021-01-11 | 2024-03-19 | 新郦璞科技(上海)有限公司 | Programmable gain amplifier with adjustable input/output voltage |
| CN114301479A (en) * | 2022-01-18 | 2022-04-08 | 青岛联众芯云科技有限公司 | Power line carrier communication receiver and control method thereof |
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