CN104617077A - Package substrate and integrated circuit chip - Google Patents
Package substrate and integrated circuit chip Download PDFInfo
- Publication number
- CN104617077A CN104617077A CN201510038389.3A CN201510038389A CN104617077A CN 104617077 A CN104617077 A CN 104617077A CN 201510038389 A CN201510038389 A CN 201510038389A CN 104617077 A CN104617077 A CN 104617077A
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- China
- Prior art keywords
- setting area
- zhi district
- packaging
- base plate
- solder mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The embodiment of the invention provides a package substrate and an integrated circuit chip. The package substrate includes: a substrate layer and the solder layer, the solder layer is disposed in the upper portion of the substrate layer; the solder resist layer includes set crystal region formed refers welding windows and protected areas; each welding refers to the area is provided with a corresponding conductive hole; the contact hole is a through hole on the substrate layer; the protective zone of the window recess is formed on the solder resist layer, and the protective zone is located by said bonding fingers between the region and the crystalline region is set to prevent overflow from the set adhesive bonding area to the bonding fingers area, including the aforementioned integrated circuit chip package substrate through the solder resist layer, welding refers to the region and the intermediate region is set crystal windows form a groove, can effectively prevent the adhesive used to hold the overflow of die bonding fingers area to improve the use of the package substrate chip package good rate.
Description
Technical field
The embodiment of the present invention relates to integrated circuit technique, particularly relates to a kind of base plate for packaging and integrated circuit (IC) chip.
Background technology
Integrated circuit (IC) chip is a kind of microelectronic device or parts.Adopt certain technique, the elements such as transistor, resistance, electric capacity and inductance required in a circuit are produced on a fritter or a few fritter semiconductor wafer or medium substrate, become the microstructure with required circuit function, be widely used in all trades and professions.Wherein, and routing bonding (English: wire bond, be called for short: W/B) packaged type is comparatively conventional in ic chip package.
Fig. 1 is the profile of integrated circuit (IC) chip conventional in prior art, as shown in Figure 1, this chip comprises base plate for packaging, adhesive and naked crystalline substance, packaged type in Fig. 1 is W/B packaged type, base plate for packaging comprises substrate layer 11 (core material or preimpregnation material and other substrate layer structures), Han Zhi district 13, solder mask 12 are (English: solder mask, be called for short: the crystalline setting area 14 S/M) and on solder mask 12, the substrate layer 11 below Han Zhi district 13 has conductive hole 15.In integrating process, naked brilliant 16 (die) are fixed on by adhesive 17 (epoxy) bonding on the crystalline setting area 14 of base plate for packaging (substrate), then by bonding line 18 (bonding wire), the Han Zhi district 13 that the naked pin of brilliant 16 and S/M uplifting window are formed is coupled together, thus form effective electrically connect of naked brilliant 16 and base plate for packaging.Then by each layer interconnect traces and the undermost soldered ball (solder ball) of substrate, draw the electrical interface that chip is external, complete integrated circuit (IC) chip.
But, according to the common base plate for packaging design of Fig. 1, during the close together in its naked Jing Yuhanzhi district, in encapsulation process, when the pin and Han Zhi district that are connected with the naked crystalline substance of bonding line being welded by scolding tin, easily generation adhesive is heated and is spilled over to Han Zhi district, space, effective Han Zhi district is diminished, scolding tin can not effectively fill Han Zhi district, and easily generation rosin joint or not prison welding admittedly, cause the acceptance rate of the encapsulation of integrated circuit (IC) chip lower.
Summary of the invention
The invention provides a kind of base plate for packaging and integrated circuit (IC) chip, for solving in prior art, base plate for packaging designs, during the close together in its naked Jing Yuhanzhi district, during by scolding tin connecting key zygonema two sections, easily there is adhesive and be spilled over to Han Zhi district, space, effective Han Zhi district is diminished, scolding tin can not effectively be filled in Han Zhi district, and generation rosin joint or not prison welding admittedly, cause the problem that the acceptance rate of ic chip package is lower.
First aspect present invention provides a kind of base plate for packaging, comprising: substrate layer and solder mask, and described solder mask is arranged on the top of described substrate layer; Described solder mask comprises crystalline setting area, window the Han Zhi district and protection zone that are formed; Each Han Zhi district correspondence is provided with conductive hole; Described conductive hole is be arranged on the through hole on described substrate layer;
Described protection zone is the groove formed at described solder mask uplifting window, and described protection zone is between described Han Zhi district and described crystalline setting area, overflows to described Han Zhi district from described crystalline setting area for preventing adhesive.
In conjunction with first aspect, in the first possible execution mode of first aspect, described protection zone is included in the annular recess around described crystalline setting area that the solder mask uplifting window between described Han Zhi district and described crystalline setting area is formed.
In conjunction with the first possible execution mode of first aspect, in the execution mode that the second of first aspect is possible, the number of described annular recess is at least one.
Second aspect present invention provides a kind of integrated circuit (IC) chip, comprising: naked crystalline substance, adhesive and base plate for packaging;
Described base plate for packaging comprises substrate layer and solder mask, and described solder mask is arranged on the top of described substrate layer; Described solder mask comprises crystalline setting area, window the Han Zhi district and protection zone that are formed; Each Han Zhi district correspondence is provided with conductive hole; Described conductive hole is be arranged on the through hole on described substrate layer; Described naked crystalline substance is fixed on the described crystalline setting area of described base plate for packaging by described adhesive;
Wherein, described protection zone is the groove formed at described solder mask uplifting window, and described protection zone is between described Han Zhi district and described crystalline setting area, overflows to described Han Zhi district from described crystalline setting area for preventing adhesive.
In conjunction with second aspect, in the first possible execution mode of second aspect, also comprise at least identical with described Han Zhi district quantity bonding line, described bonding line is for connecting the pin of described naked crystalline substance and corresponding Han Zhi district.
In conjunction with the first possible execution mode of second aspect or second aspect; in the execution mode that the second of second aspect is possible, described protection zone is included in the annular recess around described crystalline setting area that the solder mask uplifting window between described Han Zhi district and described crystalline setting area is formed.
In conjunction with the execution mode that the second of second aspect is possible, in the third possible execution mode of second aspect, the number of described annular recess is at least one.
In conjunction with second aspect, second aspect first to the possible execution mode of any one in the third, in the 4th kind of possible execution mode of second aspect, also comprise: mold structure, described mold structure is fill with the profiled part of packaged by plastic on described naked crystalline substance and described base plate for packaging.
In conjunction with second aspect, second aspect first to the possible execution mode of any one in the third; in the 5th kind of possible execution mode of second aspect; also comprise: add a cover structure, described in add a cover the operator guards of construction packages outside described naked crystalline substance and described base plate for packaging.
Base plate for packaging provided by the invention and integrated circuit (IC) chip; protection zone is formed by the solder mask uplifting window at base plate for packaging; the position of this protection zone is between Han Zhi district and crystalline setting area; in the process of integrated circuit; when adhesive for fixing naked crystalline substance overflows; protection zone can effectively prevent adhesive Yi Zhihanzhi district from covering Han Zhi district, and the region in maintenance Han Zhi district can be complete for welding, effectively improves the acceptance rate of ic chip package.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, introduce doing one to the accompanying drawing used required in embodiment or description of the prior art simply below, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the profile of integrated circuit (IC) chip conventional in prior art;
Fig. 2 a is the profile of base plate for packaging embodiment one of the present invention;
Fig. 2 b is the vertical view of base plate for packaging embodiment one of the present invention;
Fig. 3 is the vertical view of base plate for packaging embodiment two of the present invention;
Fig. 4 is the profile of base plate for packaging embodiment three of the present invention;
Fig. 5 is the profile of base plate for packaging embodiment four of the present invention;
Fig. 6 a is the profile of the local of integrated circuit (IC) chip embodiment one of the present invention;
Fig. 6 b is the vertical view of the local of integrated circuit (IC) chip embodiment one of the present invention.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Fig. 2 a is the profile of base plate for packaging embodiment one of the present invention; Fig. 2 b is the vertical view of base plate for packaging embodiment one of the present invention, and as shown in Fig. 2 a, Fig. 2 b, the structure of new base plate for packaging 20 provided by the invention mainly comprises: substrate layer 21 and solder mask 22, and described solder mask 22 is arranged on the top of described substrate layer 21; Described solder mask 22 comprises crystalline setting area 221, window the Han Zhi district 222 and protection zone 223 that are formed; Each Han Zhi district 222 correspondence is provided with conductive hole 211; Described conductive hole 211 is for being arranged on the through hole on described substrate layer 21;
Described protection zone 223 is the groove formed at described solder mask 22 uplifting window; and described protection zone 223 is between described Han Zhi district 222 and described crystalline setting area 221; overflow to described Han Zhi district 222 for preventing adhesive from described crystalline setting area 221; the Han Zhi district 222 having offered the base plate for packaging of protection zone 223 in addition can shorten with the distance of crystalline setting area 221; not only space is saved; BD line can also be shortened, reduce spurious impedance.
In the present embodiment, substrate layer 21 comprises preimpregnation material (Prepreg material) or core material (core material), and other substrate layer structures, same as the prior art, does not indicate in detail in figure.
Scribble solder mask 22 above substrate layer 21, Main Function is that the part preventing from being sealed on is soldered, such as: Reflow Soldering realizes by solder mask.Window in the bond pad locations of solder mask 22, forming district of Han Zhi district 222, Han Zhi 222 is exactly for being carried out with the pin of naked crystalline substance the region that is electrically connected by bonding line on substrate.Crystalline setting area 221 is the region fixing naked crystalline substance in integrating process.
To window between each Han Zhi district 222 and crystalline setting area 221 in this programme formation groove, as protection zone 223, intercept in integrating process the adhesive Yi Zhihanzhi district 222 fixing naked crystalline substance, improve integrated quality.
In addition; preventing between the crystalline setting area 221 of naked crystalline substance and Han Zhi district 222, planning suitable protection zone 223; profile forms corresponding recessed groove protection zone 223 significantly as seen; the i.e. spilling of adhesive in available buffer subsequent encapsulating process process; reduce the possibility of adhesive flow to Han Zhi district, thus make the crystalline setting area of the naked crystalline substance of substrate and the distance in Han Zhi district can shorten or in packaging technology, adopt thicker adhesive.
In the present embodiment, the number of protection zone 223 does not limit, and can window as required and form one or more protection zone 223, do not affect circuit function in the position of correspondence.
The base plate for packaging that the present embodiment provides; by forming protection zone at solder mask uplifting window; the position of this protection zone is between Han Zhi district and crystalline setting area; in the process of integrated circuit; when adhesive for fixing naked crystalline substance overflows; protection zone can effectively prevent adhesive Yi Zhihanzhi district from covering Han Zhi district, and the region in maintenance Han Zhi district can be complete for welding, effectively improves the acceptance rate of ic chip package.
Fig. 3 is the vertical view of base plate for packaging embodiment two of the present invention; as shown in Figure 3; on the basis of above-described embodiment, described protection zone 223 be included in that solder mask 22 uplifting window between described Han Zhi district 222 and described crystalline setting area 221 is formed, around the annular recess of described crystalline setting area 221.
As shown in Figure 3; protection zone 223 in this embodiment is the grooves of the ring-type that couples together; namely between crystalline setting area 221 and Han Zhi district 222, plan that solder mask is windowed district; directly be linked to be a ring around crystalline setting area; form corresponding recessed groove protection ring; the spilling of adhesive in subsequent encapsulating process process can be cushioned further, prevent at adhesive from the Yi Zhihanzhi district, interval between protection zone, reduce the possibility of adhesive flow to Han Zhi district further.
Fig. 4 is the profile of base plate for packaging embodiment three of the present invention, and on the basis of the embodiment shown in above-mentioned Fig. 3, the number of the described annular recess of this protection zone 223 is at least one.Can select multiple according to actual conditions, two annular recess as shown in Figure 4.
In encapsulation process; in order to improve the reliability of encapsulation; more adhesive (namely adhesive phase is thicker) can be used to fix naked crystalline substance; therefore in order to further prevent adhesive Yi Zhihanzhi district 222, can window between Han Zhi district 222 and crystalline setting area 221 two grooves or plural annular recess are protected.
Between crystalline setting area 221 and Han Zhi district 222, plan that solder mask is windowed annular recess; this annular recess can comprise two or more circle; form corresponding multilayer recessed groove protection ring; the spilling of adhesive in subsequent encapsulating process process can be cushioned to greatest extent, reduce the possibility of adhesive flow to Han Zhi district further.
On the basis of the multiple implementation shown in above-mentioned Fig. 2 a to figure Fig. 4, Fig. 5 is the profile of base plate for packaging embodiment four of the present invention; As shown in Figure 5, in the present embodiment, the distance in crystalline setting area 221 and Han Zhi district 222 can not be shortened, and offer protection zone 223.
Concrete; between crystalline setting area 221 and Han Zhi district 222, plan that solder mask is windowed protection zone 223 (can be multi-layer annular groove); not shorten while corresponding recessed groove protection zone 223 or the distance (compared with designing with conventional base plate) in less shortening crystalline setting area 221 and Han Zhi district 222 being formed; in encapsulation process, select the adhesive that thickness is larger, make the integrated circuit (IC) chip after encapsulation obtain significant package reliability grade and promote.
Fig. 6 a is the profile of the local of integrated circuit (IC) chip embodiment one of the present invention; Fig. 6 b is the vertical view of the local of integrated circuit (IC) chip embodiment one of the present invention, and as shown in Fig. 6 a, 6b, this integrated circuit (IC) chip, comprising: naked brilliant 31, the base plate for packaging shown in adhesive 32 and Fig. 2 a, Fig. 2 b, concrete:
Described base plate for packaging 20 comprises substrate layer 21 and solder mask 22, and described solder mask 22 is arranged on the top of described substrate layer 21; Described solder mask 22 comprises crystalline setting area 221, window the Han Zhi district 222 and protection zone 223 that are formed; Each Han Zhi district 222 correspondence is provided with conductive hole 211; Described conductive hole 211 is for being arranged on the through hole on described substrate layer 21; Described naked brilliant 31 are fixed on the described crystalline setting area 221 of described base plate for packaging 20 by described adhesive 32;
Wherein, described protection zone 223 is the groove formed at described solder mask 22 uplifting window, and described protection zone 223 is between described Han Zhi district 222 and described crystalline setting area 221, overflows to described Han Zhi district 222 from described crystalline setting area 221 for preventing adhesive 32.
In addition, conductive hole 211 is not necessarily arranged on the position at place, Han Zhi district 222, other positions can also be drawn out to by the cabling connecting Han Zhi district 222 and conductive hole 211 is being set, in addition each Han Zhi district 222 at least correspondence a conductive hole 211 is set, can arrange as required in specific implementation process, this is not limited.
Further, described protection zone 223 is included in the annular recess around described crystalline setting area that solder mask 22 uplifting window between described Han Zhi district 222 and described crystalline setting area 221 is formed.The number of described annular recess is at least one.
In the present embodiment, adhesive 32 can be various epoxy or else have the adhesive of packaging operation mobility, can be fixed on crystalline setting area 221, do not limit naked brilliant 31 this.Naked brilliant 31 is the circuit entity unit that wafer cuts down, and can be silicon material, can be also other material, not limit this.
In the process of specific implementation, this integrated circuit (IC) chip 30 also comprises at least identical with described Han Zhi district 222 quantity bonding line 33.Concrete, each Han Zhi district 222 can comprise one or more weldering and refer to, each weldering refers to be connected with other positions, and just need a bonding line 33, therefore the minimum number of the bonding line 33 in each Han Zhi district 222 is one.Described bonding line 33 for connecting the described naked pin of brilliant 31 and corresponding Han Zhi district 222, the naked pin of brilliant 32 is welded with corresponding Han Zhi district 222 by this bonding line 33 in the process of encapsulation.
In addition, this integrated circuit (IC) chip also comprises molded structure or adds a cover structure, and described mold structure is fill with the profiled part of packaged by plastic on described naked crystalline substance and described base plate for packaging.And to add a cover structure be encapsulated in the operator guards outside described naked crystalline substance and described base plate for packaging, generally covering outside naked crystalline substance and base plate for packaging, can be plastics, metal or pottery etc.
Such as: W/B encapsulation forms the process of integrated circuit (IC) chip and is: on the base plate for packaging of the present invention that placed naked crystalline substance, complete naked crystalline substance with the electricity of base plate for packaging by manufacturing process such as naked brilliant bonding (die bond) and routings (wire bond) be connected, again by molded (molding) or add a cover follow-up a series of processing procedure such as (lidding) and formed and be encapsulated in outer mold structure or add a cover structure, finally form semiconductor integrated circuit chip (i.e. IC chip).
(English: Ball Grid Array by BGA Package, be called for short: process BGA) forming integrated circuit (IC) chip is, naked crystalline substance (die) is fixed on base plate for packaging provided by the invention by adhesive (epoxy) bonding, then coupled together by pin and the solder mask Han Zhi district formed of windowing that inputs or outputs of bonding line (bonding wire) by naked crystalline substance, thus form effective electrically connect of naked crystalline substance and base plate for packaging.Then by each layer interconnect traces of base plate for packaging and undermost soldered ball (solder ball) or pad (pador land or footprint), the electrical interface that this integrated circuit (IC) chip is external is drawn.
In the encapsulation process of above-mentioned integrated circuit (IC) chip; the base plate for packaging 20 shown in Fig. 2 a to Fig. 5 any embodiment can be adopted; this kind of substrate 20 is by forming protection zone 223 at solder mask 22 uplifting window; the position of this protection zone 223 is between Han Zhi district 222 and crystalline setting area 221; in the forming process of integrated circuit (IC) chip 30; this aspect, protection zone 223 1 can shorten the distance in naked brilliant 31 and Han Zhi district 222; bonding line is shortened; thus reduce encapsulation spurious impedance, obtain the better integrated circuit (IC) chip of electric property.On the other hand; this protection zone 223 can effectively prevent adhesive 32 Yi Zhihanzhi district 222 from covering Han Zhi district; the region in maintenance Han Zhi district 222 can be complete for welding; and when windowing protection zone; the dosage or thickness that use adhesive can be increased, effectively improve acceptance rate and the package reliability grade of ic chip package.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (9)
1. a base plate for packaging, is characterized in that, comprising: substrate layer and solder mask, and described solder mask is arranged on the top of described substrate layer; Described solder mask comprises crystalline setting area, window the Han Zhi district and protection zone that are formed; Each Han Zhi district correspondence is provided with conductive hole; Described conductive hole is be arranged on the through hole on described substrate layer;
Described protection zone is the groove formed at described solder mask uplifting window, and described protection zone is between described Han Zhi district and described crystalline setting area, overflows to described Han Zhi district from described crystalline setting area for preventing adhesive.
2. base plate for packaging according to claim 1, is characterized in that, described protection zone is included in the annular recess around described crystalline setting area that the solder mask uplifting window between described Han Zhi district and described crystalline setting area is formed.
3. base plate for packaging according to claim 2, is characterized in that, the number of described annular recess is at least one.
4. an integrated circuit (IC) chip, is characterized in that, comprising: naked crystalline substance, adhesive and base plate for packaging;
Described base plate for packaging comprises substrate layer and solder mask, and described solder mask is arranged on the top of described substrate layer; Described solder mask comprises crystalline setting area, window the Han Zhi district and protection zone that are formed; Each Han Zhi district correspondence is provided with conductive hole; Described conductive hole is be arranged on the through hole on described substrate layer; Described naked crystalline substance is fixed on the described crystalline setting area of described base plate for packaging by described adhesive;
Wherein, described protection zone is the groove formed at described solder mask uplifting window, and described protection zone is between described Han Zhi district and described crystalline setting area, overflows to described Han Zhi district from described crystalline setting area for preventing adhesive.
5. integrated circuit (IC) chip according to claim 4, is characterized in that, also comprises at least identical with described Han Zhi district quantity bonding line, and described bonding line is for connecting the pin of described naked crystalline substance and corresponding Han Zhi district.
6. the integrated circuit (IC) chip according to claim 4 or 5, is characterized in that, described protection zone is included in the annular recess around described crystalline setting area that the solder mask uplifting window between described Han Zhi district and described crystalline setting area is formed.
7. integrated circuit (IC) chip according to claim 6, is characterized in that, the number of described annular recess is at least one.
8. the integrated circuit (IC) chip according to any one of claim 4 to 7, is characterized in that, also comprises: mold structure, and described mold structure is fill with the profiled part of packaged by plastic on described naked crystalline substance and described base plate for packaging.
9. the integrated circuit (IC) chip according to any one of claim 4 to 7, is characterized in that, also comprises: add a cover structure, described in add a cover the operator guards of construction packages outside described naked crystalline substance and described base plate for packaging.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510038389.3A CN104617077A (en) | 2015-01-26 | 2015-01-26 | Package substrate and integrated circuit chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510038389.3A CN104617077A (en) | 2015-01-26 | 2015-01-26 | Package substrate and integrated circuit chip |
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| Publication Number | Publication Date |
|---|---|
| CN104617077A true CN104617077A (en) | 2015-05-13 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510038389.3A Pending CN104617077A (en) | 2015-01-26 | 2015-01-26 | Package substrate and integrated circuit chip |
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| CN (1) | CN104617077A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113589144A (en) * | 2021-07-28 | 2021-11-02 | 江苏云意电气股份有限公司 | Jig for improving accuracy of polarity measurement and division of chip and use method |
| CN113759607A (en) * | 2021-09-13 | 2021-12-07 | Tcl华星光电技术有限公司 | Backlight module, preparation method thereof and display device |
| TWI818719B (en) * | 2022-09-08 | 2023-10-11 | 矽品精密工業股份有限公司 | Carrier structure |
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