CN104616989A - Method for manufacturing IGBT having current-carrying electron storage layer - Google Patents
Method for manufacturing IGBT having current-carrying electron storage layer Download PDFInfo
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- CN104616989A CN104616989A CN201310538947.3A CN201310538947A CN104616989A CN 104616989 A CN104616989 A CN 104616989A CN 201310538947 A CN201310538947 A CN 201310538947A CN 104616989 A CN104616989 A CN 104616989A
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 82
- 238000000227 grinding Methods 0.000 claims abstract description 6
- 238000009825 accumulation Methods 0.000 claims description 27
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 238000002161 passivation Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 239000000203 mixture Substances 0.000 description 8
- 238000002513 implantation Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 108090000723 Insulin-Like Growth Factor I Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 102000013275 Somatomedins Human genes 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a method for manufacturing an IGBT having a current-carrying electron storage layer. The method comprises the following steps: providing a substrate having a first surface and a second surface; forming a first groove in the first surface of the substrate; epitaxially forming a first epitaxial layer having the same conductivity type as the substrate on the first groove, wherein the first epitaxial layer fills the first groove; grinding the first epitaxial layer until the first surface of the substrate is exposed; forming a second groove, of which the depth and width are smaller than those of the first groove, in the upper surface of the first epitaxial layer after grinding so as to leave part of the first epitaxial layer, wherein the remaining first epitaxial layer is used as a current-carrying electron storage layer; epitaxially forming a second epitaxial layer having the same conductivity type as the substrate on the second groove, wherein the second epitaxial layer fills the second groove; and grinding the second epitaxial layer until the first surface of the substrate is exposed. The method can avoid the problem that the breakdown voltage of a device is too low due to the concentration of a CS corner.
Description
[technical field]
The present invention relates to semiconductor design and manufacturing technology field, particularly a kind of IGBT(Insulated Gate Bipolar Transistor with current-carrying electrons accumulation layer, igbt) manufacture method.
[background technology]
IGBT is by BJT(Bipolar Junction Transistor, bipolar junction transistor) and MOSFET(Metal-Oxide-Semiconductor-Field-Effect-Transistor, mos field effect transistor) the compound full-control type voltage driven type power semiconductor that forms, have the advantage of the high input impedance of MOSFET and low conduction voltage drop two aspect of BJT concurrently, there is operating frequency high, control circuit is simple, current density is high, on-state such as to force down at the feature, is widely used in power control field.In actual applications, IGBT seldom uses as an individual devices, and especially under the condition of inductive load, IGBT needs a fast recovery diode afterflow.Therefore, existing igbt product, the general fly-wheel diode in parallel (Freewheeling diode is called for short FWD) that adopts is to protect IGBT.
The existing IGBT with current-carrying electrons accumulation layer mainly adopts ion implantation mode to form current-carrying electrons accumulation layer (CS layer), and its shortcoming is that CS layer process controls difficulty greatly in technique manufacturing process, and CS layer concentration is wayward, pushes away trap consuming time longer; And CS layer corner easily punctures, thus cause overall device puncture voltage on the low side.
Therefore, be necessary to provide a kind of technical scheme of improvement to overcome the problems referred to above.
[summary of the invention]
The object of the present invention is to provide a kind of manufacture method with the IGBT of current-carrying electrons accumulation layer, itself and existing common process are compatible, and CS layer concentration is easy to control, efficiency is high and can avoid the problem because CS corner concentration problems causes device electric breakdown strength on the low side.
In order to solve the problem, according to an aspect of the present invention, the invention provides a kind of manufacture method with the IGBT of current-carrying electrons accumulation layer, it comprises:
The substrate with first surface and second surface is provided;
The first groove is formed at the first surface of described substrate;
On described first groove, extension forms conduction type first epitaxial loayer identical with substrate, and described first epitaxial loayer fills up the first groove, and wherein the doping content of the first epitaxial loayer is high compared with the doping content of substrate;
Grind described first epitaxial loayer until expose the first surface of described substrate;
The upper surface Formation Depth of the first epitaxial loayer after grinding and width are less than the degree of depth of described first groove and the second groove of width to remain a part of first epitaxial loayer, and remaining first epitaxial loayer is as current-carrying electrons accumulation layer;
On described second groove, extension forms conduction type second epitaxial loayer identical with substrate, and described second epitaxial loayer fills up the second groove; With
Grind described second epitaxial loayer until expose the first surface of described substrate.
As a preferred embodiment of the present invention, the doping content of the second epitaxial loayer equals the doping content of substrate.
As a preferred embodiment of the present invention, form the Facad structure of IGBT in the side of first surface of the substrate being formed with the first epitaxial loayer and the second epitaxial loayer,
The inverse layer structure of IGBT is formed in the side of second surface of the substrate being formed with the first epitaxial loayer and the second epitaxial loayer.
As a preferred embodiment of the present invention, the Facad structure of described IGBT comprises:
Described first epitaxial loayer selectively forms the conduction type base different from substrate;
The emitter region that the conduction type selectively formed in described base is identical with substrate;
Be positioned at the gate oxide on described substrate;
The polysilicon gate that the surface of described grid oxic horizon is formed;
Cover the dielectric layer of described grid oxic horizon and polysilicon gate;
With described base and described emitter region front metal electrode in electrical contact;
The inverse layer structure of described IGBT comprises:
The second surface of described substrate is formed the conduction type collector layer different from substrate;
Described collector layer is formed back metal electrode, this back metal electrode and described collector layer in electrical contact.
As a preferred embodiment of the present invention, the Facad structure of described IGBT also comprises:
Be formed at the passivation layer outside front metal electrode.
The present invention also provides another kind to have the manufacture method of the IGBT of current-carrying electrons accumulation layer, and it comprises:
The substrate with first surface and second surface is provided;
The first groove is formed at the first surface of described substrate;
On described first groove, extension forms conduction type first epitaxial loayer identical with substrate, and described first epitaxial loayer fills up the first groove, and wherein the doping content of the first epitaxial loayer is high compared with the doping content of substrate;
Grind described first epitaxial loayer until expose the first surface of described substrate;
The Facad structure of IGBT is directly formed in the side of first surface of the substrate being formed with the first epitaxial loayer, and
The inverse layer structure of IGBT is formed in the side of second surface of the substrate being formed with the first epitaxial loayer.
As a preferred embodiment of the present invention, the Facad structure of described IGBT comprises:
Described first epitaxial loayer selectively forms the conduction type base different from substrate;
The emitter region that the conduction type selectively formed in described base is identical with substrate;
Be positioned at the gate oxide on described substrate;
The polysilicon gate that the surface of described grid oxic horizon is formed;
Cover the dielectric layer of described grid oxic horizon and polysilicon gate;
With described base and described emitter region front metal electrode in electrical contact;
The inverse layer structure of described IGBT comprises:
The second surface of described substrate is formed the conduction type collector layer different from substrate;
Described collector layer is formed back metal electrode, this back metal electrode and described collector layer in electrical contact.
As a preferred embodiment of the present invention, the Facad structure of described IGBT also comprises:
Be formed at the passivation layer outside front metal electrode.
As a preferred embodiment of the present invention, described Ginding process is CMP (Chemical Mechanical Polishing) process.
Compared with prior art, the present invention is a kind of to be had in the manufacture method of the IGBT of current-carrying electrons accumulation layer, use and realize CS layer with the epitaxial growth method of the existing process compatible of routine, technique is simple, CS layer concentration is easy to control, efficiency is high and can avoid the problem because CS corner concentration problems causes device electric breakdown strength on the low side.
[accompanying drawing explanation]
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.Wherein:
Fig. 1 is the flow chart in one embodiment of the manufacture method with the IGBT of current-carrying electrons accumulation layer in the present invention;
Fig. 2 to Fig. 7 is the vertical section schematic diagram that each manufacturing process of manufacture method in Fig. 1 obtains wafer.
[embodiment]
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, and below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
Alleged herein " embodiment " or " embodiment " refers to special characteristic, structure or the characteristic that can be contained at least one implementation of the present invention.Different local in this manual " in one embodiment " occurred not all refers to same embodiment, neither be independent or optionally mutually exclusive with other embodiments embodiment.
Introduce in the present invention there is the manufacture method of the IGBT of current-carrying electrons accumulation layer before, it should be noted that, the emitter of IGBT and the face at grid place are understood to front usually, and the face at the collector electrode place of IGBT is understood reverse side or the back side usually.
Fig. 1 is manufacture method 100 flow chart in one embodiment with the IGBT of current-carrying electrons accumulation layer in the present invention.As shown in Figure 1, described manufacture method 100 comprises the steps.
Step 110, provides the N-type or P type substrate 10 with first surface 11 and second surface 12.
Concrete, described substrate 10 be silicon chip, and its thickness is normal is such as the silicon wafer thickness that normally circulates for the thickness of 6 cun of sheets, and the normal thickness such as 6 cun of sheets is 625 μm/675 μm, the normal thickness of 8 cun of sheets is 725 μm.
Step 120, shown in composition graphs 2, forms the first groove 13 at the first surface 11 of described substrate 10.
In one embodiment, described first groove 13 can be formed by etching technics, certainly, also can adopt other techniques.
Step 130, shown in composition graphs 3, described first groove 13 carries out extension and fills the first epitaxial loayer 14 forming N-type or P type, described first epitaxial loayer 14 fills up the first groove 13, and the doping content of described first epitaxial loayer 14 is higher than the doping content of described substrate 10.
Concrete, the lower surface of described first epitaxial loayer contacts with the first surface 11 of described substrate, and the minimum point of the upper surface of described first epitaxial loayer is higher than the peak of the first surface 11 of described substrate.
When described substrate is N-type, form N-type first epitaxial loayer 14 in described step 130, when described substrate 10 is P type, form P type first epitaxial loayer 14 in described step 130, conduction type is between the two identical.In the embodiment shown by Fig. 2-7, with backing material 10 for N-type, the first epitaxial loayer 14 for N-type be that example is introduced.Concrete, as shown in Figure 3, described first groove 13 carries out extension and fills the first epitaxial loayer 14 forming N-type, resistivity is 5 ~ 100 Ω * cm.The doping content of described first epitaxial loayer 14 is higher than the doping content of described substrate 10, and described dopant is N-type impurity ion (such as phosphorus or arsenic).
Step 140, shown in composition graphs 4, grinds described first epitaxial loayer 14 until expose the first surface 11 of described substrate 10.
Concrete, start to polish described first epitaxial loayer 14 until expose the first surface 11 of described substrate 10 from the upper table of described first epitaxial loayer 14 by CMP (Chemical Mechanical Polishing) process (CMP), now the described upper surface of the first epitaxial loayer 14 and the first surface 11 of described substrate 10 flush.
Step 150, shown in composition graphs 5, the upper surface Formation Depth of the first epitaxial loayer 14 after grinding and width are less than the degree of depth of described first groove 13 and the second groove 17 of width to remain a part of first epitaxial loayer, and remaining first epitaxial loayer is as current-carrying electrons accumulation layer 18;
Concrete, form the second groove 17 at the upper surface of described first epitaxial loayer 14; Now described first epitaxial loayer 14 forms current-carrying electrons accumulation layer 18; The degree of depth of described first groove 13 and width are greater than the degree of depth and the width of described second groove 17.
Step 160, described second groove 17 carries out extension and fills the second epitaxial loayer 19 forming N-type, described second epitaxial loayer 19 fills up the second groove 17;
Concrete, the lower surface of described second epitaxial loayer 19 contacts with the upper surface of described first epitaxial loayer 14, and the minimum point of the upper surface of described second epitaxial loayer 19 is higher than the peak of the upper surface of described first epitaxial loayer 14, described second epitaxial loayer 19 ooze the doping content that assorted concentration equals described substrate 10, object in order to existing process compatible, do not need change subsequent technique.
Step 170, shown in composition graphs 6, grinds described second epitaxial loayer 19 until expose the first surface 11 of described substrate 10.
Concrete, start to polish described second epitaxial loayer 19 until expose the first surface 11 of described substrate from the upper surface of described second epitaxial loayer 19 by CMP (Chemical Mechanical Polishing) process.
Step 180, shown in composition graphs 7, forms the Facad structure of IGBT in the side of first surface 11 of the substrate 10 being formed with the first epitaxial loayer 14 and the second epitaxial loayer 19,
Step 190, shown in composition graphs 7, forms the inverse layer structure of IGBT in the side of second surface 12 of the substrate 10 being formed with the first epitaxial loayer 14 and the second epitaxial loayer 19.
Concrete, shown in composition graphs 7, described N-type substrate 10, as drift region 22, has Facad structure and the structure of the IGBT of current-carrying electrons accumulation layer based on described drift region 22 described in being formed.
The Facad structure of a kind of planar I GBT is illustrated in Fig. 7.The Facad structure of described IGBT comprises: the P type base (P-body) 23 selectively formed on the surface of described first epitaxial loayer 14, the N-type emitter region 24 selectively formed in described P type base 23, be positioned at the gate oxide (not shown) on the first surface 11 of described drift region 22, the polysilicon gate 25 that described grid oxic horizon is formed, the dielectric layer covering described grid oxic horizon and polysilicon gate 25 is not shown, and with described P type base 23 and described N-type emitter region 24 front metal electrode (i.e. emitter in electrical contact, not shown).
Just schematically illustrate front metal electrode in Fig. 7, in fact, front metal electrode may cover whole dielectric layer.In addition, the Facad structure of described IGBT also may comprise the passivation layer (not shown) be formed at outside front metal electrode, such as silicon dioxide and silicon nitride.
In other embodiments, can manufacture groove-shaped IGBT, the described Facad structure of groove-shaped IGBT is not identical with the Facad structure of the IGBT in Fig. 7, but has disclosed a lot of groove-shaped IGBT in prior art yet, here just no longer repeated description.Need to know, from certain angle of the present invention, the present invention is not concerned about the concrete Facad structure of IGBT especially, as long as have Facad structure and can form operable IGBT device.
The present invention proposes an example of the manufacturing process of the Facad structure of the IGBT in a kind of Fig. 7, and this flow process comprises:
Step one, growth grid oxic horizon, such as thickness is
Step 2, on grid oxic horizon, generate polycrystalline silicon gate layer, such as thickness is
Step 3, polysilicon gate photoetching, etching, ion implantation, push away trap to form P base, p type impurity implantation dosage is 1E12 ~ 1E15cm
-2, Implantation Energy is 20keV ~ 1MeV; Pushing away trap temperature is 1000 ~ 1250 DEG C, and the time is 10min ~ 1000min.
Step 4, the photoetching of N-type emitter region, ion implantation, annealing to form N-type, dosage 1E14 ~ 1E16cm
-2, energy is 20keV ~ 1MeVcm
-2; Annealing temperature is 800 ~ 1000 DEG C, and the time is 10min ~ 1000min;
Step 5, somatomedin layer, thickness:
Step 6, contact hole photoetching, be etched with formation contact hole, this contact hole communicates with described N-type emitter region and P type base;
Step 7, front metal layer deposit, thickness is about 2 μm ~ 6 μm;
Step 8, passivation layer deposit.
Also show the structure of IGBT in Fig. 7, the structure of described IGBT comprises: on described drift region 22 second surface 12, form P type collector layer 26;
Described P type collector layer 26 forms back metal electrode, this back metal electrode and described P type collector layer 26 in electrical contact.
From another angle, about the concrete manufacturing process of the front and back structure of IGBT does not belong to emphasis of the present invention yet, it can adopt existing various manufacturing process manufacture to form, therefore in order to outstanding emphasis of the present invention, about the concrete manufacturing process of the front and back structure of IGBT is not described in detail in this article.
Present invention also offers another kind of execution mode, the step of this kind of execution mode comprises above-mentioned steps 110-140, therefore step 110-140 does not repeat them here.
After step 140, directly form the Facad structure of IGBT in the side of first surface 11 of the substrate 10 being formed with the first epitaxial loayer 14,
The inverse layer structure of IGBT is formed in the side of second surface 12 of the substrate 10 being formed with the first epitaxial loayer 14.
Making due to the obverse and reverse structure of IGBT has had in the manufacture method of the IGBT of current-carrying electrons accumulation layer at the first to be introduced in detail, therefore does not repeat them here.
It should be noted that, in this manufacture method, the Implantation Energy of P type base (P-body) 23 and N-type emitter region 24 and dosage etc. need reset.Because comparatively substrate 10 concentration is high for the first epitaxial loayer 14 doping content, in order to ensure cut-in voltage Vth not step-down, the implantation dosage of P type base 23 needs to increase (energy can not make and change), adulterate in order to compensate substrate 10, how many concrete increases is depending on the first epitaxial loayer 14 doping content, in like manner, the implantation dosage of N-type emitter region 24 can reduce (energy can not make and change).
What the those of ordinary skill in affiliated field should be understood that is, one of feature of the present invention or object are: the method adopting epitaxial growth CS layer, effective control CS layer doping content, and process compatible existing with routine, technique is simple, efficiency is high, and the concentration process of CS turning is better, can not become and puncture weak spot.
N-type in above-described embodiment can be called as the first conduction type, and P type can be called as the second conduction type.In other embodiments, the region (such as P base, P type collector area) of the involved all P types in above-described embodiment can change to N-type, the region (N-type drift region, N-type current-carrying electrons accumulation layer, N-type emitter region) of all N-types can change to P type, now can think that the first conduction type is N-type, the second conduction type is P type.
It is pointed out that the scope be familiar with person skilled in art and any change that the specific embodiment of the present invention is done all do not departed to claims of the present invention.Correspondingly, the scope of claim of the present invention is also not limited only to previous embodiment.
Claims (9)
1. have a manufacture method of the IGBT of current-carrying electrons accumulation layer, it is characterized in that, it comprises:
The substrate with first surface and second surface is provided;
The first groove is formed at the first surface of described substrate;
On described first groove, extension forms conduction type first epitaxial loayer identical with substrate, and described first epitaxial loayer fills up the first groove, and wherein the doping content of the first epitaxial loayer is high compared with the doping content of substrate;
Grind described first epitaxial loayer until expose the first surface of described substrate;
The upper surface Formation Depth of the first epitaxial loayer after grinding and width are less than the degree of depth of described first groove and the second groove of width to remain a part of first epitaxial loayer, and remaining first epitaxial loayer is as current-carrying electrons accumulation layer;
On described second groove, extension forms conduction type second epitaxial loayer identical with substrate, and described second epitaxial loayer fills up the second groove; With
Grind described second epitaxial loayer until expose the first surface of described substrate.
2. the manufacture method with the IGBT of current-carrying electrons accumulation layer according to claim 1, it is characterized in that, it also comprises:
The doping content of the second epitaxial loayer equals the doping content of substrate.
3. the manufacture method with the IGBT of current-carrying electrons accumulation layer according to claim 1, it is characterized in that, it also comprises:
The Facad structure of IGBT is formed in the side of first surface of the substrate being formed with the first epitaxial loayer and the second epitaxial loayer,
The inverse layer structure of IGBT is formed in the side of second surface of the substrate being formed with the first epitaxial loayer and the second epitaxial loayer.
4. the manufacture method with the IGBT of current-carrying electrons accumulation layer according to claim 3, is characterized in that,
The Facad structure of described IGBT comprises:
Described first epitaxial loayer selectively forms the conduction type base different from substrate;
The emitter region that the conduction type selectively formed in described base is identical with substrate;
Be positioned at the gate oxide on described substrate;
The polysilicon gate that the surface of described grid oxic horizon is formed;
Cover the dielectric layer of described grid oxic horizon and polysilicon gate; With
With described base and described emitter region front metal electrode in electrical contact;
The inverse layer structure of described IGBT comprises:
The second surface of described substrate is formed the conduction type collector layer different from substrate;
Described collector layer is formed back metal electrode, this back metal electrode and described collector layer in electrical contact.
5. the manufacture method with the IGBT of current-carrying electrons accumulation layer according to claim 4, is characterized in that, the Facad structure of described IGBT also comprises:
Be formed at the passivation layer outside front metal electrode.
6. have a manufacture method of the IGBT of current-carrying electrons accumulation layer, it is characterized in that, it comprises:
The substrate with first surface and second surface is provided;
The first groove is formed at the first surface of described substrate;
On described first groove, extension forms conduction type first epitaxial loayer identical with substrate, and described first epitaxial loayer fills up the first groove, and wherein the doping content of the first epitaxial loayer is high compared with the doping content of substrate;
Grind described first epitaxial loayer until expose the first surface of described substrate;
The Facad structure of IGBT is directly formed in the side of first surface of the substrate being formed with the first epitaxial loayer; With
The inverse layer structure of IGBT is formed in the side of second surface of the substrate being formed with the first epitaxial loayer.
7. the manufacture method with the IGBT of current-carrying electrons accumulation layer according to claim 6, is characterized in that,
The Facad structure of described IGBT comprises:
Described first epitaxial loayer selectively forms the conduction type base different from substrate;
The emitter region that the conduction type selectively formed in described base is identical with substrate;
Be positioned at the gate oxide on described substrate;
The polysilicon gate that the surface of described grid oxic horizon is formed;
Cover the dielectric layer of described grid oxic horizon and polysilicon gate;
With described base and described emitter region front metal electrode in electrical contact;
The inverse layer structure of described IGBT comprises:
The second surface of described substrate is formed the conduction type collector layer different from substrate;
Described collector layer is formed back metal electrode, this back metal electrode and described collector layer in electrical contact.
8. the manufacture method with the IGBT of current-carrying electrons accumulation layer according to claim 7, is characterized in that, the Facad structure of described IGBT also comprises:
Be formed at the passivation layer outside front metal electrode.
9. the manufacture method with the IGBT of current-carrying electrons accumulation layer according to claim 1 or 6, is characterized in that,
Described Ginding process is CMP (Chemical Mechanical Polishing) process.
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| JP2013197306A (en) * | 2012-03-19 | 2013-09-30 | Fuji Electric Co Ltd | Manufacturing method of semiconductor device |
| KR20130119873A (en) * | 2012-04-24 | 2013-11-01 | 페어차일드코리아반도체 주식회사 | Power device and method for fabricating the same |
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| US20070080407A1 (en) * | 2005-10-06 | 2007-04-12 | Sanken Electric Co., Ltd. | Insulated gate bipolar transistor |
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| JP2013197306A (en) * | 2012-03-19 | 2013-09-30 | Fuji Electric Co Ltd | Manufacturing method of semiconductor device |
| CN102683402A (en) * | 2012-04-24 | 2012-09-19 | 电子科技大学 | Flat-grid electric charge storage type IGBT (insulated gate bipolar translator) |
| KR20130119873A (en) * | 2012-04-24 | 2013-11-01 | 페어차일드코리아반도체 주식회사 | Power device and method for fabricating the same |
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