CN104601164A - Phase inverter designed on basis of three MOS (metal oxide semiconductor) tubes and filter circuit - Google Patents
Phase inverter designed on basis of three MOS (metal oxide semiconductor) tubes and filter circuit Download PDFInfo
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- CN104601164A CN104601164A CN201510058195.XA CN201510058195A CN104601164A CN 104601164 A CN104601164 A CN 104601164A CN 201510058195 A CN201510058195 A CN 201510058195A CN 104601164 A CN104601164 A CN 104601164A
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Abstract
The invention discloses a phase inverter designed on the basis of three MOS (metal oxide semiconductor) tubes and a filter circuit. The phase inverter and the filter circuit have the advantages that two PMOS (p-channel metal oxide semiconductor) tubes are serially connected with a power supply end of the phase inverter according to e-index response working principles of the MOS tubes in ultra-low-voltage microelectronics, then an NMOS (n-channel metal oxide semiconductor) tube is serially connected to a power ground, grid electrodes of the three tubes are connected with one another in parallel to form an input end, and an output end is selectively arranged at a drain electrode of the NMOS tube; large width-to-length ratios of the two PMOS tubes are selectively determined, and the NMOS tube only selectively has a small width-to-length ratio; circuit topology formed by the three ultra-low-voltage power supply MOS tubes which are serially connected with one another has double-threshold input and phase inversion output characteristics, and the filter circuit is of a circuit topological structure with the three MOS tubes as compared with the traditional Schmidt circuit with six MOS tubes, and accordingly is simple in structure.
Description
Technical field
The present invention relates to electronic circuit design field, relate to a kind of inverter based on 3 metal-oxide-semiconductor designs and filter circuit in particular.
Background technology
In recent years, along with the urgent need of intelligent miniature terminal, extra low voltage microelectronics enjoys favor.Inverter is as the typical module in electronic circuit, and the topological structure of its classics is the Schmidt trigger not gate of the two-tube not gate of CMOS or 6 pipes.Wherein, the inverter of the two-tube non-door of CMOS has single threshold function, only has Schmidt circuit just to have dual threshold return difference characteristic.In actual applications, usually need the dual threshold return difference characteristic utilizing Schmidt circuit to carry out circuit design, but Schmidt circuit is 6 tubular constructions, circuit topological structure is complicated.
Summary of the invention
In view of this, the invention provides a kind of inverter based on 3 metal-oxide-semiconductor designs and filter circuit, this inverter has dual threshold output characteristic, and circuit topological structure is simple.
For achieving the above object, the invention provides following technical scheme:
Based on an inverter for 3 metal-oxide-semiconductor designs, comprising: the first PMOS, the second PMOS and NMOS tube;
Wherein, the source electrode of described first PMOS is connected with power supply, drains to be connected with the source electrode of described second PMOS;
The drain electrode of described second PMOS is connected with the drain electrode of described NMOS tube;
The source ground of described NMOS tube;
The gate connected in parallel of described first PMOS, described second PMOS and described NMOS tube is as signal input part, and the drain electrode of described NOMS pipe is signal output part.
Preferably, the voltage of described power supply is 440mV ~ 90mV.
Preferably, the breadth length ratio of described first PMOS and described second PMOS is 22727 ~ 1363.
Preferably, the breadth length ratio of described NMOS tube is 3636 ~ 454.
Preferably, the signal of described signal input part input is the time varying signal of peak value 30mV ~ 120mV.
A kind of filter circuit, the inverter preferably described in above content.
Known via above-mentioned technical scheme, compared with prior art, the invention discloses a kind of inverter based on 3 metal-oxide-semiconductor designs and filter circuit.This inverter is according in extra low voltage microelectronics, and the e index responsive operation principle of metal-oxide-semiconductor, to connect 2 PMOS at feeder ear, trail series connection 1 NMOS tube to power supply ground, the grid of 3 pipes in parallel is as input, and output selection is in the drain electrode of NMOS tube.And then determine that 2 PMOS select larger breadth length ratio, NMOS tube selects less breadth length ratio.To be powered the circuit topology that 3 metal-oxide-semiconductors are in series by above-mentioned extra low voltage, be namely provided with input dual threshold and export anti-phase characteristic, compared with tradition 6 metal-oxide-semiconductor Schmidt circuits, the present invention adopts the circuit topological structure of 3 metal-oxide-semiconductors, and circuit structure is simple.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only embodiments of the invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to the accompanying drawing provided.
Fig. 1 shows a kind of circuit diagram that there is an embodiment of the method for the inverter of dual threshold output characteristic based on 3 metal-oxide-semiconductors of the present invention;
Fig. 2 shows a kind of anti-phase amplification low pass circuit diagram of high input impedance that there is another embodiment of the method for the inverter of dual threshold output characteristic based on 3 metal-oxide-semiconductors of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
In extra low voltage microelectronics, the actual threshold of the metal-oxide-semiconductor of " zero " threshold value is in about 20mV, the principle obtaining the metal-oxide-semiconductor of so small threshold value is: ultralow supply power voltage is in hundreds of millivolts of magnitudes, and the breadth length ratio of pipe is in 1000 orders of magnitude, at this moment, due to the grid voltage power law that drain current is about e index, for non-linear, so in designed novel circuit topological, the pipe (2P+N) successively decreased owing to selecting the large breadth length ratio of 3 particular ranges, just can form new dual threshold working mechanism.
To sum up, in order to promote the microelectronic development of extra low voltage, design the dual threshold inverter circuit of three metal-oxide-semiconductors, further expand its four functions (to trigger, return difference, anti-phase, amplify), and be high input impedance low pass filter, as the amplifier prime of non-cpntact measurement body surface electromotive force.
Embodiment (one)
The present invention is shown, a kind of circuit diagram of an embodiment of the inverter based on 3 metal-oxide-semiconductor designs see Fig. 1.
This inverter comprises: the first PMOS PM1, the second PMOS PM2 and NMOS tube NM1.
Wherein, the source electrode of described first PMOS is connected with power supply, drains to be connected with the source electrode of described second PMOS.
The drain electrode of described second PMOS is connected with the drain electrode of described NMOS tube;
The source ground of described NMOS tube;
The gate connected in parallel of described first PMOS, affiliated second PMOS and described NMOS tube is as signal input part, and the drain electrode of described NOMS pipe is signal output part.
It should be noted that, the voltage of power supply is extra low voltage value in the present embodiment, and concrete range of choice is 440mV ~ 90mV.First PMOS and the second PMOS adopt the PMOS that breadth length ratio is larger, as adopted the PMOS of breadth length ratio scope between 22427 ~ 1363, described NMOS tube adopt breadth length ratio less as 3636 ~ 454 NMOS tube.
In addition, the input signal of the signal input part of inverter is the time varying signal of peak value at 30mV ~ 120mV in the present embodiment, the signal output loading of inverter is the CMOS inverter of stock size, and the output dual threshold scope of inverter is between 44mV ~ 0mV in the present embodiment.
Analyze input and output response characteristic and circuit structure feature known, only need three metal-oxide-semiconductors of connecting (2P1N), simply by virtue of the cost of super large breadth length ratio, the function that can simultaneously bring comprises: return difference, anti-phase, amplifies, trigger (memory), these four functions; Be different from this circuit structure and pipe yardstick, then can only realize this four functions respectively, and need 1 traditional two pipe not gate, 16 pipe Schmidt not gate, also have 1 operational amplifier.
As known from the above: the invention provides a kind of inverter based on 3 metal-oxide-semiconductor designs, with while simplification circuit topology, still keep dual threshold and reversed nature, and signal amplification factor is slightly larger than 1.
Embodiment (two)
A kind of circuit diagram of filter circuit is shown see Fig. 2.This filter circuit is the anti-phase amplification low pass circuit of high input impedance, and its principle is based on the inverter introduced in embodiment one.
As shown in Figure 2, this filter circuit comprises: the inverter be made up of the first PMOS PM1, the second PMOS PM2 and NMOS tube NM1.
Step 101: the connection and the dual threshold that first complete Fig. 1 are determined, be namely ensure that embodiment () debugging is passed through, in fig. 2, these 3 pipes are numbered PM1, PM2, NM1 equally.
At signal input part Vin place's increase by input current-limiting resistance R1 of inverter, its resistance value is 1M Ω.
At the right-hand member of resistance R1, namely grid, the pseudo-resistance of pull-up one series cascade, use 4 PMOS structure (PM4 ~ PM7), the pseudo-resistance R of series connection selecting the scope of little breadth length ratio to be in 1 ~ 56, PM4 and PM5 is the 8.9G Ω order of magnitude, and bias voltage can select supply power voltage.
The output of the signal of inverter, links output end vo ut after 1 grade of not gate (PM3, NM2) buffering, selects the scope of the little breadth length ratio of PM3 and NM2 to be in 30 ~ 100.
By the intermediate node of output end vo ut cross-over connection 1 electric capacity C1 to pseudo-resistance chain, value is 50fF.
By the grid of another 1 the electric capacity C2 of output end vo ut cross-over connection to three pipe inverters, value is 50fF.
Analyze input and output response characteristic and circuit structure feature known, on the basis of embodiment (one) (Fig. 1), increase only 6 metal-oxide-semiconductors (5P1N), 2 electric capacity and 1 resistance, with regard to the anti-phase amplification low pass circuit of high input impedance that framework makes new advances, can obtain cut-off frequency by the time constant R of low pass, the inverse of C1 and be in the 2.5kHz order of magnitude, wherein, R is the pseudo-resistance value of series connection of PM4 and PM5.
For embodiment (), in the present embodiment (two), this filter circuit has the following advantages:
(1) framework increase only 6 pipes (5P1N), 2 electric capacity and 1 resistance.
(2) cut-off frequency can be obtained by the time constant R of low pass, the inverse of C1 and be in the 2.5kHz order of magnitude.
(3) the input impedance order of magnitude of embodiment (two) circuit is 50fF//1.5T Ω.
Finally, also it should be noted that, in this article, the such as relational terms of first and second grades and so on is only used for an entity or operation to separate with another entity or operating space, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or equipment and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or equipment.When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment comprising described key element and also there is other identical element.
In this specification, each embodiment adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar portion mutually see.
To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the application.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein when not departing from the spirit or scope of the application, can realize in other embodiments.Therefore, the application can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (6)
1., based on an inverter for 3 metal-oxide-semiconductor designs, it is characterized in that, comprising: the first PMOS, the second PMOS and NMOS tube;
Wherein, the source electrode of described first PMOS is connected with power supply, drains to be connected with the source electrode of described second PMOS;
The drain electrode of described second PMOS is connected with the drain electrode of described NMOS tube;
The source ground of described NMOS tube;
The gate connected in parallel of described first PMOS, described second PMOS and described NMOS tube is as signal input part, and the drain electrode of described NOMS pipe is signal output part.
2. inverter according to claim 1, is characterized in that, the voltage of described power supply is 440mV ~ 90mV.
3. inverter according to claim 1, is characterized in that, the breadth length ratio of described first PMOS and described second PMOS is 22727 ~ 1363.
4. reverser according to claim 1, is characterized in that, the breadth length ratio of described NMOS tube is 3636 ~ 454.
5. inverter according to claim 1, is characterized in that, the signal of described signal input part input is the time varying signal of peak value 30mV ~ 120mV.
6. a filter circuit, is characterized in that, comprises the inverter described in claim 1 to claim 5 any one claim.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510058195.XA CN104601164A (en) | 2015-02-04 | 2015-02-04 | Phase inverter designed on basis of three MOS (metal oxide semiconductor) tubes and filter circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510058195.XA CN104601164A (en) | 2015-02-04 | 2015-02-04 | Phase inverter designed on basis of three MOS (metal oxide semiconductor) tubes and filter circuit |
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| CN104601164A true CN104601164A (en) | 2015-05-06 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106972850A (en) * | 2017-03-03 | 2017-07-21 | 安徽大学 | A kind of phase inverter with anti-single particle transient effect |
| CN108923777A (en) * | 2018-07-02 | 2018-11-30 | 安徽大学 | The inverter module of radiation hardened |
| WO2020147306A1 (en) * | 2019-01-17 | 2020-07-23 | 南京观海微电子有限公司 | Withstand voltage level conversion circuit |
| CN111769817A (en) * | 2020-07-10 | 2020-10-13 | 电子科技大学 | PMOS-based pull-up and pull-down filter circuit |
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| JPS59127857A (en) * | 1983-01-12 | 1984-07-23 | Hitachi Ltd | Semiconductor device |
| JPS60154657A (en) * | 1984-01-25 | 1985-08-14 | Hitachi Ltd | Low temperature semiconductor device |
| US20040012418A1 (en) * | 2002-07-19 | 2004-01-22 | Kim Kyung Whan | Power-up circuit |
| JP2010183087A (en) * | 2010-02-22 | 2010-08-19 | Mitsubishi Heavy Ind Ltd | Semiconductor circuit |
| CN102097123A (en) * | 2010-12-21 | 2011-06-15 | 中国科学院半导体研究所 | Anti-single event effect static random access memory unit |
| CN103001615A (en) * | 2012-11-22 | 2013-03-27 | 江苏格立特电子有限公司 | Delay circuit |
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2015
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59127857A (en) * | 1983-01-12 | 1984-07-23 | Hitachi Ltd | Semiconductor device |
| JPS60154657A (en) * | 1984-01-25 | 1985-08-14 | Hitachi Ltd | Low temperature semiconductor device |
| US20040012418A1 (en) * | 2002-07-19 | 2004-01-22 | Kim Kyung Whan | Power-up circuit |
| JP2010183087A (en) * | 2010-02-22 | 2010-08-19 | Mitsubishi Heavy Ind Ltd | Semiconductor circuit |
| CN102097123A (en) * | 2010-12-21 | 2011-06-15 | 中国科学院半导体研究所 | Anti-single event effect static random access memory unit |
| CN103001615A (en) * | 2012-11-22 | 2013-03-27 | 江苏格立特电子有限公司 | Delay circuit |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106972850A (en) * | 2017-03-03 | 2017-07-21 | 安徽大学 | A kind of phase inverter with anti-single particle transient effect |
| CN108923777A (en) * | 2018-07-02 | 2018-11-30 | 安徽大学 | The inverter module of radiation hardened |
| WO2020147306A1 (en) * | 2019-01-17 | 2020-07-23 | 南京观海微电子有限公司 | Withstand voltage level conversion circuit |
| CN111769817A (en) * | 2020-07-10 | 2020-10-13 | 电子科技大学 | PMOS-based pull-up and pull-down filter circuit |
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