CN104599968B - Field-effect transistor and preparation method thereof - Google Patents
Field-effect transistor and preparation method thereof Download PDFInfo
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- CN104599968B CN104599968B CN201510011790.8A CN201510011790A CN104599968B CN 104599968 B CN104599968 B CN 104599968B CN 201510011790 A CN201510011790 A CN 201510011790A CN 104599968 B CN104599968 B CN 104599968B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 41
- 238000002353 field-effect transistor method Methods 0.000 title abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 75
- 239000004065 semiconductor Substances 0.000 claims abstract description 71
- 238000010276 construction Methods 0.000 claims abstract description 50
- 238000011065 in-situ storage Methods 0.000 claims abstract description 21
- 238000002955 isolation Methods 0.000 claims abstract description 20
- 239000013078 crystal Substances 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims description 61
- 239000002184 metal Substances 0.000 claims description 61
- 238000000034 method Methods 0.000 claims description 60
- 230000005669 field effect Effects 0.000 claims description 43
- 239000000463 material Substances 0.000 claims description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 23
- 229920005591 polysilicon Polymers 0.000 claims description 23
- 229910021332 silicide Inorganic materials 0.000 claims description 23
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 22
- 238000006213 oxygenation reaction Methods 0.000 claims description 16
- 230000001105 regulatory effect Effects 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 230000008021 deposition Effects 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 10
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 6
- 239000007788 liquid Substances 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 claims description 3
- 238000003475 lamination Methods 0.000 claims 2
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- 239000010410 layer Substances 0.000 description 200
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 34
- 229910052814 silicon oxide Inorganic materials 0.000 description 28
- 230000000694 effects Effects 0.000 description 17
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- 238000000151 deposition Methods 0.000 description 11
- 238000001312 dry etching Methods 0.000 description 10
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- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 8
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000007547 defect Effects 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
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- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 3
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of field-effect transistor and preparation method thereof, including：Semiconductor substrate is provided, first grid laminated construction is formed on a semiconductor substrate, the first side wall is formed in first grid laminated construction both sides；Sunk structure is formed in the Semiconductor substrate on the outside of first side wall；Insulating medium layer is formed in sunk structure；Doping in situ is carried out, source-drain structure is formed above the insulating medium layer；Isolation structure is formed in the Semiconductor substrate on the outside of the source-drain structure；By using rear isolation technology so that in source-drain area doped epitaxial in situ using the Semiconductor substrate beyond source-drain area as extension inculating crystal layer, substantially increase the quality and speed of extension.
Description
Technical field
The invention belongs to super large-scale integration manufacturing technology field, it is related to a kind of field-effect transistor and its preparation side
Method.
Background technology
For plane MOSFET, when channel length reduces, short-channel effect will be increasingly severe.And for advanced
FDSOI (Full Depletion Semiconductor on Insulation) baseplate material, can efficiently control short ditch
Channel effect, but SOI has its own shortcoming, mainly there is self-heating effect (Self Heating Effect) and floater effect
(Floating Body Effect), these effects can influence the performance of SOI device, and component failure can be caused when serious, therefore,
Industry is directed to the self-heating effect and floater effect that how to improve SOI device as study hotspot.Wherein, one kind is referred to as standard
SOI MOSFET element can avoid self-heating effect and floater effect well.Because channel region is connected with Semiconductor substrate,
Avoid self-heating effect and floater effect；Due to being lined with insulating barrier below source-drain area, short-channel effect can be effectively improved.North
The patent of invention (application number 201310697719.0) of capital university Huang Ru professors team proposes one kind and prepares quasi- SOI source and drain effect
The method for answering transistor device, methods described can be applied in the quasi- SOI source and drain High preceding grid techniques of K Metal Gate or rear grid
In prepared by technique MOSFET, it will be clear that methods described has the obvious disadvantage that, the defect mainly has：
1st, source-drain area doped epitaxial in situ will be by source drain extension area side wall as extension inculating crystal layer, because the side wall is
Dry etching is formed, and surface has more lattice defect unavoidably, it is difficult to ensure that not having dislocation (dislocation) hair in epitaxial layer
It is raw, also, the side wall is relied solely on as extension inculating crystal layer, extension speed is slower.
2nd, methods described does not have autoregistration metal silication (Salicide) technique of source-drain area, and this necessarily greatly increases contact
Hole and the contact resistance of source-drain area, it is obviously unreasonable for this nanoscale devices.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of field-effect transistor and its system
Preparation Method, for solving in the prior art because source-drain area doped epitaxial in situ by remote building extension area side wall is used as extension seed crystal
Easily produce defect caused by layer in epitaxial layer, and extension speed it is slow the problem of, and due to no source-drain area
Salicide techniques so that the contact resistance of contact hole and source-drain area is larger, and then the problem of influence nanoscale devices performance.
In order to achieve the above objects and other related objects, embodiments of the invention provide a kind of preparation of field-effect transistor
Method, at least comprises the following steps：
Semiconductor substrate is provided, first grid laminated construction is formed on the semiconductor substrate；
The first side wall is formed in the first grid laminated construction both sides；
Sunk structure is formed on the outside of first side wall；Insulating medium layer is formed in the sunk structure；
Doped epitaxial in situ is carried out, source-drain structure is formed above insulating medium layer, with recessed during the doped epitaxial of progress original position
The Semiconductor substrate fallen on the outside of structure is used as inculating crystal layer；
Isolation structure is formed in the Semiconductor substrate on the outside of the source-drain structure；
In one embodiment, methods described is further comprising the steps of：
Autoregistration metal silication is carried out to the source-drain structure upper surface, metal silicide is formed on the source-drain structure
Layer；
And contact hole and metal interconnection structure are formed on metal silicide layer.
In one embodiment, the first grid laminated construction is from bottom to up successively comprising oxygenation level layer, high dielectric
Constant material layer, work function regulating course and Metal gate layer.
In one embodiment, the first grid laminated construction is false grid, from bottom to up successively comprising gate oxide, many
Crystal silicon layer and grid hard mask layer, methods described further comprise：After source-drain structure is formed, remove the first grid and fold
Rotating fields, and re-form in original position second grid laminated construction, the second grid laminated construction is from bottom to up successively
Include oxygenation level layer, high dielectric constant material layer, work function regulating course and Metal gate layer.
In one embodiment, the first grid laminated construction includes gate oxide, polysilicon layer successively from bottom to up
And grid hard mask layer.
In one embodiment, the sunk structure is U-shaped sunk structure, wherein, the U-shaped sunk structure is by each
Semiconductor substrate described in anisotropy dry etching and formed.
In one embodiment, the sunk structure is Σ type sunk structures, forms the method for the Σ types depression and includes：
U-shaped sunk structure is formed by Semiconductor substrate described in anisotropic dry etch；On the basis of the U-shaped sunk structure
TMAH corrosive liquids are continuing with to corrode the Semiconductor substrate using anisotropic wet and formed；
In one embodiment, the sunk structure is that S types are recessed to form the method for S types depression and include：By each
Semiconductor substrate described in anisotropy dry etching and form U-shaped sunk structure；Institute is leaned in first side wall and the U-shaped depression
State and the second side wall is formed on the wall of first grid laminated construction side side, second side wall is extended to below first side wall；
Carry out isotropic dry etch formation S type depressions；And remove second side wall.
In one embodiment, methods described forms the insulating medium layer by selective deposition so that the insulation
Dielectric layer is only remained in the sunk structure, and the thickness of the insulating medium layer is less than the depth of the sunk structure.
In one embodiment, the specific method for the isolation structure being formed on the outside of the source-drain structure is：Described
Perform etching to form groove on the outside of source-drain structure, the depth of the groove is more than the junction depth of the source-drain structure；And described
Spacer medium material is filled in groove.
In one embodiment, the thickness of source-drain structure is less than 2/3rds of the first grid laminated construction thickness.
The embodiment of the present invention additionally provides a kind of field-effect transistor, and the field-effect transistor is included：
Semiconductor substrate, the Semiconductor substrate upper surface has the gate stack structure with side wall；
Sunk structure, the sunk structure is located at the side wall both sides；
Insulating medium layer, positioned at the sunk structure bottom, the thickness of the insulating medium layer is less than the sunk structure
Depth；
Source-drain structure, the source-drain structure is located above the insulating medium layer, and the source-drain structure is tied with the depression
The Semiconductor substrate on the outside of structure carries out doped epitaxial in situ as inculating crystal layer and formed；And
Isolation structure, is formed in the Semiconductor substrate on the outside of the sunk structure.
In one embodiment, the field-effect transistor is also comprising the metal silicide for being formed at source-drain structure upper surface
Layer.
In one embodiment, the thickness of the source-drain structure is less than 2/3rds of the gate stack structure thickness.
As described above, field-effect transistor of the present invention and preparation method thereof, has the advantages that：By using rear
Isolation technology so that in source-drain area doped epitaxial in situ using the Semiconductor substrate beyond source-drain area as extension inculating crystal layer, effectively
Ground avoids the possibility that there are dislocation defects in the epitaxial layer of formation, substantially increases the quality and speed of extension；Meanwhile, lead to
Cross and carry out autoregistration metal silication (Salicide) technique in source-drain area, significantly reduce the contact electricity of contact hole and source-drain area
Resistance, and then improve the performance of device.
Brief description of the drawings
Fig. 1 is shown as the flow chart of the preparation method of the field-effect transistor provided in the embodiment of the present invention one.
Fig. 2 to Figure 20 is shown as the structural representation of the preparation method of the field-effect transistor provided in the embodiment of the present invention one
Figure.
Figure 21 to Figure 22 is shown as forming in the preparation method of the field-effect transistor provided in the embodiment of the present invention two
The schematic diagram of one gate stack structure.
Figure 23 is shown as in the preparation method of the field-effect transistor provided in the embodiment of the present invention two by chemical machinery
Glossing planarizes the schematic diagram of the first silicon oxide layer.
Figure 24 to Figure 25 is shown as in the preparation method of the field-effect transistor provided in the embodiment of the present invention three in source and drain
The schematic diagram of isolation structure is formed on the outside of structure.
Figure 26 be shown as in the preparation method of the field-effect transistor provided in the embodiment of the present invention three to source-drain structure and
The schematic diagram of autoregistration metal silication is carried out on polysilicon layer.
Component label instructions
1 Semiconductor substrate
2 first grid laminated construction
21 gate oxides
22 polysilicon layers
23 grid hard mask layers
24 oxygenation levels layer
25 high dielectric constant layers
26 power function regulating courses
27 Metal gate layers
31 first side walls
32 second side walls
4 sunk structures
41 insulating medium layers
51 first photoresist layers
511 first openings
52 second photoresist layers
521 second openings
61 source-drain structures
62 isolation structures
7 metal silicides
81 first silicon oxide layers
82 second silicon oxide layers
9 metal interconnection structures
D0The thickness sum of gate oxide and polysilicon layer
D1The thickness of insulating medium layer
D2The thickness of source-drain structure
D3When forming isolation structure the deep trouth bottom that etches to semiconductor substrate surface distance
H1The depth of U-shaped sunk structure
H2The depth that anisotropic wet corrodes during formation Σ type sunk structures
H3The depth of isotropic dry etch during formation S type sunk structures
L1The thickness of second side wall
L2The width of lateral etching during formation S type sunk structures
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Fig. 1 is referred to Figure 26.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, though only display is with relevant component in the present invention rather than according to package count during actual implement in diagram
Mesh, shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout kenel may also be increasingly complex.
Embodiment one
Fig. 1 to Figure 20 is referred to, one embodiment of the present of invention provides a kind of preparation method of field-effect transistor, described
The preparation method of field-effect transistor may be adapted to the preparation of grid technique MOSFET after quasi- SOI source and drain High K Metal Gate, extremely
Comprise the following steps less：
1) Semiconductor substrate 1 is provided, first grid laminated construction 2 is formed in the Semiconductor substrate 1；Wherein, in figure
Show in embodiment, the gate stack structure 2 is false grid, include gate oxide 21, polysilicon layer 22 and grid successively from the bottom to top
Extremely hard mask layer 23；
2) the first side wall 31 is formed in the both sides of first grid laminated construction 2；
3) sunk structure 4 is formed in the outside of the first side wall 31；Insulating medium layer is formed in the sunk structure 4
41；
4) doped epitaxial in situ is carried out, source-drain structure 61 is formed in the top of insulating medium layer 41, doped epitaxial in situ is carried out
When inculating crystal layer is used as using the Semiconductor substrate 1 in the outside of sunk structure 4；
5) isolation structure 62 is formed in the Semiconductor substrate 1 in the outside of source-drain structure 61.
In the illustrated embodiment, the preparation method of the field-effect transistor may also include following optional step：
6) autoregistration metal silication is carried out to the upper surface of source-drain structure 61, formed in the upper surface of source-drain structure 61
Metal silicide layer 7；
7) in step 6) obtained by structure upper surface deposit the first silicon oxide layer 81, first silicon oxide layer 81 it is upper
Surface exceeds the upper surface of the gate stack structure 2；First silicon oxide layer is planarized by CMP process
81；
8) the first grid laminated construction 2 is removed, and it is redeposited in the original position of the first grid laminated construction 2
Second grid laminated construction, the second grid laminated construction can be from bottom to up high-dielectric constant metal grid pole, at one
In embodiment, second grid laminated construction can be included：Oxygenation level layer, high dielectric constant material layer, work function regulating course and gold
Belong to gate layer；
9) metal interconnection structure 9 is formed above metal silicide layer.In other embodiments, methods described may not be wrapped
It is changed containing one or more of above-mentioned optional step, or to the order and particular content of some steps.
In step 1) in, the S1 steps and Fig. 2 to Fig. 3 in Fig. 1 are referred to there is provided Semiconductor substrate 1, using described half
First grid laminated construction 2 is formed on conductor substrate 1；Wherein, the first grid laminated construction 2 is false grid, from the bottom to top according to
It is secondary including gate oxide 21, polysilicon layer 22 and grid hard mask layer 23.
Specifically, in the illustrated embodiment, gate oxide 21, polysilicon layer are sequentially formed in the Semiconductor substrate 1
22 and grid hard mask layer 23, grid hard mask layer 23, polysilicon layer described in photoetching and anisotropic dry etch can be passed through
22 and gate oxide 21 form the first grid laminated construction 2；More specifically, partly led described by thermal oxidation method first
Gate oxide 21 is formed on body substrate 1, the polysilicon layer 22 is deposited secondly by Low Pressure Chemical Vapor Deposition (LPCVD),
Then the grid hard mask layer 23 is used as by Low Pressure Chemical Vapor Deposition deposited silicon nitride, finally by photoetching and it is each to
Grid hard mask layer 23, polysilicon layer 22 and gate oxide 21 form the first grid laminated construction described in different in nature dry etching
2。
Specifically, in certain embodiments, the thickness of the gate oxide 21 can be 5 angstroms~200 angstroms, the polysilicon
The thickness of layer 22 can be 200 angstroms~1000 angstroms, and the thickness of the grid hard mask layer 23 can be 10 angstroms~500 angstroms；It is described
It is D after the thickness of gate oxide 21 and the polysilicon layer 220。
In step 2) in, S2 steps and Fig. 4 in Fig. 1 are referred to, the is formed in the both sides of first grid laminated construction 2
One side wall 31.
Specifically, in the illustrated embodiment, the specific of the first side wall 31 is formed in the both sides of first grid laminated construction 2
Method can be：First spacer material layer is deposited by Low Pressure Chemical Vapor Deposition, described the is formed by Self-aligned etching
First side wall 31 of the both sides of one gate stack structure 2.
It should be noted that first side wall 31 can be made up of one or more layers material.Particularly, in an implementation
In example, when first side wall 31 is made up of multi-layer material, outermost material is not silica.Preferably, it is illustrated that implement
In example, the material of first side wall 31 is identical with the material of the grid hard mask layer 23, is silicon nitride.
In step 3) in, the S3 steps and Fig. 5 to Figure 10 in Fig. 1 are referred to, forms recessed in the both sides of the first side wall 31
Fall into structure 4；Insulating medium layer 41 is formed in the sunk structure 4.
Specifically, the sunk structure 4 can be U-shaped sunk structure, Σ types sunk structure or S type sunk structures.
Specifically, referring to Fig. 5 to Fig. 6, the specific method of U-shaped sunk structure is formed in the both sides of the first side wall 31
For：The second photoresist layer 52 with the second opening 521, second opening, 521 correspondences are formed in the Semiconductor substrate 1
In the region of the U-shaped sunk structure, as shown in Figure 5；Form described by Semiconductor substrate described in anisotropic dry etch 1
U-shaped sunk structure, the depth of the U-shaped sunk structure is H1, as shown in Figure 6.Particularly, in one embodiment, described half
1 pair of conductor substrate, first side wall 31 and the grid hard mask layer 23 have 5:More than 1 anisotropic dry etch choosing
Select ratio.
Specifically, referring to Fig. 7, the Σ types sunk structure is continuing with the basis of the U-shaped sunk structure
TMAH corrosive liquids corrode the Semiconductor substrate 1 using anisotropic wet and formed, and the depth of corrosion is H2, H2＞ H1。
Specifically, referring to Fig. 8 to Fig. 9, the S types sunk structure is on the basis of the U-shaped sunk structure, in institute
First side wall 31 and the U-shaped depression on the side wall of the side of first grid laminated construction 2 by forming the second side wall 32, described second
Side wall 32 extends to the lower section of the first side wall 31.After the second side wall 32 is completed, isotropic dry etch formation S types are carried out
Depression, finally removes the second side wall 32.
When forming the second side wall 32, the material of the second side wall 32 is deposited by LPCVD first；Thereafter by chemical vapor deposition
Area method and anisotropic dry etch form second side wall 32, and the width of second side wall 32 is L1, as shown in figure 8,
The material of second side wall 32 is different from the material of first side wall 31 and it has 1 to the Semiconductor substrate 1:5 with
Under anisotropic dry etch selection ratio, is then formed by Semiconductor substrate described in isotropic dry etch 1, longitudinally
Etching depth is H3, lateral etching width is L2, L2＞ L1, while removing second side wall by isotropism wet etching
32, as shown in Figure 9.
Specifically, being formed in the sunk structure 4 before insulating medium layer 41, in addition it is also necessary to the structure is carried out clear
Wash, to remove remnants second photoresist layer 52.
It should be noted that the sunk structure either U-shaped sunk structure, Σ types sunk structure or S type sunk structures,
Its follow-up preparation process is similar, and follow-up preparation technology is by taking U-shaped sunk structure as an example in the present embodiment, for other two kinds
The rear continuous preparation of sunk structure is not repeated herein.
Specifically, insulating medium layer 41 described in selective deposition, the i.e. insulating medium layer 41 in deposition to deposition
Carry out Soft lithograph (soft etch) so that final only to retain one layer of insulating medium layer 41 in the sunk structure 4.Institute
41 pairs of the insulating medium layer Semiconductor substrate 1, the first side wall 31 and the grid hard mask layer 23 are stated with 5:More than 1 it is soft
Etching selection ratio；The thickness D of the insulating medium layer 411Less than the depth H of the sunk structure1。
In step 4) in, S4 steps and Figure 11 in Fig. 1 are referred to, doped epitaxial in situ is carried out, in the dielectric
Layer top forms source-drain structure 61, and doped epitaxial in situ is with the outside of sunk structure 4 (i.e. away from first grid laminated construction one
Side) the Semiconductor substrate 1 be used as inculating crystal layer.
Specifically, the thickness D of the source-drain structure 612D should be met2＜ 2/3D0, it is preferable that in the present embodiment, the source
The thickness D of drain structure 612D should be met2＜ 1/2D0.In the present invention, because the doped epitaxial in situ is tied with the depression
The Semiconductor substrate 1 in the outside of structure 4 is extension inculating crystal layer so that the quality and speed of extension are greatly improved.
In step 5) in, the S5 steps and Figure 12 to Figure 15 in Fig. 1 are referred to, half in the outside of insulating medium layer 41
Isolation structure 62 is formed in conductor substrate 1.
Specifically, in the illustrated embodiment, the specific method of isolation structure 62 is formed in the outside of insulating medium layer 41
For：First in step 4) obtained by structure upper surface formed the first photoresist layer 51, in 51 pairs of first photoresist layer
The first opening 511 should be formed at the position of isolated area；The source-and-drain junction of the isolated area is removed secondly by dry etching
Structure 61 and the part Semiconductor substrate 1 remove first photoresist layer 51 and cleaned to required depth；Then,
The second silicon oxide layer 82 is deposited in the upper surface of the structure；Finally, the second silicon oxide layer 82 described in dry etching is to the source
The surface of drain structure 61.
Specifically, in the dry etching etching process, the distance from bottom of the deep trouth of the depth formation needed for being etched to
The upper surface of Semiconductor substrate 1 apart from D3More than H1-D1, it is preferable that in the present embodiment, the distance from bottom institute of the deep trouth
State the upper surface of Semiconductor substrate 1 apart from D3For 500 angstroms~2000 angstroms.
In optional step 6) in, it is preferred that Figure 16 is referred to, to carrying out autoregistration metal silication on the epitaxial layer 61,
Metal silicide layer 7 is formed in the upper surface of source-drain structure 61.
Specifically, the material of the metal silicide layer 7 can be nickel silicide.By carrying out autoregistration gold in source-drain area
Belong to silication (Salicide) technique, significantly reduce the contact resistance of contact hole and source-drain area, and then improve the property of device
Energy.
In optional step 7) in, it is preferred that Figure 17 to Figure 18 is referred to, in step 6) obtained by structure upper surface deposition
First silicon oxide layer 81, the upper surface of first silicon oxide layer 81 exceeds the upper surface of the first grid laminated construction 2；It is logical
Cross CMP process and planarize first silicon oxide layer 81.
Specifically, using Low Pressure Chemical Vapor Deposition in step 6) obtained by the upper surface of structure deposit first oxygen
SiClx layer 81.
Specifically, in the illustrated embodiment, in CMP process, removing unnecessary first silicon oxide layer 81
And the grid hard mask layer 23, last CMP process stops at the surface of the polysilicon layer 22.
In optional step 8) in, it is preferred that refer to Figure 19, remove the first grid laminated construction 2, and described the
Redeposited second grid laminated construction on the original position of one gate stack structure 2.
Specifically, removing the polysilicon layer 22 and the gate oxide 21 successively by wet etching.
Specifically, in one embodiment, the second grid laminated construction is high-dielectric constant metal grid pole, by it is lower extremely
On include oxygenation level layer 24, high dielectric constant layer 25, work function regulating course 26 and Metal gate layer 27 successively.In the first grid
The specific method of redeposited high-dielectric constant metal grid pole is on the original position of pole laminated construction 2：Pass through situ steam oxygen first
Change method forms the oxygenation level layer 24；Secondly by atomic layer deposition method (ALD) the formation high dielectric constant layer 25；Then
The work function regulating course 26 is formed by atomic layer deposition method；Finally by physical vaporous deposition (PVD) the formation gold
Belong to gate layer 27.
Specifically, in one embodiment, the thickness of the oxygenation level layer 24 can be 3 angstroms~20 angstroms；The Gao Jie
The material of permittivity layers 25 can be hafnium base or zirconium-based metallic oxide, and its thickness can be 10 angstroms~100 angstroms；The work function
The material of regulating course 26 can be titanium nitride, and its thickness can be 10 angstroms~100 angstroms；The material of the Metal gate layer 27 can be
Aluminium, titanium or tungsten, its thickness can be 200 angstroms~2000 angstroms.
In optional step 9) in, it is preferred that Figure 20 is referred to, in step 8) obtained by structure on form contact hole and gold
Belong to interconnection structure 9.
Embodiment two
Figure 21 to Figure 23 is referred to, another embodiment of the present invention provides a kind of preparation method of field-effect transistor,
The preparation method of the field-effect transistor may be adapted to the system of grid technique MOSFET before quasi- SOI source and drain High K Metal Gate
It is standby, at least comprise the following steps：
1) Semiconductor substrate 1 is provided, first grid laminated construction is formed in the Semiconductor substrate 1 using preceding grid technique
2；Wherein in the illustrated embodiment, the first grid laminated construction 2 is true grid, includes oxygenation level layer successively from the bottom to top
24th, high dielectric constant layer 25, work function regulating course 26 and Metal gate layer 27；
2) the first side wall 31 is formed in the both sides of first grid laminated construction 2；
3) sunk structure 4 is formed in the outside of the first side wall 31；Insulating medium layer is formed in the sunk structure 4
41；
4) doped epitaxial in situ is carried out, source-drain structure 61 is formed in the top of insulating medium layer 41, doped epitaxial in situ is carried out
When inculating crystal layer is used as using the Semiconductor substrate 1 in the outside of sunk structure 4；
5) isolation structure 62 is formed in the Semiconductor substrate 1 in the outside of source-drain structure 61；
In the illustrated embodiment, the preparation method of the field-effect transistor may also include following optional step：
6) autoregistration metal silication is carried out to the upper surface of source-drain structure 61, formed in the upper surface of source-drain structure 61
Metal silicide layer 7；
7) in step 6) obtained by structure upper surface deposit the first silicon oxide layer 81, first silicon oxide layer 81 it is upper
Surface exceeds the upper surface of the gate stack structure 2；First silicon oxide layer is planarized by CMP process
81；
8) metal interconnection structure 9 is formed above metal silicide layer.
In other embodiments, methods described may not include one or more of above-mentioned optional step, or to some
The order and particular content of step are changed.
In step 1) in, Figure 21 to Figure 22 is referred to there is provided Semiconductor substrate 1, using preceding grid technique in the semiconductor
First grid laminated construction 2 is formed on substrate 1；Wherein, it is illustrated that in embodiment, the first grid laminated construction 2 is true grid, by
Under supreme include oxygenation level layer 24, high dielectric constant layer 25, work function regulating course 26 and Metal gate layer 27 successively.
Specifically, in the illustrated embodiment, forming the oxygenation level layer 24 by situ steam oxidizing process first；Secondly
Pass through atomic layer deposition method (ALD) the formation high dielectric constant layer 25；The work content is formed again by atomic layer deposition method
Number regulating course 26；Then by physical vaporous deposition (PVD) the formation Metal gate layer 27, finally by photoetching and etching institute
State Metal gate layer 27, work function regulating course 26, high dielectric constant layer 25 and oxygenation level layer 24 and form the gate stack structure
2。
Specifically, the thickness of the oxygenation level layer 24 can be 3 angstroms~20 angstroms；The material of the high dielectric constant layer 25 can
Think hafnium base or zirconium-based metallic oxide, its thickness can be 10 angstroms~100 angstroms；The material of the work function regulating course 26 can be
Titanium nitride, its thickness can be 10 angstroms~100 angstroms；The material of the Metal gate layer 27 can be aluminium, titanium or tungsten, and its thickness can be
200 angstroms~2000 angstroms.
In the present embodiment, step 2)~step 6) preparation method it is identical with embodiment one, can be refering to embodiment one
Description, is not repeated herein.
In optional step 7) in, Figure 23 is referred to, in step 6) obtained by structure upper surface deposit the first silicon oxide layer
81, the upper surface of first silicon oxide layer 81 exceeds the upper surface of the gate stack structure 2；By chemically-mechanicapolish polishing work
Skill planarizes first silicon oxide layer 81.
Specifically, using Low Pressure Chemical Vapor Deposition in step 6) obtained by the upper surface of structure deposit first oxygen
SiClx layer 81.
Specifically, in CMP process, removing unnecessary first silicon oxide layer 81, last chemical machinery is thrown
Light technique stops at the surface of the Metal gate layer 27.
Embodiment three
Figure 24 to Figure 26 is referred to, further embodiment of this invention also provides a kind of preparation method of field-effect transistor, institute
The preparation method for stating field-effect transistor may be adapted to quasi- SOI source and drain regular grid MOSFET preparation, at least comprise the following steps：
1) Semiconductor substrate 1 is provided, first grid laminated construction is formed in the Semiconductor substrate 1 using common process
2, the first grid laminated construction 2 includes gate oxide 21, polysilicon layer 22 and grid hard mask layer 23 successively from the bottom to top；
2) the first side wall 31 is formed in the both sides of first grid laminated construction 2；
3) sunk structure 4 is formed in the outside of the first side wall 31；Insulating medium layer is formed in the sunk structure 4
41；
4) doped epitaxial in situ is carried out, source-drain structure 61 is formed in the top of insulating medium layer 41, doped epitaxial in situ is carried out
When inculating crystal layer is used as using the Semiconductor substrate 1 in the outside of sunk structure 4；
5) isolation structure 62 is formed in the Semiconductor substrate 1 in the outside of source-drain structure 61；
In the illustrated embodiment, the preparation method of the field-effect transistor may also include following optional step：
6) autoregistration metal silication is carried out to the source-drain structure 61 and the upper surface of the polysilicon layer 22, in the source and drain
Structure 61 and the upper surface of the polysilicon layer 22 form metal silicide layer 7；
7) in step 6) obtained by structure upper surface deposit the first silicon oxide layer 81, first silicon oxide layer 81 it is upper
Surface exceeds the upper surface of the gate stack structure 2；First silicon oxide layer is planarized by CMP process
81；
8) metal interconnection structure 9 is formed above metal silicide layer..
In the present embodiment, step 1) to step 4) preparation method it is identical with embodiment one, embodiment one can be referred to
Description, be not repeated herein.
It should be noted that in step 1) in, the gate stack structure 2 formed in the present embodiment is true grid.
In step 5) in, refer to Figure 24 to Figure 25, formed in the Semiconductor substrate 1 in the outside of the source-drain structure 61 every
From structure 62.
Specifically, being in the specific method that the outside of insulating medium layer 41 forms isolation structure 62：First in step 4)
The upper surface of resulting structure forms the first photoresist layer 51, corresponds to the position of isolated area in first photoresist layer 51
Place forms the first opening 511；The source-drain structure 61 and the part described half of the isolated area are removed secondly by dry etching
Conductor substrate 1 removes first photoresist layer 51 and cleaned to required depth；Again, in the upper table of the structure
Face deposits the second silicon oxide layer 82；Then, by CMP process remove unnecessary second silicon oxide layer 82 and
The grid hard mask layer 23, CMP process is eventually stopped on the polysilicon layer 22；Finally, based on the time
(by-time) the second silicon oxide layer 82 described in dry etching is to the surface of the source-drain structure 61.
Specifically, in the dry etching etching process, the distance from bottom of the deep trouth of the depth formation needed for being etched to
The upper surface of Semiconductor substrate 1 apart from D3More than H1-D1, it is preferable that in the present embodiment, the distance from bottom institute of the deep trouth
State the upper surface of Semiconductor substrate 1 apart from D3For 500 angstroms~2000 angstroms.
In optional step 6) in, Figure 26 is referred to, to being carried out on the source-drain structure 61 and the polysilicon layer 22 from right
Metalloid silication, forms metal silicide layer 7 on the source-drain structure 61 and the polysilicon layer 22.
Specifically, the material of the metal silicide layer 7 can be nickel silicide, cobalt silicide or Titanium silicide.Pass through
Autoregistration metal silication (Salicide) technique is carried out in source-drain area, the contact electricity of contact hole and source-drain area is significantly reduced
Resistance, and then improve the performance of device.
In step 7) in, in step 6) obtained by structure upper surface deposit the first silicon oxide layer 81, it is described first oxidation
The upper surface of silicon layer 81 exceeds the upper surface of the gate stack structure 2；Described is planarized by CMP process
One silica layer 81.
Specifically, specifically, using Low Pressure Chemical Vapor Deposition in step 6) obtained by structure upper surface deposition institute
State the first silicon oxide layer 81.
Specifically, in CMP process, removing unnecessary first silicon oxide layer 81, last chemical machinery is thrown
Light technique stops at the surface of the metal silicide 7.
Example IV
Please continue to refer to Figure 19, a kind of field-effect transistor is also provided in the present embodiment, the field-effect transistor is at least
Including：Semiconductor substrate 1, the upper surface of Semiconductor substrate 1 has the gate stack structure of the first side wall of band 31；
Sunk structure (not shown), the sunk structure is located at the both sides of the first side wall 31；
Insulating medium layer 41, positioned at the sunk structure bottom, the thickness of the insulating medium layer 41 is less than the depression
Constructional depth；
Source-drain structure 61, the source-drain structure 61 is located at the top of insulating medium layer 41, and the source-drain structure 61 is with institute
The Semiconductor substrate 1 on the outside of sunk structure is stated to be formed as inculating crystal layer progress doped epitaxial in situ；And
Isolation structure 62, is formed in the Semiconductor substrate 1 on the outside of the sunk structure.
Specifically, the gate stack structure includes oxygenation level layer 24, high dielectric constant layer 25, work(successively from the bottom to top
Function regulating course 26 and Metal gate layer 27.The thickness of the oxygenation level layer 24 can be 3 angstroms~20 angstroms；The high dielectric constant layer
25 material can be hafnium base or zirconium-based metallic oxide, and its thickness can be 10 angstroms~100 angstroms；The work function regulating course 26
Material can be titanium nitride, and its thickness can be 10 angstroms~100 angstroms；The material of the Metal gate layer 27 can be aluminium, titanium or tungsten, its
Thickness can be 200 angstroms~2000 angstroms.
Specifically, first side wall 31 can be made up of one or more layers material.Particularly, in one embodiment,
When first side wall 31 is made up of multi-layer material, outermost material is not silica.Preferably, it is illustrated that in embodiment,
The material of first side wall 31 is identical with the material of the grid hard mask layer 23, is silicon nitride.
Specifically, can be with continued reference to embodiment one and Fig. 5 to Fig. 9, the sunk structure, can for U-shaped sunk structure,
Σ types sunk structure or S type sunk structures.
Specifically, the insulating medium layer 41 is formed by selective deposition, i.e., in deposition to the described exhausted of deposition
Edge dielectric layer 41 carries out Soft lithograph (soft etch) so that final only one layer of the reservation insulation is situated between in the sunk structure
Matter layer 41.41 pairs of the insulating medium layer Semiconductor substrate 1, the first side wall 31 have 5:More than 1 Soft lithograph selection ratio；
The thickness of the insulating medium layer 41 is less than the depth of the sunk structure.
Specifically, the thickness of the source-drain structure 61 is less than 2/3rds of the gate stack structure thickness.
Specifically, the field-effect transistor also includes metal silicide layer 7, the metal silicide layer 7 is located at described
The upper surface of source-drain structure 61.Specifically, the material of the metal silicide layer 7 can be nickel silicide.By entering in source-drain area
Row autoregistration metal silication (Salicide) technique, significantly reduces the contact resistance of contact hole and source-drain area, and then improve
The performance of device.
Embodiment five
Please continue to refer to Figure 26, the present embodiment also provides a kind of field-effect transistor, the structure of the field-effect transistor
Structure with the field-effect transistor described in example IV is roughly the same, and the difference of the two is：In the present embodiment, the grid
Pole laminated construction includes gate oxide 21 and polysilicon layer 22 successively from the bottom to top；And the metal silicide layer 7 is positioned at described
The upper surface of source-drain structure 61 and affiliated gate stack structure.
In summary, the present invention provides a kind of field-effect transistor and preparation method thereof, by using rear isolation technology, makes
Obtain in source-drain area doped epitaxial in situ using the Semiconductor substrate beyond source-drain area as extension inculating crystal layer, efficiently avoid in shape
Into epitaxial layer in there is the possibility of dislocation defects, substantially increase the quality and speed of extension；Meanwhile, by entering in source-drain area
Row autoregistration metal silication (Salicide) technique, significantly reduces the contact resistance of contact hole and source-drain area, and then improve
The performance of device.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (14)
1. a kind of preparation method of field-effect transistor, it is characterised in that comprise the following steps：
Semiconductor substrate is provided, first grid laminated construction is formed on the semiconductor substrate, in the first grid lamination
Structure both sides form the first side wall；
Sunk structure is formed in the part Semiconductor substrate on the outside of first side wall, is formed in the sunk structure
Insulating medium layer；
Doped epitaxial in situ is carried out, source-drain structure is formed above the insulating medium layer, the doped epitaxial in situ is with described
The Semiconductor substrate on the outside of sunk structure is used as inculating crystal layer；And
Isolation structure is formed in the Semiconductor substrate on the outside of the source-drain structure.
2. the preparation method of field-effect transistor as claimed in claim 1, it is characterised in that methods described also includes：
Autoregistration metal silication is carried out in the source-drain structure upper surface, metal silicide layer is formed on the source-drain structure；
And
Metal interconnection structure is formed above the metal silicide layer.
3. the preparation method of field-effect transistor as claimed in claim 1, it is characterised in that the first grid laminated construction
From bottom to up successively comprising oxygenation level layer, high dielectric constant material layer, work function regulating course and Metal gate layer.
4. the preparation method of field-effect transistor as claimed in claim 1, it is characterised in that the first grid laminated construction
It is false grid, includes gate oxide, polysilicon layer and grid hard mask layer successively from bottom to up, methods described further comprises：
Formed after source-drain structure, remove the first grid laminated construction, and re-form in original position second grid lamination knot
Structure, the second grid laminated construction is from bottom to up successively comprising oxygenation level layer, high dielectric constant material layer, work function regulation
Layer and Metal gate layer.
5. the preparation method of field-effect transistor as claimed in claim 1, it is characterised in that the first grid laminated construction
Include gate oxide, polysilicon layer and grid hard mask layer successively from bottom to up.
6. the preparation method of field-effect transistor according to claim 1, it is characterised in that：The sunk structure is U-shaped
Sunk structure, wherein, the U-shaped sunk structure is formed by Semiconductor substrate described in anisotropic dry etch.
7. the preparation method of field-effect transistor according to claim 1, it is characterised in that the sunk structure is Σ types
Sunk structure, forming the method for the Σ types depression includes：
U-shaped sunk structure is formed by Semiconductor substrate described in anisotropic dry etch；
TMAH corrosive liquids are continuing with the basis of the U-shaped sunk structure semiconductor is corroded using anisotropic wet
Substrate and form Σ types depression.
8. the preparation method of field-effect transistor according to claim 1, it is characterised in that the sunk structure is S types
Depression, forming the method for the S types depression includes：
U-shaped sunk structure is formed by Semiconductor substrate described in anisotropic dry etch；
In first side wall and the U-shaped depression by forming the second side wall on the wall of the first grid laminated construction side side,
Second side wall is extended to below first side wall；
Carry out isotropic dry etch formation S type depressions；And
Remove second side wall.
9. the preparation method of field-effect transistor according to claim 1, it is characterised in that：Formed by selective deposition
The insulating medium layer so that the insulating medium layer is only remained in the sunk structure, the thickness of the insulating medium layer
Less than the depth of the sunk structure.
10. the preparation method of field-effect transistor according to claim 1, it is characterised in that outside the source-drain structure
The specific method that side forms the isolation structure is：
Perform etching to form groove on the outside of the source-drain structure, the depth of the groove is more than the junction depth of the source-drain structure；
And
Spacer medium material is filled in the groove.
11. the preparation method of field-effect transistor according to claim 1, it is characterised in that the thickness of the source-drain structure
2/3rds of degree less than the first grid laminated construction thickness.
12. a kind of field-effect transistor, it is characterised in that the field-effect transistor is included：
Semiconductor substrate, the Semiconductor substrate upper surface has the gate stack structure with side wall；
Sunk structure, the sunk structure is located at the side wall both sides；
Insulating medium layer, positioned at the sunk structure bottom, the thickness of the insulating medium layer is less than the sunk structure depth；
Source-drain structure, the source-drain structure be located at the insulating medium layer above, the source-drain structure with the sunk structure outside
The Semiconductor substrate of side carries out doped epitaxial in situ as inculating crystal layer and formed；
Isolation structure, is formed in the Semiconductor substrate on the outside of the source-drain structure.
13. field-effect transistor as claimed in claim 12, it is characterised in that the field-effect transistor is also included and is formed at
The metal silicide layer of source-drain structure upper surface.
14. field-effect transistor as claimed in claim 12, it is characterised in that the thickness of the source-drain structure is less than the grid
2/3rds of pole laminated construction thickness.
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| CP03 | Change of name, title or address |
Address after: 401331 No. 25 Xiyong Avenue, Shapingba District, Chongqing Patentee after: Huarun Microelectronics (Chongqing) Co., Ltd. Address before: 401331 No. 25 Xiyong Avenue, Xiyong Town, Shapingba District, Chongqing Patentee before: China Aviation (Chongqing) Microelectronics Co., Ltd. |