CN104581134A - Video signal resolution detection device and method - Google Patents
Video signal resolution detection device and method Download PDFInfo
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Abstract
The embodiment of the invention discloses a video signal resolution detection method which comprises the following steps of inputting a video signal and a row and field synchronization signal; detecting the input signals, performing dejitter filtering after the 1-bit row and field synchronization signal is extended to W bits if the input video signal is a VGA (Video Graphics Array) signal, otherwise directly performing dejitter filtering on the input row and field synchronization signal; detecting the polarity Hp and Vp of the row and field synchronization signal, and simultaneously performing counting to obtain the widths Hcount and Vcount of the row and field synchronization signal; obtaining the current resolution of the video signal by adopting a quadruple time sharing judgment method. The invention further discloses a detection device based on the method. According to the scheme, the quadruple time sharing judgment method is used for a judgment and decision-making machine, so that the shortcomings of an ordinary resolution detection system in terms of accuracy and compatibility are overcome, and meanwhile, the cost of a chip is lowered.
Description
Technical field
The present invention relates to the automatic detection field of a kind of resolution to incoming video signal, be specifically related to the field that VGA and the YPbPr vision signal resolution of input is detected automatically.
Background technology
Along with electronic product becomes increasingly abundant, the equipment possessing VGA (video graphics array) interface or YPbPr (color difference components) interface gets more and more, such as PC, MAC, video camera and DVD etc.In the fields such as multimedia teaching, interactive training, video conferencing system, require that VGA or the YPbPr signal by the equipment such as computing machine and DVD exports is converted to TV (television video) signal.
VGA (Video Graphics Array) namely shows drawing array, is the computer display standard of the use simulating signal that IBM proposed in 1987.The composition of VGA signal is divided into five kinds: RGBHV, is red green blue tricolor and row field sync signal respectively, namely has independent line synchronizing signal and field sync signal.
YPbPr is also color difference components interface, employing be EIA EIA-770.2a standard, be one line by line scan aberration export.And the carrier chrominance signal P that aberration exports S-Video transmits is decomposed into aberration Pr and Pb, doing so avoids two-way aberration hybrid decoding and the process be again separated, also maintain the maximum bandwidth of chrominance channel, and namely Y is luminance signal.YPbPr does not have independent synchronizing signal interface, and its synchronizing signal compound is transmitted in video signals.
In VGA/YPbPr-TV Video Quality Metric chip, need VGA/YPbPr signal difference being inputted resolution after the process such as Scaler, frame rate conversion, the CVBS signal being encoded to standard exports.VGA/YPbPr signal input resolution is more, and whether correctly the detection of resolution determines follow-up various process, is the prerequisite that whole conversion chip normally works.At present, the detection of resolution is all by carrying out sample count to the horizontal-drive signal of all resolution and vertical synchronizing signal, the information obtaining line of input field sync signal comprises row/field system chronizing impulse time, continuous and effective level time and sweep time, and it is set up resolution information table, during detection resolution, the value stored in input resolution information and resolution information table is contrasted, thus obtain the resolution of current input.The method of existing detection resolution has following deficiency:
The VGA signal of the separate rows field input meeting VESA standard can only be detected, the signal of YPbPr and so on compound row field input can not be detected, not support that VGA/YPbPr detects while inputting resolution.
Due to the difference of picture output device, the resolution information table set up by means of only row/field system chronizing impulse time, continuous and effective level time and sweep time can not distinguish the very close resolution of line frequency, field frequency exactly, can reduce the accuracy of detection.Simultaneously for the same resolution that distinct device exports, line frequency, field frequency also have the difference of certain degree, if with the row in resolution information table/field system chronizing impulse time, continuous and effective level time and judge sweep time to cause resolution to judge by accident, cause the poor compatibility detected.
Common resolution information table wants storage line lock in time, significant level time and total sweep time, and the corresponding one group of form of each resolution, needs storage space and the Compare Logic of at substantial.
Summary of the invention
In view of this, be necessary to provide one can detect VGA and YPbPr simultaneously and input resolution, accuracy and compatibility better, and don't expend the method for detection resolution and the device of too many resource.
Embodiments provide a kind of vision signal resolution detection method, the method comprises the steps:
Step S100: incoming video signal and row field sync signal;
Step S101: judge that input signal is VGA signal or YPbPr signal; If incoming video signal is VGA signal, then enter step S102, otherwise enter step S103;
Step S102: the multibit signal row field sync signal of 1 bit all being expanded to W position, wherein W is positive integer;
Step S103: Key dithering filtering process is carried out to the synchronizing signal of input;
Step S104: according to the row field sync signal after Key dithering filtering process, the polarity Hp of detect lines field sync signal and Vp, count to get width Hcount and Vcount of row field sync signal;
Step S105: the determination methods adopting quadruple timesharing, obtains the resolution of current vision signal.
Described step S104 also comprises the steps:
Step S400: the row field sync signal after input Key dithering filtering process;
Step S401: cut level value slicr_lv by register configuration one;
Step S402: field sync signal deducts clipping level slice_lv, obtains the field sync signal Vt after cutting;
Step S403: line synchronizing signal deducts clipping level slice_lv, obtains the line synchronizing signal Hout cutting rear reconstruction;
Step S404: the field sync signal Vt after cutting obtains the field sync signal Vout of reconstruction by integrating circuit;
Step S405: the polarity judging row field sync signal Hout and the Vout rebuild, exports Hp and Vp;
Step S406: count to get the Hcount that counts in a line;
Step S407: count to get the line number Vcount in.
A step is also comprised: exported after low-pass filter by input signal between described step S400 and step S401.
Described step S401 also replaces by following steps:
Find out the minimum value of the capable signal of N;
The bias voltage Reg_b that this minimum value and is arranged is added, obtains clipping level value slice_lV.
Described step S105 also comprises the steps:
Step S501: by four of current detection resolution informations: capable synchronous width Hcount, field synchronization width Vcount and row synchronous polarity Hp, Vp compare one by one with the relevant parameter in resolution information table, if compare difference all within an error margin value with four of a kind of resolution, then with this resolution match, coupling number adds 1; Otherwise do not mate;
Described resolution information table stores the row field polarity of each VGA signal and YPbPr signal, capable synchronous width and field synchronization width four values;
If coupling number is 1, the resolution of this coupling is the resolution of incoming video signal;
If coupling number is greater than 1, enter step S502; If coupling number is zero, enter step S503;
Step S502: after reducing error margin value according to the step-length of a setting, repeat step S501;
Step S503: by two of current detection resolution informations: row synchronous width Hcount and field synchronization width Vcount compares one by one with the relevant parameter in resolution information table, if compare difference all within an error margin value with four of a kind of resolution, then with this resolution match, coupling number adds 1; Otherwise do not mate;
When coupling number is 1, then detect successfully; If coupling number is greater than 1, then enter step S504; If coupling number is zero, then detect failure;
Step S504: reduce error margin value according to the step-length of a setting, repeat step S503.
The step-length set in described step S502 and step S504 is equal.
A kind of vision signal resolution pick-up unit, this device comprises: input source detecting unit, row field Bits Expanding unit, Key dithering filter unit, row field polarity and width detection unit, quadruple timesharing judging unit; Wherein,
Described input source detecting unit, for detecting input signal, judges that input signal is VGA signal or YPbPr signal;
Described row field Bits Expanding unit, for all extending to W position by the line synchronizing signal of a bit and field sync signal;
Described Key dithering filter processing unit, comprises a wave filter, for removing the jittering noise in row field sync signal;
Described row field polarity and width detection unit, for polarity Hp and the Vp of detect lines field sync signal, simultaneously by counting to get width Hcount and Vcount of row field sync signal;
Described quadruple timesharing judging unit, for according to the row field polarity Hp detected and count to get and Vp, row synchronous width Hcount and field synchronization width Vcount, adopts the determination methods of quadruple timesharing, obtains the resolution of current vision signal.
Described row field polarity and width detection unit also comprise:
Clipping level generation unit, for cutting level value slicr_lv by register configuration one;
Field synchronization cutter unit, for field sync signal is deducted clipping level slice_lv, obtains the field sync signal Vt after cutting;
The synchronous reconstruction unit of row, for line synchronizing signal is deducted clipping level slice_lv, obtains the line synchronizing signal Hout cutting rear reconstruction;
Field synchronization reconstruction unit, for the field sync signal Vout being obtained by integrating circuit rebuilding by the field sync signal Vt after cutting;
Row synchronous counting unit, for by a counter, counts to get the Hcount that counts in a line;
Field synchronization counting unit, for by a counter, counts to get the line number Vcount in;
Row field polarity judging unit, for judging the polarity of row field sync signal Hout and the Vout rebuild, exports Hp and Vp.
Described clipping level generation unit also can be replaced:
Clipping level computing unit, comprising:
Minimum value unit, for finding out the minimum value of the capable signal of N;
Superpositing unit, is added for the bias voltage Reg_b this minimum value and arranged, obtains clipping level value slice_lv.
Described row field polarity and width detection unit also comprise two low-pass filters, input after carrying out low-pass filtering to input signal.
Described quadruple timesharing judging unit also comprises:
First judging unit, comprises comparing unit one, resolution information table and control module one, wherein:
Described comparing unit one, for by four of current detection resolution informations: row synchronous width Hcount, field synchronization width Vcount and row synchronous polarity Hp, Vp compare one by one with the relevant parameter in resolution information table, if compare difference all within an error margin value with four of a kind of resolution, then with this resolution match, coupling number adds 1; Otherwise do not mate;
Described resolution information table is a storage space, for storing the row field polarity of each VGA signal and YPbPr signal, capable synchronous width and field synchronization width four values;
Described control module one, judges for the coupling number obtained according to described comparing unit one, if coupling number is 1, then detects successfully, thinks to detect to obtain the resolution that this resolution is incoming video signal; If coupling number is greater than 1, then start the first tolerance limit reducing unit; If coupling number is zero, then start the second judging unit.
First tolerance limit reducing unit, after reducing error margin value according to the step-length of a setting, inputs the first judging unit;
Second judging unit, comprises comparing unit two, resolution information table, control module two, wherein:
Described comparing unit two, for by two of current detection resolution informations: row synchronous width Hcount and field synchronization width Vcount compares one by one with the relevant parameter in resolution information table, if compare difference all within an error margin value with four of a kind of resolution, then with this resolution match, coupling number adds 1; Otherwise do not mate;
Described resolution information table is the resolution information table in described first judging unit;
Described control module two, judges for the coupling number obtained according to described comparing unit two, if coupling number is 1, then detects successfully; If coupling number is 0, then detect failure; If coupling number is greater than 1, then enter the second tolerance limit reducing unit;
Described second tolerance limit reducing unit, for reducing error margin value according to the step-length of a setting, inputs the second judging unit.
Described first tolerance limit reducing unit and the second tolerance limit reducing unit are same unit.
Pick-up unit described in the embodiment of the present invention and method can detect the resolution of VGA and YPbPr input simultaneously, reducing the horizontal synchronization pulse time in usual resolution information table content, persistent levels significant level time and vertical sync pulse time, under the prerequisite of vertical continuous and effective level time, pass through horizontal-scanning interval, vertical interval, the combination Rule of judgment of the synchronous polarity of row and field synchronization polarity, and the method using quadruple timesharing to judge solves the deficiency of usual resolution adjustment system in accuracy and compatibility, significantly reduce again the cost of chip simultaneously.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described.Apparently, the accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the overall flow figure of a kind of automatic detection resolution method in the specific embodiment of the invention;
Fig. 2 is the concrete implementing procedure figure of row field polarity and width calculation unit in the specific embodiment of the invention;
Fig. 3 is the structured flowchart of specific embodiment of the invention intermediate-resolution pick-up unit;
Fig. 4 is that the one of row field polarity and width detection unit in the specific embodiment of the invention specifically implements structured flowchart;
Fig. 5 is that the another kind of row field polarity and width detection unit in the specific embodiment of the invention specifically implements structured flowchart.
Embodiment
Below in conjunction with accompanying drawing, the present invention is elaborated.
Be a kind of process flow diagram of vision signal resolution detection method as described in Figure 1, the method comprises the steps:
Step S100: incoming video signal and row field sync signal;
Step S101: detect input signal, judges that input signal is VGA signal or YPbPr signal; If incoming video signal is VGA signal, then enter step S102, otherwise enter step S103;
Step S102: the multibit signal row field sync signal of 1 bit all being expanded to W position; Wherein W is positive integer, and expansion makes the figure place of other signals in the figure place of row field sync signal and system be consistent, and such as clipping level slice_lv etc., facilitate the process such as follow-up noise reduction and Key dithering;
Step S103: Key dithering filtering process is carried out to the synchronizing signal of input; If input is VGA signal, then synchronizing signal is the row field sync signal after step S102 expansion, and when input is YPbPr signal, then synchronizing signal comprises row field sync signal and is all compounded on Y-signal, i.e. composite synchronizing signal.
Described Key dithering filtering generally adopts mean filter or IIR filtering etc. to complete; After described Key dithering filtering process, obtain more desirable line synchronizing signal Hin1, field sync signal Vin1.
Step S104: according to the row field sync signal after Key dithering filtering process, the polarity Hp of detect lines field sync signal and Vp, simultaneously by counting to get width Hcount and Vcount of row field sync signal;
Step S105: according to the row field polarity Hp detected and count to get and Vp, and the synchronous width Hcount of the row counted to get and field synchronization width Vcount, adopt the determination methods of quadruple timesharing, obtain the resolution of current vision signal.
Whether the implementation method of described step S101 has normal composite video signal to input data by detecting composite synchronizing signal input end, thus judges whether input signal is YPbPr signal, otherwise is VGA signal;
Whether the implementation method of described step S101 also has normal line synchronizing signal or field sync signal by detect lines synchronizing signal and field sync signal input end, if any being then VGA signal, otherwise is YPbPr signal;
Described step S101 also by while detect lines field sync signal input end and composite synchronizing signal input end all whether have corresponding input signal, because input signal can not be two kinds of signals simultaneously, therefore, uniquely can obtain a kind of input signal detection result.
Described step S104 specifically also can comprise the steps, as shown in Figure 2:
Step S400: the row field sync signal after input Key dithering filtering process;
Step S401: cut level value slicr_lv by register configuration one;
Step S402: field sync signal carries out deducting clipping level slice_lv, obtains the field sync signal Vt after cutting;
Step S403: line synchronizing signal deducts clipping level slice_lv, obtains the line synchronizing signal Hout cutting rear reconstruction;
Step S404: the field sync signal Vt after cutting obtains the field sync signal Vout of reconstruction by integrating circuit;
Step S405: the polarity judging row field sync signal Hout and the Vout rebuild, exports Hp and Vp;
Step S406: count to get the Hcount that counts in a line;
Step S407: count to get the line number Vcount in.
To it should be noted that in described step S401 that clipping level value slicr_lv is except by except register configuration, also obtains by following steps:
Find out the minimum value of the capable signal of N;
The bias voltage Reg_b that this minimum value and is arranged is added, obtains clipping level value slice_lv.
The level value calculated by said method meets the vision signal of current input more, thus can cut more preparatively and obtain desirable synchronizing signal.
Also a step can be comprised: exported after low-pass filter by input signal between described step S400 and step S401;
In described step S105, the determination methods of quadruple timesharing comprises the steps:
Step S501: within a judgement cycle, by four of current detection resolution informations: row synchronous width Hcount, field synchronization width Vcount and row synchronous polarity Hp, Vp compare one by one with the relevant parameter in resolution information table, if compare difference all within an error margin value with four of a kind of resolution, then with this resolution match, coupling number adds 1; Otherwise do not mate;
Judge the coupling number obtained, if coupling number is unique, then detect successfully, think that detection obtains the resolution that this resolution is incoming video signal;
If coupling number is greater than 1, enter step S502; If coupling number is zero, enter step S503.
Described resolution information table includes the row field polarity of the present invention's each VGA signal detectable and YPbPr signal, capable synchronous width and field synchronization width four values, described four values are different according to the difference of sample frequency, by register configuration, or write by control system.
Step S502: after reducing error margin value according to the step-length of a setting, repeat the detection of step S501.
Step S503: the parameter judged in step S501 is reduced to two, comprises row synchronous width Hcount and field synchronization width Vcount, repeats the judgement of step S501, obtain the resolution number of mating.That is:
By two of current detection resolution informations: row synchronous width Hcount and field synchronization width Vcount compares one by one with the relevant parameter in resolution information table, if error in the error margin value of a setting, is then thought identical;
If two parameters are all identical, then think and this resolution match success; When coupling number is 1, then think that the resolution of current matching is the resolution of incoming video signal; If when coupling number is greater than 1, then enter step S504; If coupling number is zero, then detect failure, think that the vision signal of current input is not in the category that described resolution information tabular is lifted.
Step S504: after reducing error margin value according to the step-length of a setting, repeat the judgement of step S503.
It should be noted that described step S502 can be identical with the step-length in S504, also can adopt different step-lengths.
Generally, after step S501 and step S502, the resolution of current video signal can be judged uniquely, step S503 and step S504 can judge the resolution that some departs from video standard larger, because the condition relaxing judgement can the farthest resolution that exports of compatible distinct device.
Based on above-mentioned vision signal resolution detection method, the invention allows for a kind of vision signal resolution pick-up unit, the one being illustrated in figure 3 this device specifically implements structured flowchart, and this device comprises input source detecting unit 101, row field Bits Expanding unit 102, Key dithering filter unit 103, row field polarity and width detection unit 104, quadruple timesharing judging unit 105, wherein, input signal is line synchronizing signal Hin, field sync signal Vin and composite synchronizing signal Yin, and described line of input synchronizing signal Hin, field sync signal Vin input to input source detecting unit 101 and row field Bits Expanding unit 102, composite synchronizing signal Yin inputs to input source detecting unit 101 and Key dithering filter unit 103 respectively, row field sync signal after described row field Bits Expanding unit 102 exports expansion inputs to described Key dithering filter unit 103, described input source detecting unit 101 output detections consequential signal is to described row field polarity and width detection unit 104 and described quadruple timesharing judging unit 105, row field sync signal after described Key dithering filter unit 103 output filtering and composite synchronizing signal are to described row field polarity and width detection unit 104, obtain row field polarity number Hp and Vp and line width angle value Hcount and field width angle value Vcount and input to described quadruple timesharing judging unit 105, obtain the resolution type of final VGA signal or YPbPr signal.
Wherein, whether described input source detecting unit 101 has normal composite video signal to input data by detecting composite synchronizing signal input end, thus judges whether input signal is YPbPr signal, otherwise is VGA signal;
Whether described input source detecting unit 101 also has normal line synchronizing signal or field sync signal by detect lines synchronizing signal and field sync signal input end, if any being then VGA signal, otherwise is YPbPr signal;
Described input source detecting unit 101 also by while detect lines field sync signal input end and composite synchronizing signal input end all whether have corresponding input signal.
The line synchronizing signal of a bit and field sync signal are all extended to W position by described row field Bits Expanding unit 102, be convenient to the process such as filtering and cutting in later stage, obtain more desirable and row field sync signal accurately, thus detect the resolution obtaining incoming video signal more exactly.
Described Key dithering filter processing unit 103, for removing the jittering noise in row field sync signal, can be a mean filter, and other has the wave filter of equal filter effect also to can be iir filter etc.After described Key dithering filter unit 103, obtain more desirable line synchronizing signal Hin1, field sync signal Vin1 and composite synchronizing signal Yin1.
The one being illustrated in figure 4 described row field polarity and width detection unit 104 specifically implements structured flowchart, and this unit comprises clipping level generation unit 401, field synchronization cutter unit 402, row synchronous reconstruction unit 403, field synchronization reconstruction unit 404, row synchronous counting unit 405, field synchronization counting unit 406 and row field polarity judging unit 407, wherein, line synchronizing signal Hin1 after foregoing units process, composite synchronizing signal Yin1 and offset level Reg_b all inputs to described clipping level productive unit 401 and obtains clipping level slice_lv, clipping level slice_lv inputs to described field synchronization cutter unit 402 and the synchronous reconstruction unit 403 of row respectively, field sync signal Vin1 after foregoing units process and composite synchronizing signal Yin1 all inputs to described field synchronization cutter unit 402, field sync signal Vt after described field synchronization cutter unit 402 exports cutting inputs to described field synchronization reconstruction unit 404, obtain rebuilding rear field sync signal Vout and input to described field synchronization counting unit 406 and row field polarity judging unit 407 respectively, line number Vcount in obtaining every and field polarity Vp, described row synchronous reconstruction unit 403 exports line synchronizing signal Hout extremely described row synchronous counting unit 405 and the described row field polarity judging unit 407 regenerated, the Hount and row polarity Hp that counts in often being gone.
Described clipping level generation unit 401 comprises a register configuration unit, by configuration register value configuration cuts level value slice_lv;
In another embodiment, described clipping level generation unit 401 comprises the capable detecting unit of N, a totalizer and a register configuration unit, first the minimum value obtained in the capable data of N is detected by the capable detecting unit of N, configure a bias voltage Reg_b by configuration register simultaneously, described N capable data minimum value and bias voltage Reg_b input to totalizer addition and obtain described clipping level value slice_lv, wherein, N be more than or equal to 1 natural number.
The synchronous reconstruction unit 403 of described row comprises a subtracter, the line synchronizing signal Hin1 of input and clipping level slice_lv subtract each other in subtracter obtain rebuilding after more satisfactory line synchronizing signal Hout, export polarity judging unit and row synchronous counting unit to.
Described field synchronization cutter unit 402 comprises a subtracter, and the field sync signal Vin1 of input and clipping level slice_lv subtracts each other and obtains field sync signal Vt in subtracter, inputs to field synchronization reconstruction unit 404.
Described field synchronization reconstruction unit 404 comprises a field synchronization integral unit and a comparer, the field sync signal of field sync signal especially in compound row field sync signal, need to ask for field sync signal by integrating circuit, integrating circuit utilizes additive calculating, only have actual field sync signal could generate new field sync signal by integration, and row is synchronous or the signal such as interference after integrating circuit process all by filtering, enhance the stability of rebuilding and generating field sync signal.
Described row synchronous counting unit 405 comprises a counter, counts counting in a line.
Described field synchronization counting unit 406 comprises a counter, counts the line number in.
Described row field polarity judging unit 407, judges that line synchronizing signal starting point and field sync signal starting point are rising pulses or falling pulse, adopts 0 and 1 signal to distinguish.
In another embodiment, described row field polarity and width detection unit 104 also comprise two low-pass filters 408 and 409; As shown in Figure 5.When incoming video signal is VGA form, then row field signal is respectively through inputing to described clipping level generation unit 401, the synchronous reconstruction unit 403 of row and field synchronization cutter unit 402 after two low-pass filters 408 and 409 low-pass filtering again.After increasing described low-pass filter, the synchronizing signal in the synchronizing signal of VGA form and composite signal can be leached better.
Described quadruple timesharing judging unit 105 comprises:
First judging unit, comprises comparing unit one, resolution information table and control module one, wherein:
Described comparing unit one, for four of current detection the capable synchronous width Hcount of resolution information, field synchronization width Vcount and row synchronous polarity Hp, Vp are compared one by one with the relevant parameter in resolution information table, if compare difference all within an error margin value with four of a kind of resolution, then with this resolution match, coupling number adds 1; Otherwise do not mate, coupling number remains unchanged;
Described resolution information table is a storage space, store the row field polarity of the present invention's each VGA signal detectable and YPbPr signal, the synchronous width of row and field synchronization width four values, described four values are different according to the difference of sample frequency, by register configuration, or write this storage space by control system.
Described control module one, judges for the coupling number obtained according to described comparing unit one, if coupling number is 1, then detects successfully, thinks to detect to obtain the resolution that this resolution is incoming video signal; If coupling number is greater than 1, then start the first tolerance limit reducing unit; If coupling number is zero, then start the second judging unit.
First tolerance limit reducing unit, after reducing error margin value according to the step-length of a setting, again inputs the first judging unit and compares;
Second judging unit, comprises comparing unit two, resolution information table, control module two, wherein:
Described comparing unit two, for by two of current detection resolution informations: row synchronous width Hcount and field synchronization width Vcount compares one by one with the relevant parameter in resolution information table, if compare difference all within an error margin value with four of a kind of resolution, then with this resolution match, coupling number adds 1; Otherwise do not mate;
Described resolution information table is the resolution information table in described first judging unit;
Described control module two, judges for the coupling number obtained according to described comparing unit two, if coupling number is 1, then detects successfully; If coupling number is 0, then detect failure; If coupling number is greater than 1, then enter the second tolerance limit reducing unit;
Second tolerance limit reducing unit, after reducing error margin value according to the step-length of a setting, again inputs the second judging unit and judges.
Described first tolerance limit reducing unit and the second tolerance limit reducing unit can be same unit, also can be different unit.
One of ordinary skill in the art will appreciate that all or part of flow process realized in above-described embodiment method, that the hardware that can carry out instruction relevant by computer program has come, described program can be stored in a computer read/write memory medium, this program, when performing, can comprise the flow process of the embodiment as above-mentioned each side method.Wherein, described storage medium can be magnetic disc, CD, read-only store-memory body (Read-Only Memory, ROM) or random store-memory body (Random Access Memory, RAM) etc.
Being described in detail the embodiment of the present invention above, applying embodiment herein to invention has been elaboration, the explanation of above embodiment just understands method and apparatus of the present invention for helping; Meanwhile, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (12)
1. a vision signal resolution detection method, is characterized in that, the method comprises the steps:
Step S100: incoming video signal and row field sync signal;
Step S101: judge that input signal is VGA signal or YPbPr signal; If incoming video signal is VGA signal, then enter step S102, otherwise enter step S103;
Step S102: the multibit signal row field sync signal of 1 bit all being expanded to W position, wherein W is positive integer;
Step S103: Key dithering filtering process is carried out to the synchronizing signal of input;
Step S104: according to the row field sync signal after Key dithering filtering process, the polarity Hp of detect lines field sync signal and Vp, count to get width Hcount and Vcount of row field sync signal;
Step S105: the determination methods adopting quadruple timesharing, obtains the resolution of current vision signal.
2. detection method according to claim 1, is characterized in that, described step S104 also comprises the steps:
Step S400: the row field sync signal after input Key dithering filtering process;
Step S401: cut level value slicr_lv by register configuration one;
Step S402: field sync signal deducts clipping level slice_lv, obtains the field sync signal Vt after cutting;
Step S403: line synchronizing signal deducts clipping level slice_lv, obtains the line synchronizing signal Hout cutting rear reconstruction;
Step S404: the field sync signal Vt after cutting obtains the field sync signal Vout of reconstruction by integrating circuit;
Step S405: the polarity judging row field sync signal Hout and the Vout rebuild, exports Hp and Vp;
Step S406: count to get the Hcount that counts in a line;
Step S407: count to get the line number Vcount in.
3. detection method according to claim 2, is characterized in that, also comprises a step: exported after low-pass filter by input signal between described step S400 and step S401.
4. detection method according to claim 2, is characterized in that, described step S401 also replaces by following steps:
Find out the minimum value of the capable signal of N;
The bias voltage Reg_b that this minimum value and is arranged is added, obtains clipping level value slice_lv.
5. detection method according to claim 1, is characterized in that, described step S105 also comprises the steps:
Step S501: by four of current detection resolution informations: capable synchronous width Hcount, field synchronization width Vcount and row synchronous polarity Hp, Vp compare one by one with the relevant parameter in resolution information table, if compare difference all within an error margin value with four of a kind of resolution, then with this resolution match, coupling number adds 1; Otherwise do not mate;
Described resolution information table stores the row field polarity of each VGA signal and YPbPr signal, capable synchronous width and field synchronization width four values;
If coupling number is 1, the resolution of this coupling is the resolution of incoming video signal;
If coupling number is greater than 1, enter step S502; If coupling number is zero, enter step S503;
Step S502: after reducing error margin value according to the step-length of a setting, repeat step S501;
Step S503: by two of current detection resolution informations: row synchronous width Hcount and field synchronization width Vcount compares one by one with the relevant parameter in resolution information table, if compare difference all within an error margin value with four of a kind of resolution, then with this resolution match, coupling number adds 1; Otherwise do not mate;
When coupling number is 1, then detect successfully; If coupling number is greater than 1, then enter step S504; If coupling number is zero, then detect failure;
Step S504: reduce error margin value according to the step-length of a setting, repeat step S503.
6. detection method according to claim 5, is characterized in that, the step-length set in described step S502 and step S504 is equal.
7. a kind of vision signal resolution pick-up unit of detection method according to claim 1, it is characterized in that, this device comprises: input source detecting unit, row field Bits Expanding unit, Key dithering filter unit, row field polarity and width detection unit, quadruple timesharing judging unit; Wherein,
Described input source detecting unit, for detecting input signal, judges that input signal is VGA signal or YPbPr signal;
Described row field Bits Expanding unit, for all extending to W position by the line synchronizing signal of a bit and field sync signal;
Described Key dithering filter processing unit, comprises a wave filter, for removing the jittering noise in row field sync signal;
Described row field polarity and width detection unit, for polarity Hp and the Vp of detect lines field sync signal, simultaneously by counting to get width Hcount and Vcount of row field sync signal;
Described quadruple timesharing judging unit, for according to the row field polarity Hp detected and count to get and Vp, row synchronous width Hcount and field synchronization width Vcount, adopts the determination methods of quadruple timesharing, obtains the resolution of current vision signal.
8. pick-up unit according to claim 7, is characterized in that, described row field polarity and width detection unit also comprise:
Clipping level generation unit, for cutting level value slicr_lv by register configuration one;
Field synchronization cutter unit, for field sync signal is deducted clipping level slice_lv, obtains the field sync signal Vt after cutting;
The synchronous reconstruction unit of row, for line synchronizing signal is deducted clipping level slice_lv, obtains the line synchronizing signal Hout cutting rear reconstruction;
Field synchronization reconstruction unit, for the field sync signal Vout being obtained by integrating circuit rebuilding by the field sync signal Vt after cutting;
Row synchronous counting unit, for by a counter, counts to get the Hcount that counts in a line;
Field synchronization counting unit, for by a counter, counts to get the line number Vcount in;
Row field polarity judging unit, for judging the polarity of row field sync signal Hout and the Vout rebuild, exports Hp and Vp.
9. pick-up unit according to claim 7, is characterized in that, described clipping level generation unit also can be replaced:
Clipping level computing unit, comprising:
Minimum value unit, for finding out the minimum value of the capable signal of N;
Superpositing unit, is added for the bias voltage Reg_b this minimum value and arranged, obtains clipping level value slice_lv.
10. pick-up unit according to claim 8, is characterized in that, described row field polarity and width detection unit also comprise two low-pass filters, input after carrying out low-pass filtering to input signal.
11. pick-up units according to claim 7, is characterized in that, described quadruple timesharing judging unit also comprises:
First judging unit, comprises comparing unit one, resolution information table and control module one, wherein:
Described comparing unit one, for by four of current detection resolution informations: row synchronous width Hcount, field synchronization width Vcount and row synchronous polarity Hp, Vp compare one by one with the relevant parameter in resolution information table, if compare difference all within an error margin value with four of a kind of resolution, then with this resolution match, coupling number adds 1; Otherwise do not mate;
Described resolution information table is a storage space, for storing the row field polarity of each VGA signal and YPbPr signal, capable synchronous width and field synchronization width four values;
Described control module one, judges for the coupling number obtained according to described comparing unit one, if coupling number is 1, then detects successfully, thinks to detect to obtain the resolution that this resolution is incoming video signal; If coupling number is greater than 1, then start the first tolerance limit reducing unit; If coupling number is zero, then start the second judging unit.
First tolerance limit reducing unit, after reducing error margin value according to the step-length of a setting, inputs the first judging unit;
Second judging unit, comprises comparing unit two, resolution information table, control module two, wherein:
Described comparing unit two, for by two of current detection resolution informations: row synchronous width Hcount and field synchronization width Vcount compares one by one with the relevant parameter in resolution information table, if compare difference all within an error margin value with four of a kind of resolution, then with this resolution match, coupling number adds 1; Otherwise do not mate;
Described resolution information table is the resolution information table in described first judging unit;
Described control module two, judges for the coupling number obtained according to described comparing unit two, if coupling number is 1, then detects successfully; If coupling number is 0, then detect failure; If coupling number is greater than 1, then enter the second tolerance limit reducing unit;
Described second tolerance limit reducing unit, for reducing error margin value according to the step-length of a setting, inputs the second judging unit.
12. pick-up units according to claim 11, is characterized in that, described first tolerance limit reducing unit and the second tolerance limit reducing unit are same unit.
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