CN104579252B - Delay-based double-rail pre-charging logic trigger - Google Patents
Delay-based double-rail pre-charging logic trigger Download PDFInfo
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- CN104579252B CN104579252B CN201510005000.5A CN201510005000A CN104579252B CN 104579252 B CN104579252 B CN 104579252B CN 201510005000 A CN201510005000 A CN 201510005000A CN 104579252 B CN104579252 B CN 104579252B
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Abstract
The invention discloses a delay-based double-rail pre-charging logic trigger. The delay-based double-rail pre-charging logic trigger comprises a first-stage data converter, a second-stage main latch and a third-stage slave latch, the first-stage data converter converts a delay-based double-rail pre-charging logic (DDPL) signal into a sense amplifer-based logic (SABL) signal, and the second-stage main latch collects and latches a time delay signal of the sense amplifer-based logic (SABL) signal. The third-stage slave latch collects and latches a time delay signal of an output signal of the second-stage main latch. The first-stage data converter is independently simulated, compared with the structure in the prior art, time delay is shortened by 49 percent, and the minimum time delay capable of being recognized is shortened to be smaller than 0.1 ps. The second-stage main latch is independently simulated, and compared with the structure in the prior art, time delay is shortened by 38.4 percent to the maximum degree. In addition, the speed, power consumption and power consumption balance of the trigger are greatly improved relative to those of a trigger in the prior art.
Description
Technical field
The present invention relates to trigger technology field, is more particularly to a kind of double track preliminary filling logical trigger based on time delay.
Background technology
Because the double track preliminary filling logic DDPL signal based on time delay only jumps edge or lower jump along attached on clock signal clk
The nearly of short duration time embodies, and the signal on remaining time double track is consistent and fixed, it is impossible to continue the too long of time, therefore existing
DDPL flip-flop designs be all based on being converted into DDPL signals to preserve the signal format such as complementary metal oxygen of certain hour
The DDPL signals of compound semiconductor CMOS signal, then data output is realized into the work(of trigger when arriving in the next evaluation cycle
Energy.There are several DDPL triggers to be suggested in document prior art, one of which is by the way that DDPL signals are transformed into
Cmos signal, is then converted into when arriving in the next evaluation cycle on this basis DDPL signal outputs, this D-C-D circuits
The trigger structure of structure is complicated, postpones big, power consumption height, and speed is slow, and power consumption is uneven.
Another kind is that first DDPL signals are converted into based on the logical signal SABL signals of sense amplifier, then by one
Similar to SABL signals master-slave flip-flop structure by data remain to next evaluation cycle arrive when export again, input signal
SABL signals are converted into by DDPL-SABL transducers, then are jumped under clock signal clk by second level DDPL p-types main latch
Edge is sampled to SABL signals, but has the signal mode for dividing in preliminary filling cycle and evaluation cycle because SABL signals are also one
Formula, although at this moment SABL signals can be due to being pre-charged with a saltus step and saltus step has certain time delay, but time span is not enough
To allow second level latch to sample successfully, therefore a module time delay being made up of 3 grades of phase inverters is introduced in two-stage circuit,
Ensure the retention time of sampling, and the operated in anti-phase needed to signal.Same time delay module exists in second level master
Latch and the third level are between latch, playing same delay SABL signals, it is ensured that the retention time of sampling.The third level from
SABL signals are converted into DDPL signal outputs by latch while edge sampling and latch signal are jumped on clock signal clk.
The input of first order data converter DDPL-SABL is actually the DDPL signals of p-type, low in clock signal clk
Output is charged in advance low level during level, DDPL input signals DDPL_in rising edge is jumped after on clock, now by
Time delay between DDPL_in dual-rail output signal rising edges produces a pulse signal CKB and is used for opening two transmission by XOR gate
Door, and thus corresponding outfan is pulled upward to into high level, it is achieved in the first order converter function envisioned.In Fig. 1 a,
SABL represents the output signal through first order data converter；DDPL_in represents input signal.
Output is charged in advance high level by second level main latch when clock signal clk is low, is jumped along post-sampling on CLK
Edge is jumped under signal SABL_int after the time delay of SABL signals, corresponding output node is pulled down to into low level.This circuit is prevented
Charge share, while avoiding the DC channel occurred in precharging circuit.In Fig. 1 b, L-SABL is represented through second level main latch
The output signal of device process；SABL_int is input signal.
The third level is charged in advance low level in CLK=0 from latch to output, jumps on clock signal clk along rear reading
The upper jump edge of signal L-SABL-int of the output signal after time delay after the process of second level main latch, forms double track letter
Number first it is upper jump edge, after delay, form another upper jump edge of dual-rail output signal；Through the 3rd pole from latch
The signal exported after reason is output signal DDPL-out of trigger.
Second level main latch is simplified afterwards, the circuit diagram after simplifying is as shown in Figure 2.
Structure as shown in Figure 1 a, 1 b increases the length of evaluation pipe, and power consumption is big, speed is slow.
Simple structure as shown in Figure 2, but its transmission delay is little and there is a problem of charge share.
The content of the invention
(1) technical problem to be solved
The technical problem to be solved in the present invention is time delay, the power consumption for how reducing DDPL triggers, improves speed and power consumption
Balance, while avoiding charge share problem.
(2) technical scheme
In order to solve above-mentioned technical problem, the invention provides a kind of double track preliminary filling logical trigger based on time delay, bag
First order data converter, second level main latch and the third level are included from latch, the first order data converter is by base
Be converted to based on the logical signal of sense amplifier in the double track preliminary filling logical signal of time delay, the second level main latch is to institute
The time delayed signal for being set forth in the logical signal of sense amplifier is acquired and latches；The third level is from latch to described second
The time delayed signal of the output signal of level main latch is acquired and latches；
The first order data converter include first, second, third, fourth PMOS transistor, first, second, third,
Four, the 5th nmos pass transistors and first, second phase inverter；
The source electrode of first PMOS transistor, the source electrode of the second PMOS transistor, the source electrode of the 3rd PMOS transistor,
The source electrode of four PMOS transistors is all connected with power supply, and the grid of first PMOS transistor, the grid of the second PMOS transistor are equal
Connection clock signal, the grid of the 3rd PMOS transistor, the grid of the 4th PMOS transistor connect respectively the described 4th
The grid of the grid of nmos pass transistor, the 5th nmos pass transistor；The drain electrode of first PMOS transistor, the 3rd PMOS transistor
Drain electrode, the drain electrode of the 4th nmos pass transistor, the input of the first phase inverter be all connected with the grid of the 5th nmos pass transistor,
The drain electrode of second PMOS transistor, the drain electrode of the 4th PMOS transistor, the drain electrode of the 5th nmos pass transistor, the second phase inverter
Input be all connected with the grid of the 4th nmos pass transistor；Source electrode, the 5th NMOS crystal of the 4th nmos pass transistor
The source electrode of pipe connects respectively the drain electrode of second nmos pass transistor, the drain electrode of the 3rd nmos pass transistor；2nd NMOS is brilliant
The source electrode of body pipe, the source electrode of the 3rd nmos pass transistor are all connected with the drain electrode of first nmos pass transistor, and the 2nd NMOS is brilliant
The grid of body pipe, the grid of the 3rd nmos pass transistor connect respectively the reverse of input signal and the input signal；Described first
Nmos pass transistor grid connects the clock signal, its source ground；The outfan of first phase inverter, the second phase inverter
Outfan is respectively based on the logical signal reverse, based on sense amplifier of the logical signal of sense amplifier.
Preferably, the second level main latch include the five, the six, the seven, the 8th PMOS transistors, the six, the 7th,
Eight, the nine, the ten, the 11st nmos pass transistors and the three, the 4th phase inverters；
The source electrode of the 5th PMOS transistor, the source electrode of the 6th PMOS transistor are all connected with power supply, the 5th PMOS
The grid of transistor, the grid of the 6th PMOS transistor connect respectively the time delay letter of the logical signal based on sense amplifier
Number, the time delayed signal of the logical signal based on sense amplifier it is reverse；The drain electrode connection of the 5th PMOS transistor
The source electrode of the 7th PMOS transistor and the drain electrode of the 8th nmos pass transistor；The grid of the 8th nmos pass transistor
The time delayed signal of the connection logical signal based on sense amplifier, its source electrode connects the leakage of the 6th nmos pass transistor
Pole；The 7th PMOS transistor grid connects the clock signal, the signal input of its drain electrode connection the 3rd phase inverter
End and the drain electrode of the tenth nmos pass transistor；Grid, the grid of the tenth nmos pass transistor of the 6th nmos pass transistor
It is all connected with the clock signal；Source electrode, the source grounding of the tenth nmos pass transistor of the 6th nmos pass transistor；Described
The source electrode of drain electrode connection the 8th PMOS transistor of six PMOS transistors and the drain electrode of the 9th nmos pass transistor；Institute
The grid for stating the 8th PMOS transistor connects the clock signal, and its drain electrode connects input and the institute of the 4th phase inverter
State the drain electrode of the 11st nmos pass transistor；The grid connection logic based on sense amplifier of the 9th nmos pass transistor
Reverse, the drain electrode of its source electrode connection the 7th nmos pass transistor of the time delayed signal of signal；11st nmos pass transistor
Grid, the grid of the 7th nmos pass transistor be all connected with the clock signal；The source electrode of 11 nmos pass transistor, the 7th
The source grounding of nmos pass transistor；3rd phase inverter, the outfan of the 4th phase inverter are respectively the main lock in the second level
The output signal of storage, the output signal of the second level main latch it is reverse.
Preferably, the second level main latch include the nine, the ten, the 11st, the 12nd PMOS transistor, the tenth
2nd, the 13rd nmos pass transistor and the 5th, hex inverter；
The source electrode of the 9th PMSO transistors, the source electrode of the tenth PMOS transistor are all connected with power supply；9th PMSO
The grid of transistor, the grid of the tenth PMOS transistor are all connected with the clock signal；The drain electrode of the 9th PMSO transistors,
The drain electrode of the tenth PMOS transistor connects respectively source electrode, the source of the 12nd PMOS transistor of the 11st PMSO transistors
Pole；The grid of the 11st PMSO transistors, the grid of the 12nd PMOS transistor connect respectively described based on sensitive amplification
The time delayed signal of the logical signal of device, the time delayed signal of the logical signal based on sense amplifier it is reverse；Described tenth
The input of drain electrode connection the 5th phase inverter of one PMSO transistors and the drain electrode of the tenth bi-NMOS transistor；Institute
State the input and the 13rd nmos pass transistor of the drain electrode connection hex inverter of the 12nd PMOS transistor
Drain electrode；The grid of the tenth bi-NMOS transistor, the grid of the 13rd nmos pass transistor are all connected with the clock signal；It is described
The source electrode of the tenth bi-NMOS transistor, the source grounding of the 13rd nmos pass transistor；The outfan of the 5th phase inverter,
The outfan of hex inverter is respectively the output letter of the output signal of the second level main latch, the second level main latch
Number it is reverse.
Preferably, the third level includes the 13rd, the 14th PMOS transistor from latch, the 14th, the 15th, the
16, the 17th, the 18th, the 19th nmos pass transistor and the seven, the 8th phase inverters；
The source electrode of the 13rd PMSO transistors, the source electrode of the 14th PMSO transistors are all connected with power supply, and the described tenth
The grid of three PMSO transistors, the grid of the 14th PMSO transistors are all connected with the clock signal；13rd PMOS is brilliant
The signal input part of drain electrode connection the 7th phase inverter of body pipe and the drain electrode of the 18th nmos pass transistor；Described
The signal input part of drain electrode connection the 8th phase inverter of 14 PMOS transistors and the 19th nmos pass transistor
Drain electrode；The grid of the 18th nmos pass transistor, the grid of the 19th nmos pass transistor are all connected with the clock signal；It is described
The source electrode of the 18th nmos pass transistor connects the drain electrode of the 14th nmos pass transistor and the 16th nmos pass transistor
Drain electrode；The source electrode of the 19th nmos pass transistor connects the drain electrode and the described 15th of the 17th nmos pass transistor
The drain electrode of nmos pass transistor；The grid of the 14th nmos pass transistor, the grid of the 15th nmos pass transistor connect respectively institute
State the time delayed signal of the output signal of second level main latch, the time delayed signal of the output signal of second level main latch it is anti-
To；The grid of the 16th nmos pass transistor and the grid of the 17th nmos pass transistor are all connected with the clock signal
Time delayed signal；Source electrode, the source electrode of the 15th nmos pass transistor, the 16th nmos pass transistor of the 14th nmos pass transistor
Source electrode and the 17th nmos pass transistor source grounding；The outfan of the 7th phase inverter, the 8th phase inverter it is defeated
Go out the output signal of end respectively reverse, the described trigger of the output signal of the trigger.
(3) beneficial effect
The invention provides a kind of double track preliminary filling logical trigger based on time delay, for the first DBMS turns in the present invention
Parallel operation is individually emulated, and for structure of the prior art, delay decrease 49%, the minimum time delay that can recognize is reduced
To less than 0.1ps；For second level main latch is individually emulated in the present invention, relative to structure of the prior art, time delay is most
It is big to shorten 38.4%；
The trigger of the other present invention is in terms of speed, power consumption, power-consumption balance relative to trigger of the prior art
For be all enhanced.
Description of the drawings
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
The accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 a are the circuit diagram of the first order data converter of DDPL triggers in prior art；
Fig. 1 b are the circuit diagram of the second level main latch of DDPL triggers in prior art；
Fig. 2 is the circuit diagram of the second level main latch of the DDPL triggers being improved to Fig. 1 b；
Fig. 3 a are the circuit diagram of the first order data converter of the DDPL triggers of a preferred embodiment of the present invention；
Fig. 3 b are the circuit diagram of the second level main latch of the DDPL triggers of a preferred embodiment of the present invention；
Fig. 3 c are the circuit diagram of the third level of the DDPL triggers of a preferred embodiment of the present invention from latch；
Fig. 4 is the circuit diagram of the second level main latch of the DDPL triggers of another preferred embodiment in the present invention；
Fig. 5 is the time delay simulation oscillogram of the first order data converter of the present invention；
Fig. 6 is structure shown in Fig. 1 a to being input into the simulation waveform of the ability to bear of dual-rail output signal Δ delay decrease；
Fig. 7 is first order data converter of the invention to being input into the emulation of the ability to bear of dual-rail output signal Δ delay decrease
Oscillogram；
Fig. 8 is the time delay simulation oscillogram of circuit structure shown in Fig. 3 b；
Fig. 9 is the time delay simulation oscillogram of circuit structure shown in Fig. 4；
Figure 10 is the sequential functional circuit for emulating trigger；
Figure 11 is the improvement time stimulatiom oscillogram of trigger 1；
Figure 12 is the improvement time stimulatiom oscillogram of trigger 2；
Figure 13 is 5ps to improve trigger 1 in Δ time delay, the oscillogram when clock cycle is 110ps；
Figure 14 is 5ps to improve trigger 2 in Δ time delay, the oscillogram when clock cycle is 100ps；
Figure 15 is the artificial circuit design drawing of the condition of power consumption for emulating flip-flop circuit.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.Following examples are used to illustrate this
It is bright, but can not be used for limiting the scope of the present invention.
The invention discloses a kind of double track preliminary filling logical trigger based on time delay, including first order data converter,
, from latch, the first order data converter believes the double track preliminary filling logic based on time delay for two grades of main latch and the third level
Number be converted to based on the logical signal of sense amplifier, the second level main latch is believed the logic of be set forth in sense amplifier
Number time delayed signal be acquired and latch；The third level is from latch to the output signal of the second level main latch
Time delayed signal is acquired and latches；
The first order data converter includes that the first PMOS transistor P1, the second PMOS transistor P2, the 3rd PMOS are brilliant
Body pipe P3, the 4th PMOS transistor P4, the first nmos pass transistor N1, the second nmos pass transistor N2, the 3rd nmos pass transistor N3,
Four nmos pass transistor N4, the 5th nmos pass transistor N5 and the first phase inverter F1, the second phase inverter F2；The first PMOS crystal
The source electrode of pipe P1, the source electrode of the second PMOS transistor P2, the source electrode of the 3rd PMOS transistor P3, the source of the 4th PMOS transistor P4
Pole is all connected with power supply, and the grid of first PMOS transistor P1, the grid of the second PMOS transistor P2 are all connected with clock signal
CLK, the grid of the 3rd PMOS transistor P3, the grid of the 4th PMOS transistor P4 connect respectively the 4th NMOS crystal
The grid of the grid of pipe N4, the 5th nmos pass transistor N5；The drain electrode of first PMOS transistor P1, the 3rd PMOS transistor P3
Drain electrode, the drain electrode of the 4th nmos pass transistor N4, the input of the first phase inverter F1 be all connected with the 5th nmos pass transistor N5
Grid, the drain electrode of second PMOS transistor P2, the drain electrode of the 4th PMOS transistor P4, the leakage of the 5th nmos pass transistor N5
Pole, the input of the second phase inverter F2 are all connected with the grid of the 4th nmos pass transistor N4；The 4th nmos pass transistor N4
Source electrode, the source electrode of the 5th nmos pass transistor N5 connect the drain electrode of the second nmos pass transistor N2, the 3rd NMOS crystal respectively
The drain electrode of pipe N3；The source electrode of the second nmos pass transistor N2, the source electrode of the 3rd nmos pass transistor N3 are all connected with described first
The drain electrode of nmos pass transistor N1, the grid of the second nmos pass transistor N2, the grid of the 3rd nmos pass transistor N3 connect respectively
Input signal DDPL-in and input signal DDPL-in it is reverse；When the first nmos pass transistor N1 grids connect described
Clock signal CLK, its source ground；The outfan of the one phase inverter F1, the outfan of the second phase inverter F2 are respectively SABL letters
Number reverse, SABL signals.
As shown in Figure 3 a, wherein DDPL-in is the DDPL letters of input to the circuit diagram of the first order data converter of the present invention
Number, preliminary filling is carried out to circuit internal node and output node in CLK=0, jump on CLK along rear to input signal DDPL-in
Sampled, so on the one hand eliminated CMOS XOR doors complicated in former prior art circuits, on the other hand shortened
Postpone, reduce power consumption, increased speed, shorten setup time, promote power-consumption balance.
Preferably, the second level main latch include the 5th PMOS transistor P5, the 6th PMOS transistor P6, the 7th
PMOS transistor P7, the 8th PMOS transistor P8, the 6th nmos pass transistor N6, the 7th nmos pass transistor N7, the 8th NMOS crystal
Pipe N8, the 9th nmos pass transistor N9, the tenth nmos pass transistor N10, the 11st nmos pass transistor N11 and the 3rd phase inverter F3,
4th phase inverter F4；The source electrode of the 5th PMOS transistor P5, the source electrode of the 6th PMOS transistor P6 are all connected with power supply, described
The grid of the 5th PMOS transistor P5, the grid of the 6th PMOS transistor P6 connect respectively the time delayed signal of the SABL signals
SABL-int, the time delayed signal SABL-int of the SABL signals it is reverse；The drain electrode connection of the 5th PMOS transistor P5
The source electrode of the 7th PMOS transistor P7 and the drain electrode of the 8th nmos pass transistor P8；The 8th nmos pass transistor P8
Grid connect the time delayed signal SABL-int of the SABL signals, its source electrode connects the leakage of the 6th nmos pass transistor N6
Pole；The 7th PMOS transistor P7 grid connects the clock signal clk, the letter of its drain electrode connection the 3rd phase inverter F3
The drain electrode of number input and the tenth nmos pass transistor N10；The grid of the 6th nmos pass transistor N6, the tenth NMOS are brilliant
The grid of body pipe N10 is all connected with the clock signal clk；Source electrode, the tenth nmos pass transistor of the 6th nmos pass transistor N6
The source grounding of N10；The source electrode of drain electrode connection the 8th PMOS transistor P8 of the 6th PMOS transistor P6 and
The drain electrode of the 9th nmos pass transistor N9；The grid of the 8th PMOS transistor P8 connects the clock signal clk, its leakage
Pole connects the input of the 4th phase inverter F4 and the drain electrode of the 11st nmos pass transistor N11；9th NMOS
The grid of transistor N9 connects the reverse of the time delayed signal SABL-int of the SABL signals, and its source electrode connects the 7th NMOS
The drain electrode of transistor N7；The grid of the 11st nmos pass transistor N11, the grid of the 7th nmos pass transistor N7 are all connected with described
Clock signal clk；The source electrode of the 11 nmos pass transistor N11, the source grounding of the 7th nmos pass transistor N7；Described 3rd
Phase inverter F3, the outfan of the 4th phase inverter F4 be respectively output signal L-SABL of the second level main latch, described
Output signal L-SABL of two grades of main latch it is reverse.
The circuit diagram of second level main latch in the present invention as shown in Figure 3 b, it is to avoid the appearance of charge share, in addition
Evaluation critical path is shortened again, additionally due to the raising of NMOS ratios, the decline of PMOS sizes, electric capacity reduces in circuit, work(
Consumption is also reduced.
Preferably, the second level main latch include the 9th PMOS transistor P9, the tenth PMOS transistor P10, the tenth
One PMOS transistor P11, the 12nd PMOS transistor P12, the tenth bi-NMOS transistor N12, the 13rd nmos pass transistor N13 with
And the 5th phase inverter F5, hex inverter F6；
The source electrode of the 9th PMSO transistor P9, the source electrode of the tenth PMOS transistor P10 are all connected with power supply；Described 9th
The grid of PMSO transistor P9, the grid of the tenth PMOS transistor P10 are all connected with the clock signal；The 9th PMSO crystal
The drain electrode of pipe P9, the drain electrode of the tenth PMOS transistor P10 connect respectively the source electrode of the 11st PMSO transistor P11, the tenth
The source electrode of two PMOS transistors P12；Grid, the grid of the 12nd PMOS transistor P12 of the 11st PMSO transistor P11
Connect respectively the time delayed signal SABL-int of the SABL signals, the time delayed signal SABL-int of the SABL signals it is reverse；
The input and the 12nd NMOS of drain electrode connection the 5th phase inverter F5 of the 11st PMOS transistor P11 is brilliant
The drain electrode of body pipe N12；The input of the drain electrode connection hex inverter F6 of the 12nd PMOS transistor P12 and institute
State the drain electrode of the 13rd nmos pass transistor N13；Grid, the 13rd nmos pass transistor N13 of the tenth bi-NMOS transistor N12
Grid be all connected with the clock signal clk；Source electrode, the 13rd nmos pass transistor N13 of the tenth bi-NMOS transistor N12
Source grounding；The outfan of the 5th phase inverter F5, the outfan of hex inverter F6 are respectively the second level master
Output signal L-SABL of latch, output signal L-SABL of the second level main latch it is reverse.
Although as shown in Figure 4 circuit still can not compare the appearance of charge share, the situation of each charge share is caused
It is consistent, it is to avoid resulting power consumption imbalance problem.The simple of circuit structure also brings low power consumption；But evaluation
Critical path is more longer than circuit shown in Fig. 3 b, and speed can be slightly slow.
Preferably, the third level includes the 13rd PMOS transistor P13, the 14th PMOS transistor P14 from latch,
14th nmos pass transistor N14, the 15th nmos pass transistor N15, the 16th nmos pass transistor N16, the 17th nmos pass transistor
N17, the 18th nmos pass transistor N18, the 19th nmos pass transistor N19 and the 7th phase inverter F7, the 8th phase inverter F8；It is described
The source electrode of the 13rd PMSO transistor P13, the source electrode of the 14th PMSO transistor P14 are all connected with power supply, the 13rd PMSO
The grid of transistor P13, the grid of the 14th PMSO transistor P14 are all connected with the clock signal clk；13rd PMOS
The signal input part of drain electrode connection the 7th phase inverter F7 of transistor P13 and the 18th nmos pass transistor N18's
Drain electrode；The signal input part of drain electrode connection the 8th phase inverter F8 of the 14th PMOS transistor P14 and described the
The drain electrode of 19 nmos pass transistor N19；Grid, the grid of the 19th nmos pass transistor N19 of the 18th nmos pass transistor N18
Pole is all connected with the clock signal clk；The source electrode of the 18th nmos pass transistor N18 connects the 14th nmos pass transistor
The drain electrode of N14 and the drain electrode of the 16th nmos pass transistor N16；The source electrode connection of the 19th nmos pass transistor N19
The drain electrode of the 17th nmos pass transistor N17 and the drain electrode of the 15th nmos pass transistor N15；14th NMOS
The grid of transistor N14, the grid of the 15th nmos pass transistor N15 connect respectively the output signal of the second level main latch
The time delayed signal L-SABL-int of L-SABL, the time delayed signal L-SABL-int of the output signal of the second level main latch
Reversely；The grid of the 16th nmos pass transistor N16 and the grid of the 17th nmos pass transistor N17 are all connected with described
The time delayed signal CKD of clock signal；Source electrode, the source of the 15th nmos pass transistor N15 of the 14th nmos pass transistor N14
The source grounding of pole, the source electrode of the 16th nmos pass transistor N16 and the 17th nmos pass transistor N17；Described 7th is anti-phase
The outfan of device F7, the outfan of the 8th phase inverter F8 are respectively the anti-of output signal DDPL-out of the trigger of the present invention
To, the present invention trigger output signal DDPL-out.
As shown in Figure 3 c, the third level is charged in advance low level in CLK=0 from latch to output, jumps on CLK along rear reading
The upper jump edge of the number of winning the confidence L_SABL_int, opens N14, and corresponding output node is pulled upward to 1 by N15, forms double track letter
Number first it is upper jump edge, the upper jump of the signal CKD after Δ postpones along N16, N17 is opened, by another output node
Move 1 to, formed and jump on another of dual-rail output signal edge.
The time delay of the first order data converter of the present invention is emulated under flip-flop circuit environment, emulation tool is
HSPICE, based on SMIC40nm technology libraries, input is given by signal source, input signal rising edge relative time clock along delayed one section when
Between, with the input under simulating actual conditions.Observation is from input signal DDPL_in rising edge to output signal SABL signal rising edge
Between time delay, waveform is as shown in figure 5, delay product is as shown in table 1.Unit of time is the E-11 seconds in form, and XY refers in Fig. 1 a
The first order data converter of proposition, Pro refers to the first order data converter proposed in the present invention, sets forth in oscillogram
Clock CLK, input signal DDPL_in and output signal SABL.From waveform and data, the first DBMS proposed by the present invention
Transducer can realize the function of timing conversion, be SABL logics by DDPL logical transitions, and relative to the structure of prior art
For, the structure delay decrease of proposition 49%.
Table 1
| Delay(E-11s) | Data 0 | Data 1 | Meansigma methodss |
| XY | 4.7406 | 5.0663 | 4.90345 |
| Pro | 2.5196 | 2.5196 | 2.5196 |
In order to observe ability to bear of the first order data converter of the present invention to input signal Δ delay decrease, devise
Emulate, in trigger environment, DDPL is input into jump jump edge along relative CLK on dual-rail output signal has certain time-delay (2ns) with imitation
Situation in true input, all input signals are given by signal source, and signal rise and fall time is 20ps, the clock cycle
10ns, dutycycle 50% sets gradually the Δ time delay between input dual-rail output signal for 100ps, 80ps, 60ps, 40ps,
20ps, observes the upper jump situation that first order data converter exports SABL signals.The institute of the simulation waveform of structure such as Fig. 6 shown in Fig. 1 a
Show, the simulation waveform of the first order data converter of the present invention is as shown in Figure 7.
From simulation waveform, for the Δ time delay for tapering into, the structure in Fig. 1 a can not be just in Δ=40ps
The other input data of general knowledge simultaneously forms the SABL signals of needs, and the first order data converter of the present invention after Δ is less than 20ps still
The normal reading and output of signal can be realized.Further emulation shows that the minimum delta time delay that the structure of Fig. 1 a can be recognized exists
41ps, and the minimum delta that the first order data converter of the present invention can be differentiated is less than 0.1ps.
The second level main latch of the present invention is emulated in trigger, emulation tool is HSPICE, is based on
SMIC40nm technology libraries, the input signal of trigger is still given by signal source, and input signal rising edge relative time clock is along delayed
For a period of time, with the input under simulating actual conditions.Observation is jumped along the time delay that edge is jumped under L_SABL signals under CLK.Fig. 3 b
Distinguish as shown in Figure 8 and Figure 9 with the oscillogram of circuit structure shown in Fig. 4.Oscillogram is input into except giving clock signal clk
The level of output, gives outward intermediate node M, the waveform of N, as seen from the figure, M in the case of the two various, the charge share of N
Either be avoided or share situation unanimously will not produce impact to circuit power consumption, realize the purpose of design.Delay data
Table 2 is given, and the unit of time delay is the E-11 seconds, and by Biao Ke get, circuit shown in Fig. 3 b and Fig. 4 has speed with for prior art relatively
The lifting of degree, time delay has been respectively shortened 29.0% and 38.4%, but relative to the prior art speed for having charge share problem
Will be partially slow.
Table 2
| Delay(E-11s) | 0 | 1 | Meansigma methodss |
| Fig. 1 b circuits | 2.9873 | 2.9875 | 2.9874 |
| Fig. 2 circuits | 1.7476 | 1.7467 | 1.74715 |
| Fig. 3 b circuits | 1.8414 | 1.8416 | 1.8415 |
| Fig. 4 circuits | 2.1199 | 2.1201 | 2.12 |
The raising of the first order data converter of the present invention and the speed parameter of second level master latch circuit finally embodies
In the workable highest frequency of trigger, additionally, the impact improved to power consumption and power-consumption balance is also required to carry out trigger
Overall emulation.Due to proposing a kind of data converter and two kinds of second level main latch structures, build on this basis
Two triggers, are referred to as improvement trigger 1 and improve trigger 2, wherein improving trigger 1 has used first for proposing
DBMS transducer and as shown in Figure 3 b second level main latch, improve trigger 2 and have used the first order data conversion for proposing
Device and as described in Figure 4 second level main latch.
In order to emulate the sequential functional realiey of trigger, the simulated environment such as Figure 10 is devised.CLK signal and CKD signals
Be given by signal source, dutycycle 50%, rise and fall time 20ps, CKD has adjustable Δ time delay relative to CLK, be input into
DDPL signals are given by CMOS-DDPL data converters, and the Δ time delay between double track is by signal CLK, CKD and CMOS-DDPL numbers
Together decide on according to transducer.
First Δ time delay be 1ns, the clock cycle be 10ns in the case of respectively to improve trigger 1 and improve trigger
2 are emulated, and realize that respectively by Figure 11, Figure 12 is provided the oscillogram of emulation to observe its sequential.By Tu Ke get, two triggerings
Device all realizes the function of trigger.
In order to emulate minimum delta time delay and the maximum clock frequency that DDPL triggers can bear, adjust successively in the environment
Whether Δ time delays and the clock signal of CLK of the CKD relative to CLK, observation output DDPL signals reduce the data of input signal,
Minimum delta time delay and highest CLK frequency that trigger can bear are judged according to this.Because emulation and observation condition are limited, Δ time delay number
According to simulation step length be 5ps, the simulation step length of clk cycle is 10ps.The result of emulation is as shown in table 3
Table 3
| Unit：s | Minimum delta time delay | Minimum clk cycle |
| The trigger that Fig. 1 b circuits are constituted | 45p | 160p |
| The trigger that Fig. 2 circuits are constituted | 45p | 160p |
| Improve trigger 1 | 5p | 110p |
| Improve trigger 1 | 5p | 100p |
By shown in table, trigger 1 is improved for the trigger of prior art, the Δ time delay that can be born is reduced
89%, the clock cycle that can be born also reduces 32%, and the minimum clock cycle that improving trigger 2 can bear reduces 37%.
Figure 13 gives improvement trigger 1 and is 5ps in Δ time delay, the waveform when clock cycle is 110ps, and Figure 14 gives improvement triggering
Device 2 is 5ps in Δ time delay, the waveform when clock cycle is 100ps.As seen from the figure, in the respective cases, two circuits can be defeated
Go out the signal waveform of needs.
The emulation of power consumption needs emulation each periodic circuit power consumption feelings under a string of stochastic inputs, output loading different situations
Condition, and the distribution of power consumption is thus calculated, compare its power consumption size, normalization power consumption profile NED, normalization standard profile NSD.
This needs emulation platform as shown in figure 15, wherein providing cmos signal by random cmos signal generator is input to CMOS-
Thus DDPL transducers produce DDPL signals, and send in DDPL triggers.The power supply of CMOS-DDPL data converters and triggering
Device power supply uses each independent power supply.For the unbalanced situation of fictitious load, the output of trigger double track connects respectively 1 and 5
Individual phase inverter, the power ground of phase inverter, the electric capacity of simulation output node.Clock signal is 100MHz, and dutycycle 50% rises
Fall time is 20ps, and CKD is given by signal source, provides Δ for 1ns.Emulation platform is HSPCIE, SMIC40nm techniques.Finally
Sampled 8 cycles power consumption as data sample analyze power consumption profile.
Table 4 gives the result after power consumption data is processed, and has average power consumption, NED and NSD respectively, simulates multiple triggerings
Device situation, and thus observing the power consumption situation of entirety and part level, the unit of power consumption is E-6w.C1, C2, C3 refer to respectively existing
There are trigger, the trigger of Fig. 2 compositions that the D-C-D triggers in technology, Fig. 1 a and Fig. 1 b are constituted；C1P and C1N refer to respectively by
Several number converters of D-C-D triggers of the prior art are replaced by structure shown in Fig. 1 a, respectively in p-type DDPL logical sum N-type
The trigger realized under DDPL logics；C21, C31 are represented respectively and its first order data converter are replaced with the first of the present invention
The trigger formed after DBMS transducer.By Biao Ke get, improve trigger 1 and improve the average power consumption of trigger 2, NED,
NSD is better than all triggers above, relative to the trigger that Fig. 1 a and Fig. 1 b is constituted, improves trigger 1 and improves triggering
The power consumption of device 2 reduce respectively 46% and 50%, NED reduce respectively 65% and 52%, NSD reduce 71% He respectively
63%.Improve trigger 1 and improve the contrast of trigger 2 and C21, C31, improvement trigger 1 is more slightly larger than C21 power consumption, but improves
The power consumption of the power dissipation ratio C21 and C31 of trigger 2 will be little, and improve trigger 1 and improve trigger 2 all realize it is lower
NED and NSD.Representing the improved effect of second level main latch will get well relative to C2 and C3.Additionally, improving trigger 1
Power dissipation ratio improve trigger 2 it is bigger, improve trigger 2 anti-DPA effects than improvement trigger 1 it is slightly poor.
Table 4
For the independent emulation of first order data converter of the present invention, for the structure in Fig. 1 a, the knot of proposition
Structure delay decrease 49%, the minimum delta time delay that structure can be recognized, the 41ps of the structure from Fig. 1 a narrowed down to less than 0.1ps.
For the independent emulation of the second level main latch of the present invention, structure shown in Fig. 3 b and Fig. 4 has relative to structure shown in Fig. 1 b
The lifting of speed, time delay has been respectively shortened 29.0% and 38.4%.
In figure, CMOS-in represents the signal input of data converter.
Additionally, having carried out the emulation of entirety to trigger, trigger 1 is improved and improves trigger 2 all realizing needs
Logic function, improve trigger 1 for existing DPL triggers, the Δ time delay that can be born reduces 89%, can bear when
The clock cycle reduces 32%, and the minimum clock cycle that improving trigger 2 in addition can bear reduces 37%.For power consumption aspect
Speech, for the DDPL triggers of prior art, the power consumption improved trigger 1 and improve trigger 2 is reduced respectively
46% and 50%, NED reduce respectively 65% and 52%, NSD reduce 71% and 63% respectively.
Can be obtained by emulation data, the present invention trigger structure in terms of speed, power consumption, power-consumption balance relative to document
All it is enhanced for middle trigger.
Above-mentioned PMOS transistor refers to n-type substrate, p-channel, partly leads by the metal-oxide of the flowing transport electric current in hole
Body field effect transistor；Nmos pass transistor refers to p-substrate, n-channel, and the metal-oxide half of electric current is transported in the flowing by free electron
Conductor field effect transistor.
Embodiment of above is merely to illustrate the present invention, rather than limitation of the present invention.Although with reference to embodiment to this
It is bright to be described in detail, it will be understood by those within the art that, technical scheme is carried out various combinations,
Modification or equivalent, without departure from the spirit and scope of technical solution of the present invention, all should cover will in right of the invention
Ask in the middle of scope.
Claims (3)
1. a kind of double track preliminary filling logical trigger based on time delay, including first order data converter, second level main latch with
And the third level is from latch, it is characterised in that the first order data converter will be based on the double track preliminary filling logical signal of time delay
Be converted to based on the logical signal of sense amplifier, logical signal of the second level main latch to be set forth in sense amplifier
Time delayed signal be acquired and latch；The third level prolonging to the output signal of the second level main latch from latch
When signal be acquired and latch；
The first order data converter includes first, second, third, fourth PMOS transistor, first, second, third, the
4th, the 5th nmos pass transistor and first, second phase inverter；
The source electrode of first PMOS transistor, the source electrode of the second PMOS transistor, the source electrode of the 3rd PMOS transistor, the 4th
The source electrode of PMOS transistor is all connected with power supply, and the grid of first PMOS transistor, the grid of the second PMOS transistor connect
Clock signal is connect, the grid of the 3rd PMOS transistor, the grid of the 4th PMOS transistor connect respectively the 4th NMOS
The grid of the grid of transistor, the 5th nmos pass transistor；The drain electrode of first PMOS transistor, the leakage of the 3rd PMOS transistor
Pole, the drain electrode of the 4th nmos pass transistor, the input of the first phase inverter are all connected with the grid of the 5th nmos pass transistor, described
The drain electrode of the second PMOS transistor, the drain electrode of the 4th PMOS transistor, the drain electrode of the 5th nmos pass transistor, the second phase inverter it is defeated
Enter the grid that end is all connected with the 4th nmos pass transistor；The source electrode of the 4th nmos pass transistor, the 5th nmos pass transistor
Source electrode connects respectively the drain electrode of second nmos pass transistor, the drain electrode of the 3rd nmos pass transistor；Second nmos pass transistor
Source electrode, the source electrode of the 3rd nmos pass transistor be all connected with the drain electrode of first nmos pass transistor, second nmos pass transistor
Grid, the grid of the 3rd nmos pass transistor connect the reverse of input signal and the input signal respectively；First NMOS
Transistor gate connects the clock signal, its source ground；The outfan of first phase inverter, the output of the second phase inverter
End is respectively based on the logical signal reverse, based on sense amplifier of the logical signal of sense amplifier；
Wherein, the second level main latch include the five, the six, the seven, the 8th PMOS transistors, the six, the seven, the 8th,
Nine, the ten, the 11st nmos pass transistors and the three, the 4th phase inverters；
The source electrode of the 5th PMOS transistor, the source electrode of the 6th PMOS transistor are all connected with power supply, the 5th PMOS crystal
The grid of pipe, the grid of the 6th PMOS transistor connect respectively the logical signal based on sense amplifier time delayed signal,
The time delayed signal of the logical signal based on sense amplifier it is reverse；The drain electrode connection of the 5th PMOS transistor is described
The drain electrode of the source electrode of the 7th PMOS transistor and the 8th nmos pass transistor；The grid connection of the 8th nmos pass transistor
The time delayed signal of the logical signal based on sense amplifier, its source electrode connects the drain electrode of the 6th nmos pass transistor；Institute
State the 7th PMOS transistor grid and connect the clock signal, the signal input part of its drain electrode connection the 3rd phase inverter and
The drain electrode of the tenth nmos pass transistor；The grid of the 6th nmos pass transistor, the grid of the tenth nmos pass transistor are all connected with
The clock signal；Source electrode, the source grounding of the tenth nmos pass transistor of the 6th nmos pass transistor；6th PMOS
The source electrode of drain electrode connection the 8th PMOS transistor of transistor and the drain electrode of the 9th nmos pass transistor；Described 8th
The grid of PMOS transistor connects the clock signal, the input and the described tenth of its drain electrode connection the 4th phase inverter
The drain electrode of one nmos pass transistor；The grid connection logical signal based on sense amplifier of the 9th nmos pass transistor
Reverse, the drain electrode of its source electrode connection the 7th nmos pass transistor of time delayed signal；The grid of the 11st nmos pass transistor,
The grid of the 7th nmos pass transistor is all connected with the clock signal；The source electrode of 11 nmos pass transistor, the 7th NMOS crystal
The source grounding of pipe；3rd phase inverter, the outfan of the 4th phase inverter are respectively the defeated of the second level main latch
Go out signal, the output signal of the second level main latch it is reverse.
2. trigger according to claim 1, it is characterised in that the second level main latch includes the 9th, the tenth, the
11, the 12nd PMOS transistor, the 12nd, the 13rd nmos pass transistor and the 5th, hex inverter；
The source electrode of the 9th PMSO transistors, the source electrode of the tenth PMOS transistor are all connected with power supply；The 9th PMSO crystal
The grid of pipe, the grid of the tenth PMOS transistor are all connected with the clock signal；The drain electrode of the 9th PMSO transistors, the tenth
The drain electrode of PMOS transistor connects respectively source electrode, the source electrode of the 12nd PMOS transistor of the 11st PMSO transistors；Institute
State the grid of the 11st PMSO transistors, the grid of the 12nd PMOS transistor and connect the patrolling based on sense amplifier respectively
The time delayed signal of volume signal, the time delayed signal of the logical signal based on sense amplifier it is reverse；11st PMSO
The input of drain electrode connection the 5th phase inverter of transistor and the drain electrode of the tenth bi-NMOS transistor；Described tenth
The input of the drain electrode connection hex inverter of two PMOS transistors and the drain electrode of the 13rd nmos pass transistor；Institute
State the grid of the tenth bi-NMOS transistor, the grid of the 13rd nmos pass transistor and be all connected with the clock signal；Described 12nd
The source grounding of the source electrode of nmos pass transistor, the 13rd nmos pass transistor；It is the outfan of the 5th phase inverter, the 6th anti-phase
The outfan of device be respectively the output signal of the second level main latch, the output signal of the second level main latch it is anti-
To.
3. trigger according to claim 1 and 2, it is characterised in that the third level includes the 13rd from latch, the
14 PMOS transistors, the 14th, the 15th, the 16th, the 17th, the 18th, the 19th nmos pass transistor and the 7th,
Eight phase inverters；
The source electrode of the 13rd PMSO transistors, the source electrode of the 14th PMSO transistors are all connected with power supply, and the described 13rd
The grid of PMSO transistors, the grid of the 14th PMSO transistors are all connected with the clock signal；The 13rd PMOS crystal
The signal input part of drain electrode connection the 7th phase inverter of pipe and the drain electrode of the 18th nmos pass transistor；Described tenth
The signal input part of drain electrode connection the 8th phase inverter of four PMOS transistors and the leakage of the 19th nmos pass transistor
Pole；The grid of the 18th nmos pass transistor, the grid of the 19th nmos pass transistor are all connected with the clock signal；Described
The source electrode of 18 nmos pass transistors connects the drain electrode of the 14th nmos pass transistor and the 16th nmos pass transistor
Drain electrode；The source electrode of the 19th nmos pass transistor connects the drain electrode and the described 15th of the 17th nmos pass transistor
The drain electrode of nmos pass transistor；The grid of the 14th nmos pass transistor, the grid of the 15th nmos pass transistor connect respectively institute
State the time delayed signal of the output signal of second level main latch, the time delayed signal of the output signal of second level main latch it is anti-
To；The grid of the 16th nmos pass transistor and the grid of the 17th nmos pass transistor are all connected with the clock signal
Time delayed signal；Source electrode, the source electrode of the 15th nmos pass transistor, the 16th nmos pass transistor of the 14th nmos pass transistor
Source electrode and the 17th nmos pass transistor source grounding；The outfan of the 7th phase inverter, the 8th phase inverter it is defeated
Go out the output signal of end respectively reverse, the described trigger of the output signal of the trigger.
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| CN102339637A (en) * | 2011-06-01 | 2012-02-01 | 北京大学 | Condition-precharged sense-amplifier-based flip flop |
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| US6876573B2 (en) * | 2001-08-09 | 2005-04-05 | Renesas Technology Corporation | Semiconductor memory device |
| CN102339637A (en) * | 2011-06-01 | 2012-02-01 | 北京大学 | Condition-precharged sense-amplifier-based flip flop |
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