CN104576852A - Stress regulation method for luminous quantum wells of GaN-based LED epitaxial structure - Google Patents
Stress regulation method for luminous quantum wells of GaN-based LED epitaxial structure Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 230000033228 biological regulation Effects 0.000 title claims abstract description 20
- 230000004888 barrier function Effects 0.000 claims abstract description 19
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910052594 sapphire Inorganic materials 0.000 claims abstract description 13
- 239000010980 sapphire Substances 0.000 claims abstract description 13
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 claims description 34
- 238000000137 annealing Methods 0.000 claims description 20
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 18
- 239000011777 magnesium Substances 0.000 claims description 16
- RGGPNXQUMRMPRA-UHFFFAOYSA-N triethylgallium Chemical compound CC[Ga](CC)CC RGGPNXQUMRMPRA-UHFFFAOYSA-N 0.000 claims description 14
- 229910052757 nitrogen Inorganic materials 0.000 claims description 11
- 239000011248 coating agent Substances 0.000 claims description 10
- 238000000576 coating method Methods 0.000 claims description 10
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 8
- 239000002019 doping agent Substances 0.000 claims description 8
- 230000008569 process Effects 0.000 claims description 8
- 230000006641 stabilisation Effects 0.000 claims description 8
- 238000011105 stabilization Methods 0.000 claims description 8
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 claims description 8
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 claims description 8
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 7
- 239000001257 hydrogen Substances 0.000 claims description 7
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- 239000002131 composite material Substances 0.000 claims description 5
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- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 229910021529 ammonia Inorganic materials 0.000 claims description 4
- 239000012159 carrier gas Substances 0.000 claims description 4
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 4
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- 238000011065 in-situ storage Methods 0.000 claims description 4
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- 229910052749 magnesium Inorganic materials 0.000 claims description 4
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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Abstract
The invention provides a stress regulation method for luminous quantum wells of a GaN-based LED epitaxial structure. The GaN-based LED epitaxial structure sequentially comprises a sapphire substrate, a low-temperature GaN nucleating layer, a high-temperature GaN buffer layer, a high-temperature u type GaN layer, a high-temperature n type GaN layer, a V-pits layer of a low-temperature stress release layer, a multi-quantum-well luminous layer, a p type AlGaN electron barrier layer, a high-temperature p-GaN layer and a compound p type GaN contact layer from bottom to top. By means of the method, the pressure stress in the quantum wells can be effectively released, the stokes effect in the MQW is weakened, the accordance probability between electronic carriers and hole carriers is increased so that the internal quantum efficiency can be improved, and the LED light-emitting efficiency is improved.
Description
Technical field
The present invention relates to GaN base LED preparing technical field, be specially a kind of luminescent quantum trap stress regulation and control method of GaN base LED epitaxial structure.
Background technology
Semiconductor light-emitting-diode (light-emission diodes, LED) has obviously advantage because it has energy-saving and environmental protection, green health, long-life etc., is used widely gradually in instruction, display, field of backlights.Along with LED is in the propelling of the application of illumination, people need the chip developing high power, high-brightness LED, replace current other light sources.
The GaN base LED generally used at present is epitaxially grown on a sapphire substrate, because of the lattice mismatch comparatively large (about 13%) of sapphire and GaN, causes there is larger compression in GaN epitaxial layer; Simultaneously because there is very large lattice mismatch (being about 11%) between InN and GaN, cause also there is very large compression in the quantum well InGaN/GaN of GaN base LED luminescent layer.On the one hand, compression can produce piezoelectric polarization electric field, the inclination causing quantum well to be with, and makes the overlapping minimizing of electronics and hole wave functions, causes the decline of internal quantum efficiency, i.e. so-called quantum confined Stark effect (QCSE); On the other hand, compression can affect effective merging of In in quantum well, makes it be difficult to be formed the quantum well of the good high In component of crystal mass, thus makes the luminous efficiency of LED lower.So the modulation of stress becomes one of key factor improving luminous efficiency in InGaN quantum well.
Summary of the invention
Technical problem solved by the invention is a kind of luminescent quantum trap stress regulation and control method providing GaN base LED epitaxial structure, the compression that part discharges the InGaN layer in MQW is carried out by introducing low temperature V-pits layer between MQW and n-GaN layer, raising electronic carrier and holoe carrier meet probability, to improve internal quantum efficiency, thus improve the luminous efficiency of LED, to solve the problem in above-mentioned background technology.
Technical problem solved by the invention realizes by the following technical solutions: a kind of luminescent quantum trap stress regulation and control method of GaN base LED epitaxial structure, its epitaxial structure, order from bottom to top comprises successively: Sapphire Substrate, low temperature GaN nucleating layer, high temperature GaN resilient coating, high temperature u-GaN layer, high temperature n-type GaN layer, low temperature stress release layer V-pits layer, multiple quantum well light emitting layer, p-type AlGaN electronic barrier layer, high temperature p-GaN layer, composite p-type GaN contact layer; Its stress regulation and control method, comprises the following steps:
Step one, Sapphire Substrate, anneals in hydrogen atmosphere, clean sapphire substrate surface, and temperature controls, between 1050-1100 DEG C, then to carry out nitrogen treatment 5-10min;
Step 2, drops between 500-550 DEG C by temperature, the low temperature GaN nucleating layer that growth 25-35nm is thick, growth pressure controls between 500-550Torr, V/III mol ratio between 80-120, graphite plate stabilization of speed at 500-600 rev/min, TMGa as Ga source;
Step 3, after described low temperature GaN nucleating layer growth terminates, carry out in-situ annealing process, growth thickness is the high temperature GaN resilient coating between 0.5-1um;
Step 4, after described high temperature GaN buffer growth terminates, growth one deck undoped high temperature u-GaN layer;
Step 5, after described high temperature undoped GaN layer growth terminates, growth one deck high temperature n-type GaN layer;
Step 6, after described high temperature n-type GaN layer growth terminates, growing low temperature stress release layer V-pits layer, low temperature stress release layer V-pits layer thickness controls at 200-300nm, growth temperature controls between 800-860 DEG C, pressure between 300-350Torr, growth rate 1.0-1.5um/hr, V/III mol ratio is between 1600-2000, and Si doping content is 10
15-10
16cm
-3between, use TMGa to provide Ga source;
Step 7, after described low temperature stress release layer V-pits layer growth terminates, growth one deck multiple quantum well light emitting layer;
Step 8, after described multiple quantum well light emitting layer terminates, growth p-type AlGaN electronic barrier layer;
Step 9, after described p-type AlGaN electronic barrier layer terminates, growth high temperature p-GaN layer;
Step 10, after described high temperature p-GaN layer growth terminates, growing mixed p-type GaN contact layer;
After above outer layer growth terminates, chamber pressure is dropped to 100Torr, temperature is down to 750-800 DEG C, adopts pure nitrogen gas atmosphere to carry out annealing in process 5-10min, is then down to room temperature, terminate growth.
In described step 3, high temperature GaN buffer growth pressure is between 500-550Torr, and V/III mol ratio is between 200-250, and TMGa is as Ga source.
In described step 3 between annealing temperature 1020-1040 DEG C, annealing time is between 7-10min; After annealing, by temperature stabilization between 980-1000 DEG C.
In described step 4, high temperature u-GaN layer growth thickness is between 2-2.5um, and growth temperature controls between 1080-1100 DEG C, and growth pressure is between 200-250Torr, and V/III mol ratio, between 120-200, utilizes TMGa as Ga source.
In described step 5, high temperature n-type GaN layer thickness is between 2-3.5um, and growth temperature is between 1070-1090 DEG C, and pressure is between 200-250Torr, and V/III mol ratio is between 100-180, and Si doping content is 10
18-10
19cm
-3between, utilize TMGa to provide Ga source.
In described step 7 multiple quantum well light emitting layer by 6-9 cycle InGaN/GaN trap build structure form, the cycle of single quantum well between 8-12nm, In
yga
1-ythe thickness of N (y=0.2-0.3) well layer and GaN barrier layer is between 1:2-1:3; Growth pressure is between 300-350Torr, and Ga source provides by TEGa, and V/III mol ratio is between 2000-3500.
In described step 8, its growth temperature of p-type AlGaN electronic barrier layer controls between 900-950 DEG C, growth pressure between 100-150Torr, V/III mol ratio between 80-120, thickness between 25-35nm, p-Al
zga
1-zin N layer, z is between 0.2-0.3, and Mg doping content is 10
15-10
16cm
-3between, utilize TMGa to provide Ga source.
In described step 9, high temperature p-GaN layer growth temperature controls between 950-1000 DEG C, and pressure is between 450-500Torr, and V/III mol ratio is between 200-300, and p-GaN layer growth thickness controls between 50-100nm, and Mg doping content is 10
17-10
18cm
-3between, utilize TMGa to provide Ga source.
In described step 10 between composite p-type GaN contact layer thickness 5-10nm, use TEGa to provide Ga source, Mg doping content is 10
14-10
15cm
-3between, In/Ga ratio controls between 0.1-0.3, and control growth temperature between 750-800 DEG C, pressure is between 200-250Torr, and V/III mol ratio is between 1000-1500;
Institute's growing epitaxial sheet, after the follow-up chip processing procedures such as cleaning, deposition, photoetching and etching, is processed into the LED chip of 7mil × 14mil.
The present invention using high-purity hydrogen or nitrogen as carrier gas, with trimethyl gallium (TMGa) or triethyl-gallium (TEGa), trimethyl aluminium (TMAl), trimethyl indium (TMIn) and ammonia (NH
3) respectively as Ga, Al, In and N source, n-type dopant is silane (SiH
4), p-type dopant is two luxuriant magnesium (Cp
2mg).
Compared with public technology, there is following advantage in the present invention: the present invention effectively can discharge the compression in quantum well, weakens the Stokes effect in MQW, and raising electronic carrier and holoe carrier meet probability, to improve internal quantum efficiency, thus improve the luminous efficiency of LED.
Accompanying drawing explanation
Fig. 1 is epitaxial structure schematic diagram of the present invention.
Fig. 2 is conventional epitaxial structure extension sheet COW test brightness LOP1 distribution map.
Fig. 3 is conventional epitaxial structure extension sheet COW test wavelength WLD1 distribution map.
Fig. 4 is epitaxial structure epitaxial wafer COW test brightness LOP1 distribution map of the present invention.
Fig. 5 is epitaxial structure epitaxial wafer COW test wavelength WLD1 distribution map of the present invention.
In figure: 1-Sapphire Substrate, 2-low temperature GaN nucleating layer, 3-high temperature GaN resilient coating, 4-high temperature u-GaN layer, 5-high temperature n-type GaN layer, 6-low temperature stress release layer V-pits layer, 7-multiple quantum well light emitting layer, 8-p type AlGaN electronic barrier layer, 9-high temperature p-GaN layer, 10-recombination P-type GaN contact layer.
Embodiment
Object is reached and effect is easy to understand in order to make technological means of the present invention, creation characteristic, workflow, using method, below in conjunction with the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
As shown in Figure 1, a kind of LED epitaxial structure, order from bottom to top comprises successively: Sapphire Substrate 1, low GaN temperature nucleating layer 2, high temperature GaN resilient coating 3, high temperature u-GaN layer 4, high temperature n-type GaN layer 5, low temperature stress release layer V-pits layer 6, multiple quantum well light emitting layer 7, p-type AlGaN electronic barrier layer 8, high temperature p-GaN layer 9, composite p-type GaN contact layer 10.
Embodiment 1
A luminescent quantum trap stress regulation and control method for GaN base LED epitaxial structure, comprises the following steps:
Step one, Sapphire Substrate 1, anneals in hydrogen atmosphere, clean described substrate 1 surface, and temperature controls, at 1050 DEG C, then to carry out nitrogen treatment 10min;
Step 2, drops to 550 DEG C by temperature, the low temperature GaN nucleating layer 2 that growth 35nm is thick, and growth pressure controls at 550Torr, and V/III mol ratio is 120, and graphite plate stabilization of speed is at 600 revs/min, and TMGa is as Ga source;
Step 3, after described low temperature GaN nucleating layer 2 growth terminates, carry out in-situ annealing process, annealing temperature 1040 DEG C, annealing time is at 10min; After annealing, by temperature stabilization to 1000 DEG C, growth thickness is the high temperature GaN resilient coating 3 of 1um, growth pressure at 550Torr, V/III mol ratio at 250, TMGa as Ga source;
Step 4, after described high temperature GaN resilient coating 3 growth terminates, the u-GaN layer 4 of growth one deck undoped, growth thickness is at 2.5um, and growth temperature controls at 1100 DEG C, and growth pressure is at 250Torr, and V/III mol ratio, 200, utilizes TMGa as Ga source;
Step 5, after described high temperature undoped GaN layer 4 growth terminates, growth one deck high temperature compound n-GaN layer 5; Thickness is 3.5um, growth temperature at 1090 DEG C, pressure at 250Torr, V/III mol ratio in 180, Si doping content 10
18-10
19cm
-3between, utilize TMGa to provide Ga source;
Step 6, after described high temperature n-type GaN layer 5 growth terminates, growing low temperature stress release layer V-pits layer, this layer is core layer of the present invention, and THICKNESS CONTROL is at 300nm, and growth temperature controls at 860 DEG C, pressure is at 350Torr, growth rate 1.5um/hr, V/III mol ratio in 2000, Si doping content 10
15-10
16cm
-3between, use TMGa to provide Ga source,
Step 7, after the growth of low temperature stress release layer V-pits layer 6 terminates, growth multicycle mqw light emitting layer 7, Multiple Quantum Well 7 is built structure by the InGaN/GaN trap in 6-9 cycle and is formed, and the cycle of single quantum well is at 12nm, In
yga
1-ythe thickness of N (y=0.2-0.3) well layer and GaN barrier layer is between 1:2-1:3; Growth pressure provides by TEGa in 350Torr, Ga source, and V/III mol ratio is 3500;
Step 8, after described multiple quantum well light emitting layer 7 terminates, growth p-type AlGaN electronic barrier layer 8, its growth temperature controls at 950 DEG C, and growth pressure is at 150Torr, and V/III mol ratio is 120, and thickness is at 35nm, p-Al
zga
1-zin N layer, z is between 0.2-0.3, and Mg doping content is 10
15-10
16cm
-3between, utilize TMGa to provide Ga source;
Step 9, after described p-type AlGaN electronic barrier layer 8 terminates, growth high temperature p-type GaN layer 9, its growth temperature controls at 1000 DEG C, and pressure is at 500Torr, and V/III mol ratio is 300, and p-GaN layer growth thickness controls in 100nm, Mg doping content 10
17-10
18cm
-3between, utilize TMGa to provide Ga source;
Step 10, after described high temperature p-type GaN layer 9 growth terminates, growth p-type GaN contact layer 10, thickness 10nm, use TEGa to provide Ga source, Mg doping content is 10
14-10
15cm
-3between, In/Ga ratio controls 0.3, and control growth temperature at 800 DEG C, pressure is at 250Torr, and V/III mol ratio is 1500;
After above outer layer growth terminates, chamber pressure is dropped to 100Torr, temperature is down to 800 DEG C, adopts pure nitrogen gas atmosphere to carry out annealing in process 10min, is then down to room temperature, terminate growth.Namely LED epitaxial structure is as shown in Figure 1 obtained.
Institute's growing epitaxial sheet, after the follow-up chip processing procedures such as cleaning, deposition, photoetching and etching, is processed into the LED chip of 7mil × 14mil.
The present embodiment using nitrogen as carrier gas, with triethyl-gallium (TEGa), trimethyl aluminium (TMAl), trimethyl indium (TMIn) and ammonia (NH
3) respectively as Ga, Al, In and N source, n-type dopant is silane (SiH
4), p-type dopant is two luxuriant magnesium (Cp
2mg).
Embodiment 2
A luminescent quantum trap stress regulation and control method for GaN base LED epitaxial structure, comprise the following steps: step one, Sapphire Substrate 1, anneals in hydrogen atmosphere, clean described substrate 1 surface, and temperature controls, at 1050 DEG C, then to carry out nitrogen treatment 5min;
Step 2, drops to 500 DEG C by temperature, the low temperature GaN nucleating layer 2 that growth 25nm is thick, and growth pressure controls at 500Torr, and V/III mol ratio is 80, and graphite plate stabilization of speed is at 500 revs/min, and TMGa is as Ga source;
Step 3, after described low temperature GaN nucleating layer 2 growth terminates, carry out in-situ annealing process, annealing temperature 1020 DEG C, annealing time is at 7min; After annealing, by temperature stabilization to 980 DEG C, growth thickness is the high temperature GaN resilient coating 3 of 0.5um, growth pressure at 500Torr, V/III mol ratio at 200, TMGa as Ga source;
Step 4, after described high temperature GaN resilient coating 3 growth terminates, the u-GaN layer 4 of growth one deck undoped, growth thickness is at 2um, and growth temperature controls at 1080 DEG C, and growth pressure is at 200Torr, and V/III mol ratio, 120, utilizes TMGa as Ga source;
Step 5, after described high temperature undoped GaN layer 4 growth terminates, growth one deck high temperature n-GaN layer 5; Thickness is 2um, growth temperature at 1070 DEG C, pressure between 200Torr, V/III mol ratio in 100, Si doping content 10
18-10
19cm
-3between, utilize TMGa to provide Ga source;
Step 6, after described high temperature n-type GaN layer 5 growth terminates, growing low temperature stress release layer V-pits layer, this layer is core layer of the present invention, and THICKNESS CONTROL is at 200nm, and growth temperature controls at 800 DEG C, pressure is at 300Torr, growth rate 1.0um/hr, V/III mol ratio in 1600, Si doping content 10
15-10
16cm
-3between, use TMGa to provide Ga source,
Step 7, after the growth of low temperature stress release layer V-pits layer 6 terminates, growth multicycle mqw light emitting layer 7, Multiple Quantum Well 7 is built structure by the InGaN/GaN trap in 6-9 cycle and is formed, and the cycle of single quantum well is at 8nm, In
yga
1-ythe thickness of N (y=0.2-0.3) well layer and GaN barrier layer is between 1:2-1:3; Growth pressure provides by TEGa in 300Torr, Ga source, and V/III mol ratio is 2000;
Step 8, after described multiple quantum well light emitting layer 7 terminates, growth p-type AlGaN electronic barrier layer 8, its growth temperature controls at 900 DEG C, and growth pressure is at 100Torr, and V/III mol ratio is 80, and thickness is at 25nm, p-Al
zga
1-zin N layer, z is between 0.2-0.3, and Mg doping content is 10
15-10
16cm
-3between, utilize TMGa to provide Ga source;
Step 9, after described p-type AlGaN electronic barrier layer 8 terminates, growth high temperature p-type GaN layer 9, its growth temperature controls at 950 DEG C, and pressure is at 450Torr, and V/III mol ratio is 200, and p-GaN layer growth thickness controls in 50nm, Mg doping content 10
17-10
18cm
-3between, utilize TMGa to provide Ga source;
Step 10, after described high temperature p-type GaN layer 9 growth terminates, growth p-type GaN contact layer 10, thickness 5nm, use TEGa to provide Ga source, Mg doping content is 10
14-10
15cm
-3between, In/Ga ratio controls 0.1, and control growth temperature at 750 DEG C, pressure is at 200Torr, and V/III mol ratio is 1000;
After above outer layer growth terminates, chamber pressure is dropped to 100Torr, temperature is down to 750 DEG C, adopts pure nitrogen gas atmosphere to carry out annealing in process 5-10min, is then down to room temperature, terminate growth.Namely LED epitaxial structure is as shown in Figure 1 obtained.
Institute's growing epitaxial sheet, after the follow-up chip processing procedures such as cleaning, deposition, photoetching and etching, is processed into the LED chip of 7mil × 14mil.
The present embodiment using high-purity hydrogen as carrier gas, with trimethyl gallium (TMGa), trimethyl aluminium (TMAl), trimethyl indium (TMIn) and ammonia (NH
3) respectively as Ga, Al, In and N source, n-type dopant is silane (SiH
4), p-type dopant is two luxuriant magnesium (Cp
2mg).
The luminosity that effectively can improve LED of the present invention.Distribution uses conventional epitaxial structure and epitaxial structures growth epitaxial wafer of the present invention, is made into 7mil × 14mil chip simultaneously, under operating current 60mA condition, carries out COW luminance test respectively, and result improves 13.6% for adopting epitaxial wafer luminosity of the present invention.As accompanying drawing 2, Fig. 3, be the chip not adopting epitaxial wafer of the present invention to make, the mapping figure distribution of COW test dies, the average 49.1mW of the average 453.1nm of its wavelength WLD1, corresponding brightness LOP1; Accompanying drawing 4, Fig. 5 are the chip adopting epitaxial wafer of the present invention to make, the mapping figure distribution of COW test dies, the average 55.8mW of the average 453.4nm of its wavelength WLD1, corresponding brightness LOP1.
More than show and describe general principle of the present invention, principal character and advantage of the present invention.The technical staff of the industry should understand; the present invention is not restricted to the described embodiments; what describe in above-described embodiment and specification just illustrates principle of the present invention; without departing from the spirit and scope of the present invention; the present invention also has various changes and modifications, and these changes and improvements all fall in the claimed scope of the invention.Claimed scope of the present invention is defined by appending claims and equivalent thereof.
Claims (10)
1. the luminescent quantum trap stress regulation and control method of a GaN base LED epitaxial structure, its epitaxial structure, order from bottom to top comprises successively: Sapphire Substrate, low temperature GaN nucleating layer, high temperature GaN resilient coating, high temperature u-GaN layer, high temperature n-type GaN layer, low temperature stress release layer V-pits layer, multiple quantum well light emitting layer, p-type AlGaN electronic barrier layer, high temperature p-GaN layer, composite p-type GaN contact layer; It is characterized in that: its stress regulation and control method, comprises the following steps:
Step one, Sapphire Substrate, anneals in hydrogen atmosphere, clean sapphire substrate surface, and temperature controls, between 1050-1100 DEG C, then to carry out nitrogen treatment 5-10min;
Step 2, drops between 500-550 DEG C by temperature, the low temperature GaN nucleating layer that growth 25-35nm is thick, growth pressure controls between 500-550Torr, V/III mol ratio between 80-120, graphite plate stabilization of speed at 500-600 rev/min, TMGa as Ga source;
Step 3, after described low temperature GaN nucleating layer growth terminates, carry out in-situ annealing process, growth thickness is the high temperature GaN resilient coating between 0.5-1um;
Step 4, after described high temperature GaN buffer growth terminates, growth one deck undoped high temperature u-GaN layer;
Step 5, after described high temperature undoped GaN layer growth terminates, growth one deck high temperature n-type GaN layer;
Step 6, after described high temperature n-type GaN layer growth terminates, growing low temperature stress release layer V-pits layer, low temperature stress release layer V-pits layer thickness controls at 200-300nm, growth temperature controls between 800-860 DEG C, pressure between 300-350Torr, growth rate 1.0-1.5um/hr, V/III mol ratio is between 1600-2000, and Si doping content is 10
15-10
16cm
-3between, use TMGa to provide Ga source;
Step 7, after low temperature stress release layer V-pits layer growth terminates, growth one deck multiple quantum well light emitting layer;
Step 8, after described multiple quantum well light emitting layer terminates, growth p-type AlGaN electronic barrier layer;
Step 9, after described p-type AlGaN electronic barrier layer terminates, growth high temperature p-GaN layer;
Step 10, after described high temperature p-GaN layer growth terminates, growing mixed p-type GaN contact layer;
After above outer layer growth terminates, chamber pressure is dropped to 100Torr, temperature is down to 750-800 DEG C, adopts pure nitrogen gas atmosphere to carry out annealing in process 5-10min, is then down to room temperature, terminate growth.
2. the luminescent quantum trap stress regulation and control method of a kind of GaN base LED epitaxial structure according to claim 1, it is characterized in that: in described step 3, high temperature GaN buffer growth pressure is between 500-550Torr, V/III mol ratio is between 200-250, and TMGa is as Ga source.
3. the luminescent quantum trap stress regulation and control method of a kind of GaN base LED epitaxial structure according to claim 1, is characterized in that: in described step 3 between annealing temperature 1020-1040 DEG C, annealing time is between 7-10min; After annealing, by temperature stabilization between 980-1000 DEG C.
4. the luminescent quantum trap stress regulation and control method of a kind of GaN base LED epitaxial structure according to claim 1, it is characterized in that: in described step 4, high temperature u-GaN layer growth thickness is between 2-2.5um, growth temperature controls between 1080-1100 DEG C, growth pressure is between 200-250Torr, V/III mol ratio, between 120-200, utilizes TMGa as Ga source.
5. the luminescent quantum trap stress regulation and control method of a kind of GaN base LED epitaxial structure according to claim 1, it is characterized in that: in described step 5, high temperature n-type GaN layer thickness is between 2-3.5um, growth temperature is between 1070-1090 DEG C, pressure is between 200-250Torr, V/III mol ratio is between 100-180, and Si doping content is 10
18-10
19cm
-3between, utilize TMGa to provide Ga source.
6. the luminescent quantum trap stress regulation and control method of a kind of GaN base LED epitaxial structure according to claim 1, it is characterized in that: in described step 7, multiple quantum well light emitting layer is made up of the InGaN/GaN trap base structure in 6-9 cycle, the cycle of single quantum well between 8-12nm, In
yga
1-ythe thickness of N (y=0.2-0.3) well layer and GaN barrier layer is between 1:2-1:3; Growth pressure is between 300-350Torr, and Ga source provides by TEGa, and V/III mol ratio is between 2000-3500.
7. the luminescent quantum trap stress regulation and control method of a kind of GaN base LED epitaxial structure according to claim 1, it is characterized in that: in described step 8, its growth temperature of p-type AlGaN electronic barrier layer controls between 900-950 DEG C, growth pressure is between 100-150Torr, V/III mol ratio is between 80-120, thickness between 25-35nm, p-Al
zga
1-zin N layer, z is between 0.2-0.3, and Mg doping content is 10
15-10
16cm
-3between, utilize TMGa to provide Ga source.
8. the luminescent quantum trap stress regulation and control method of a kind of GaN base LED epitaxial structure according to claim 1, it is characterized in that: in described step 9, high temperature p-GaN layer growth temperature controls between 950-1000 DEG C, pressure is between 450-500Torr, V/III mol ratio is between 200-300, p-GaN layer growth thickness controls between 50-100nm, and Mg doping content is 10
17-10
18cm
-3between, utilize TMGa to provide Ga source.
9. the luminescent quantum trap stress regulation and control method of a kind of GaN base LED epitaxial structure according to claim 1, is characterized in that: in described step 10 between composite p-type GaN contact layer thickness 5-10nm, and use TEGa to provide Ga source, Mg doping content is 10
14-10
15cm
-3between, In/Ga ratio controls between 0.1-0.3, and control growth temperature between 750-800 DEG C, pressure is between 200-250Torr, and V/III mol ratio is between 1000-1500.
10. the luminescent quantum trap stress regulation and control method of a kind of GaN base LED epitaxial structure according to claim 1, it is characterized in that: its growth course using high-purity hydrogen or nitrogen as carrier gas, with trimethyl gallium (TMGa) or triethyl-gallium (TEGa), trimethyl aluminium (TMAl), trimethyl indium (TMIn) and ammonia (NH
3) respectively as Ga, Al, In and N source, n-type dopant is silane (SiH
4), p-type dopant is two luxuriant magnesium (Cp
2mg).
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