CN104576715A - Germanium-silicon heterojunction bipolar transistor and manufacturing method thereof - Google Patents
Germanium-silicon heterojunction bipolar transistor and manufacturing method thereof Download PDFInfo
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- CN104576715A CN104576715A CN201410354317.5A CN201410354317A CN104576715A CN 104576715 A CN104576715 A CN 104576715A CN 201410354317 A CN201410354317 A CN 201410354317A CN 104576715 A CN104576715 A CN 104576715A
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- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 86
- 239000002184 metal Substances 0.000 claims abstract description 86
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 43
- 239000010703 silicon Substances 0.000 claims abstract description 43
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 99
- 239000011229 interlayer Substances 0.000 claims description 42
- 238000000034 method Methods 0.000 claims description 35
- 238000002513 implantation Methods 0.000 claims description 32
- 238000005468 ion implantation Methods 0.000 claims description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 18
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 18
- 230000004888 barrier function Effects 0.000 claims description 18
- 239000010936 titanium Substances 0.000 claims description 18
- 229910052719 titanium Inorganic materials 0.000 claims description 18
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 18
- 229910052721 tungsten Inorganic materials 0.000 claims description 18
- 239000010937 tungsten Substances 0.000 claims description 18
- 238000005516 engineering process Methods 0.000 claims description 15
- 238000000926 separation method Methods 0.000 claims description 13
- 230000008569 process Effects 0.000 claims description 12
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 229910052732 germanium Inorganic materials 0.000 claims description 7
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 7
- 230000001105 regulatory effect Effects 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 abstract description 5
- 238000009933 burial Methods 0.000 abstract 2
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 10
- 230000006872 improvement Effects 0.000 description 9
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 4
- 239000012528 membrane Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000012634 fragment Substances 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66242—Heterojunction transistors [HBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Abstract
The invention discloses a germanium-silicon heterojunction bipolar transistor. The germanium-silicon heterojunction bipolar transistor is formed on a P-epitaxial layer of a P+silicon substrate, an active region is isolated by field oxide regions, and a collector region is formed in the active region and extends to enter the bottoms of the field oxide regions on the two sides of the active region; burial layers are formed at the bottoms of the field oxide regions on the two sides of the active region and in contact with the collector region, and first deep hole contacts are formed in the field oxide regions at the tops of the burial layers so that collecting electrodes are led out; a base region consisting of a germanium-silicon epitaxial layer, and an emitter region consisting of polysilicon are successively formed at the top of the collector region, and metal contacts are respectively formed at the tops of the base region and the emitter region; a second deep hole contact penetrating through an interlaminar film and the P-epitaxial layer is formed at the exterior zone of a device, and an emitter is connected with the second deep hole contact and connected to the P+ silicon substrate through top metal layers. The invention further discloses a manufacturing method of the germanium-silicon heterojunction bipolar transistor. According to the germanium-silicon heterojunction bipolar transistor provided by the invention, the structure of the device is not required to be changed, the ground spurious inductance of the device can be reduced, and the power characteristic of the device is improved.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of Ge-Si heterojunction bipolar transistor; The invention still further relates to a kind of manufacture method of Ge-Si heterojunction bipolar transistor.
Background technology
Increasingly mature along with germanium silicon (SiGe) technique, radio circuit is integrated also more and more general, radio frequency acceptance, radio-frequency transmissions and switch etc. all tend to integrated, the power amplifier (PA) of the low noise amplifier (LNA) and amplifying emission signal that therefore amplify acknowledge(ment) signal all should make on the same chip, therefore require on same set of SiGe technique platform, only to change the high pressure Ge-Si heterojunction bipolar transistor (SiGe HBT) that domain can design different puncture voltage, with the demand of satisfied different amplifier.Traditional high pressure SiGe HBT adopts heavily doped n type buried layer (NBL), the lightly doped collector region of extension, the puncture voltage of device is changed by change collector region thickness and doping content, the extraction of collector region connects NBL by N+Sinker to realize, therefore conventional high-tension SiGe HBT obtains different puncture voltages by the change of technique, same chip can not realize the SiGe HBT of different puncture voltage, thus limit the system integration of radio circuit.
Meanwhile, in Designing power amplifier, in order to obtain higher power efficiency, the stray inductance over the ground (ground inductance) of device must be reduced.In existing structure, usual employing silicon through hole (Through SiliconVias, TSV) structure realizes the front side emitter pole of Ge-Si heterojunction bipolar transistor to be connected with the P+ silicon substrate at the back side, thus reduce the stray inductance over the ground of device, but TSV technique is more complicated, cost is high, has very large fragment risk when grinding overleaf simultaneously.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of Ge-Si heterojunction bipolar transistor, does not need carry out changing the stray inductance over the ground that just can reduce device to device architecture and improve the power characteristic of device.For this reason, the present invention also will provide a kind of manufacture method of Ge-Si heterojunction bipolar transistor.
For solving the problems of the technologies described above, the invention provides a kind of Ge-Si heterojunction bipolar transistor, comprising:
P+ silicon substrate, described P+ silicon substrate is formed with P-epitaxial loayer, in described P-epitaxial loayer, isolate active area by Chang Yang district.
One collector region, is made up of the N-type ion implanted region be formed in described active area, and the described collector region degree of depth is greater than the degree of depth bottom described Chang Yang district and the horizontal expansion of described collector region enters bottom the Chang Yang district of both sides, described active area.
One counterfeit buried regions, be made up of the N-type ion implanted region bottom the Chang Yang district being formed at both sides, described active area, the part that the horizontal expansion of described counterfeit buried regions and described collector region enters bottom described Chang Yang district contacts.
One base, is made up of the P type germanium silicon epitaxial layer be formed on described silicon substrate, comprises an intrinsic base region and an outer base area, and described intrinsic base region is formed at top, described active area and is formed with described collector region and contacts, and described outer base area is formed at top, described Chang Yang district.
One emitter region, is made up of the N-type polycrystalline silicon being formed at described intrinsic base region top, is formed contact with described intrinsic base region.
Interlayer film, covers the described P-epi-layer surface outside the described emitter region of Ge-Si heterojunction bipolar transistor, described base and surface, described Chang Yang district and described Ge-Si heterojunction bipolar transistor region.
The Metal Contact of described interlayer film is formed through respectively in described outer base area and top, described emitter region, the described Metal Contact being positioned at top, described outer base area contacts with described outer base area and for drawing base stage, and the described Metal Contact being positioned at top, described emitter region contacts with described emitter region and for drawing emitter.
Be formed through first deep hole contact in described interlayer film and described Chang Yang district at the top of described counterfeit buried regions, described first deep hole contact contacts with described counterfeit buried regions and for drawing collector electrode.
Outside described Ge-Si heterojunction bipolar transistor region, be formed through the second deep hole contact of described interlayer film and described P-epitaxial loayer, described second deep hole contact contacts with described P+ silicon substrate; Described emitter to be connected with described second deep hole contact by metal layer at top and to connect described P+ silicon substrate by described second deep hole contact, can reduce the stray inductance over the ground of described Ge-Si heterojunction bipolar transistor.
Further improvement is, described Metal Contact by after deposit titanium in the contact hole formed in described Metal Contact position and titanium nitride barrier metal layer, insert tungsten again and formed; Described first deep hole contact by after deposit titanium in the first deep hole formed in described first deep hole contact position and titanium nitride barrier metal layer, insert tungsten again and formed; Described second deep hole contact by after deposit titanium in the second deep hole formed in described second deep hole contact position and titanium nitride barrier metal layer, insert tungsten again and formed.
Further improvement is, described counterfeit buried regions on lateral attitude and described active area to be separated by a lateral separation, by the puncture voltage regulating the lateral separation of described counterfeit buried regions and described active area to regulate described Ge-Si heterojunction bipolar transistor.
For solving the problems of the technologies described above, the manufacture method of Ge-Si heterojunction bipolar transistor provided by the invention comprises the steps:
Step one, on P+ silicon substrate, form P-epitaxial loayer, in described P-epitaxial loayer, form Chang Yang district groove, and go out active area by Chang Yang district trench isolations.
Step 2, form counterfeit buried regions in the N-type ion implantation of carrying out of the described Chang Yang district channel bottom of both sides, described active area.
Step 3, insert in described Chang Yang district groove silica formed Chang Yang district.
Step 4, in described active area, carry out N-type ion implantation form collector region, the described collector region degree of depth be greater than the degree of depth bottom described Chang Yang district and the horizontal expansion of described collector region enter both sides, described active area Chang Yang district bottom and formed with described counterfeit buried regions and contact.
Step 5, carry out on described silicon substrate P type germanium and silicon epitaxial layer growth formed base, described base comprises an intrinsic base region and an outer base area, described intrinsic base region is formed at top, described active area and is formed with described collector region and contacts, and described outer base area is formed at top, described Chang Yang district.
Step 6, to carry out N-type polycrystalline silicon growth form emitter region on described intrinsic base region top, described emitter region is formed with described intrinsic base region and contacts.
Step 7, formation interlayer film, described interlayer film covers the described P-epi-layer surface outside the described emitter region of Ge-Si heterojunction bipolar transistor, described base and surface, described Chang Yang district and described Ge-Si heterojunction bipolar transistor region.
Step 8, form the Metal Contact through described interlayer film respectively in described outer base area and top, described emitter region, the described Metal Contact being positioned at top, described outer base area contacts with described outer base area and for drawing base stage, and the described Metal Contact being positioned at top, described emitter region contacts with described emitter region and for drawing emitter.
Form the first deep hole contact through described interlayer film and described Chang Yang district at the top of described counterfeit buried regions, described first deep hole contact contacts with described counterfeit buried regions and for drawing collector electrode.
Outside described Ge-Si heterojunction bipolar transistor region, form the second deep hole contact through described interlayer film and described P-epitaxial loayer, described second deep hole contact contacts with described P+ silicon substrate.
Step 8, form metal layer at top at described interlayer film top, described metal layer at top is more than one deck, described metal layer at top forms described collector electrode, described base stage and described emitter respectively, described emitter to be connected with described second deep hole contact by metal layer at top and to connect described P+ silicon substrate by described second deep hole contact, can reduce the stray inductance over the ground of described Ge-Si heterojunction bipolar transistor.
Further improvement is, the N-type ion implantation technology condition of counterfeit buried regions described in step 2 is: implantation dosage 1e14cm
-2~ 1e16cm
-2, Implantation Energy 1KeV ~ 100KeV.
Further improvement is, the N-type ion implantation technology condition of collector region described in step 4 is: implantation dosage 1e12cm
-2~ 5e14cm
-2, Implantation Energy is 50KeV ~ 500KeV.
Further improvement is, the type of P described in step 5 germanium silicon epitaxial layer adopts boron doping, and wherein intrinsic base region adopts the doping in place of outer time delay, and the boron doped technique of outer base area is ion implantation technology, and process conditions are: implantation dosage is 1e14cm
-2~ 1e16cm
-2, Implantation Energy is 1KeV ~ 50KeV; Being distributed as of germanium is trapezoidal profile or Triangle-Profile.
Further improvement is, the N-type polycrystalline silicon of emitter region described in step 6 is adulterated by N-type ion implantation, and the process conditions of described N-type ion implantation are: implantation dosage 1e14cm
-2~ 1e16cm
-2, Implantation Energy 10KeV ~ 200KeV.
Further improvement is, the step of the described Metal Contact of the formation in step 8 comprises and first forms contact hole in described Metal Contact position, afterwards in described contact hole after deposit titanium and titanium nitride barrier metal layer, insert tungsten again and formed; The step forming described first deep hole contact comprises and first forms the first deep hole in described first deep hole contact position, afterwards in described first deep hole after deposit titanium and titanium nitride barrier metal layer, insert tungsten again and formed; The step forming described second deep hole contact comprises and first forms the second deep hole in described second deep hole contact position, afterwards in described second deep hole after deposit titanium and titanium nitride barrier metal layer, insert tungsten again and formed.
Further improvement is, counterfeit buried regions described in step 2 on lateral attitude and described active area to be separated by a lateral separation, by the puncture voltage regulating the lateral separation of described counterfeit buried regions and described active area to regulate described Ge-Si heterojunction bipolar transistor.
Ge-Si heterojunction bipolar transistor of the present invention have employed counterfeit buried structure, and counterfeit buried regions is positioned at the bottom in Chang Yang district, can regulate and improve the puncture voltage of device by regulating the lateral separation of counterfeit buried regions and active area; Collector electrode is drawn by the first deep hole contact that have passed through interlayer film and Chang Yang district being formed at counterfeit buried regions top, can greatly reduction of device area and reduce the dead resistance of device.Avoid in prior art the structure needing to form n type buried layer in the bottom of P-epitaxial loayer after adopting counterfeit buried regions simultaneously, therefore device architecture of the present invention is easy to the second deep hole contact of being formed outside Ge-Si heterojunction bipolar transistor region through interlayer film and P-epitaxial loayer, the bottom of the second deep hole contact can directly contact with P+ silicon substrate, the top of the second deep hole contact then to be contacted with emitter by metal layer at top thus realize the connection of emitter and P+ silicon substrate, because the second deep hole contact is positioned at outside Ge-Si heterojunction bipolar transistor region, therefore can not impact the structure of device own, and the connection of emitter and P+ silicon substrate can reduce the stray inductance over the ground of device and improve the power characteristic of device, so the present invention does not need carry out changing the stray inductance over the ground that just can reduce device to device architecture and improve the power characteristic of device.
In addition, relative to needing in prior art to use through whole silicon substrate and needing to carry out thinning through-silicon via structure to silicon substrate, second deep hole contact of the present invention only needs through interlayer film and P-epitaxial loayer, process complexity and process costs can be reduced, reduce fragment risk when grinding overleaf.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is embodiment of the present invention Ge-Si heterojunction bipolar transistor structural representation;
Fig. 2 A-Fig. 2 J is the Ge-Si heterojunction bipolar transistor structural representation in each step of embodiment of the present invention manufacture method.
Embodiment
As shown in Figure 1, be embodiment of the present invention Ge-Si heterojunction bipolar transistor structural representation; Embodiment of the present invention Ge-Si heterojunction bipolar transistor comprises:
P+ silicon substrate 1, described P+ silicon substrate 1 is formed with P-epitaxial loayer 2, in described P-epitaxial loayer 2, isolate active area by Chang Yang district 3, also namely described active area by described Chang Yang district 3 around described P-epitaxial loayer 2 form.
One collector region 4, is made up of the N-type ion implanted region be formed in described active area, and described collector region 4 degree of depth is greater than the degree of depth bottom described Chang Yang district 3 and described collector region 4 horizontal expansion enters bottom the Chang Yang district 3 of both sides, described active area.The N-type ion implantation technology condition of described collector region 4 is: implantation dosage 1e12cm
-2~ 5e14cm
-2, Implantation Energy is 50KeV ~ 500KeV.
One counterfeit buried regions 5, be made up of the N-type ion implanted region bottom the Chang Yang district 3 being formed at both sides, described active area, the part that the horizontal expansion of described counterfeit buried regions 5 and described collector region 4 enters bottom described Chang Yang district 3 contacts.Be preferably, described counterfeit buried regions 5 on lateral attitude and described active area to be separated by a lateral separation, by the puncture voltage regulating the lateral separation of described counterfeit buried regions 5 and described active area to regulate described Ge-Si heterojunction bipolar transistor.The N-type ion implantation technology condition of described counterfeit buried regions is: implantation dosage 1e14cm
-2~ 1e16cm
-2, Implantation Energy 1KeV ~ 100KeV.
One base 8, be made up of the P type germanium silicon epitaxial layer be formed on described silicon substrate, comprise intrinsic base region 8 and an outer base area 8, described intrinsic base region 8 is formed at top, described active area and is formed with described collector region 4 and contacts, and described outer base area 8 is formed at top, described Chang Yang district 3.The position of described intrinsic base region and size are defined by a base window, described base window is positioned at described active region and the size of described base window is more than or equal to described active area dimensions, the position of described base window and size are defined by base Windows media layer, described base Windows media layer comprises ground floor silica or silicon nitride film 6, second layer polysilicon membrane 7, and described ground floor silica or silicon nitride film 6 are formed on described P-epitaxial loayer 2, second layer polysilicon membrane 7 is formed on described ground floor silica or silicon nitride film 6.Described P type germanium silicon epitaxial layer adopts boron doping, and wherein intrinsic base region is the doping in place of extension, and the boron doped technique in outer base area is ion implantation technology, and process conditions are: implantation dosage is 1e14cm
-2~ 1e16cm
-2, Implantation Energy is 1KeV ~ 50KeV.Being distributed as of germanium is trapezoidal profile or Triangle-Profile.
One emitter region 11, is made up of the N-type polycrystalline silicon being formed at described intrinsic base region 8 top, is formed contact with described intrinsic base region 8.Described position, emitter region 11 and size are defined by an emitter window, described emitter window is positioned at above described intrinsic base region and the size of described emitter window is less than described active area dimensions, the position of described emitter window and size are defined by emitter window dielectric layer, described emitter window dielectric layer comprises third layer silicon oxide film 9, the 4th layer of silicon nitride film 10, and described third layer silicon oxide film 9 is formed in described P type germanium silicon epitaxial layer 8, described 4th layer of silicon nitride film 10 is formed on described third layer silicon oxide film 9.The N-type polycrystalline silicon of described emitter region is adulterated by N-type ion implantation, and the process conditions of described N-type ion implantation are: implantation dosage 1e14cm
-2~ 1e16cm
-2, Implantation Energy 10KeV ~ 200KeV.
Interlayer film 12, covers described P-epitaxial loayer 2 surface outside the described emitter region 22 of Ge-Si heterojunction bipolar transistor, described base 8 and surface, described Chang Yang district 3 and described Ge-Si heterojunction bipolar transistor region.
The Metal Contact 13 of described interlayer film 12 is formed through respectively in described outer base area 8 and top, described emitter region 22, the described Metal Contact 13 being positioned at top, described outer base area 8 contacts with described outer base area 8 and is connected with metal layer at top 16 thus draws base stage, and the described Metal Contact 13 being positioned at top, described emitter region 22 contacts with described emitter region 22 and is connected with metal layer at top 16 thus draws emitter.
Be formed through first deep hole contact 14 in described interlayer film 12 and described Chang Yang district 3 at the top of described counterfeit buried regions 5, described first deep hole contact 14 contacts with described counterfeit buried regions 5 and is connected with metal layer at top 16 thus draws collector electrode.
Outside described Ge-Si heterojunction bipolar transistor region, be formed through the second deep hole contact 15 of described interlayer film 12 and described P-epitaxial loayer 2, described second deep hole contact 15 contacts with described P+ silicon substrate 1.
Wherein, metal layer at top 16 is formed at interlayer film 12 surface.According to technique needs, interlayer film can be multilayer, and metal layer at top also can be multilayer.In the embodiment of the present invention, interlayer film 12 is also formed another interlayer film 12a, is also formed by another metal layer at top 16a on the surface of interlayer film 12a.Counter electrode between different metal layer at top is connected by Metal Contact, as realized connecting by Metal Contact 13a between metal layer at top 16 and 16a.
In the embodiment of the present invention, described emitter to be connected with described second deep hole contact 15 by metal layer at top and to connect described P+ silicon substrate 1 by described second deep hole contact 15, concrete annexation is with reference to shown in figure 1, it is the connection being realized emitter and described second deep hole contact 15 by the metal layer at top 16a of the second layer and corresponding Metal Contact 13a, finally realize the connection of described emitter and described P+ silicon substrate 1, the stray inductance over the ground of described Ge-Si heterojunction bipolar transistor can be reduced like this.
Be preferably, described Metal Contact 13 by after deposit titanium in the contact hole formed in described Metal Contact 13 position and titanium nitride barrier metal layer, insert tungsten again and formed; Described first deep hole contact 14 by after deposit titanium in the first deep hole formed in described first deep hole contact 14 position and titanium nitride barrier metal layer, insert tungsten again and formed; Described second deep hole contact 15 by after deposit titanium in the second deep hole formed in described second deep hole contact 15 position and titanium nitride barrier metal layer, insert tungsten again and formed.
Metal layer on back 17 is formed at the back side of described P+ silicon substrate 1.
As shown in Fig. 2 A to Fig. 2 J, it is the Ge-Si heterojunction bipolar transistor structural representation in each step of embodiment of the present invention manufacture method.The manufacture method of embodiment of the present invention Ge-Si heterojunction bipolar transistor comprises the steps:
Step one, as shown in Figure 2 A, P+ silicon substrate 1 forms P-epitaxial loayer 2, in described P-epitaxial loayer 2, form Chang Yang district groove 3a, and isolate active area by Chang Yang district groove 3a.
Step 2, as shown in Figure 2 B, the photoetching offset plate figure 18 adopting lithographic etch process to be formed defines the position that counterfeit buried regions 5 is positioned at the bottom of described Chang Yang district groove 3a.As shown in Figure 2 C, the N-type ion implantation of carrying out bottom the described Chang Yang district groove 3a of both sides, described active area forms counterfeit buried regions 5.Be preferably, described counterfeit buried regions 5 on lateral attitude and described active area to be separated by a lateral separation, by the puncture voltage regulating the lateral separation of described counterfeit buried regions 5 and described active area to regulate described Ge-Si heterojunction bipolar transistor.The N-type ion implantation technology condition of described counterfeit buried regions 5 is: implantation dosage 1e14cm
-2~ 1e16cm
-2, Implantation Energy 1KeV ~ 100KeV.
Step 3, as shown in Figure 2 C, inserts silica and forms Chang Yang district 3 in described Chang Yang district groove 3a.
Step 4, as shown in Figure 2 D, the photoetching offset plate figure 18 adopting lithographic etch process to be formed defines the regional location of collector region 4.As shown in Figure 2 E, in described active area, carry out N-type ion implantation form collector region 4, described collector region 4 degree of depth be greater than the degree of depth bottom described Chang Yang district 3 and described collector region 4 horizontal expansion enter both sides, described active area Chang Yang district 3 bottom and formed with described counterfeit buried regions 5 and contact.Be preferably, the N-type ion implantation technology condition of described collector region 4 is: implantation dosage 1e12cm
-2~ 5e14cm
-2, Implantation Energy is 50KeV ~ 500KeV.
Step 5, formation base 8.First, as shown in Figure 2 F, base Windows media floor is formed: on the described P-epitaxial loayer 2 being formed with described Chang Yang district 3, form ground floor silica or silicon nitride film 6, on described ground floor silica or silicon nitride film 6, form second layer polysilicon membrane 7.Secondly, form base window: formed by etching the base Windows media layer on top, described active area and described ground floor silica or silicon nitride film 6 and second layer polysilicon membrane 7, the size of described base window is more than or equal to described active area dimensions, and the germanium silicon epitaxial layer that so just can ensure the base that source region grows is all single crystalline layer.As shown in Figure 2 G, carry out P type germanium and silicon epitaxial layer growth, the described P type germanium silicon epitaxial layer being positioned at described base window interior is mono-crystalline structures, and the described P type germanium silicon epitaxial layer being positioned at described base window-external is polycrystalline structure.As illustrated in figure 2h, etch away described P type germanium silicon epitaxial layer and the base Windows media layer of outside, described base 8, form described base 8, being wherein formed at top, described active area is described intrinsic base region, and described intrinsic base region is formed with described collector region 4 and contacts; What be formed at top, described Chang Yang district 3 is described outer base area, and most of described outer base area and described Chang Yang district 3 are separated by and have described base Windows media floor, and described base Windows media layer can reduce the junction capacitance between described outer base area and described collector region.Described P type germanium silicon epitaxial layer adopts boron doping, and wherein intrinsic base region adopts the doping in place of extension, and the boron doped technique in outer base area is ion implantation technology, and process conditions are: implantation dosage is 1e14cm
-2~ 1e16cm
-2, Implantation Energy is 1KeV ~ 50KeV.Being distributed as of germanium is trapezoidal profile or Triangle-Profile.
Step 6, formation emitter region 11.First, as shown in figure 2i, emitter window dielectric layer is formed: in the described P type germanium silicon epitaxial layer of described base 8, form third layer silicon oxide film 9, on third layer silicon oxide film 9, form the 4th layer of silicon nitride film 10; Form emitter window: form described emitter window by etching described emitter window dielectric layer above described intrinsic base region and third layer silicon oxide film 9 and the 4th layer of silicon nitride film 10, the size of described emitter window is less than described active area dimensions, so just can avoid the second-rate impact on intrinsic BE knot of the P type germanium silicon epitaxial layer of active-surface.As shown in fig. 2j, then carry out N-type polycrystalline silicon growth on described intrinsic base region top and the described emitter region 11 of etching formation, described emitter region 11 is formed with described intrinsic base region and contacts.The N-type polycrystalline silicon of described emitter region is adulterated by N-type ion implantation, and the process conditions of described N-type ion implantation are: implantation dosage 1e14cm
-2~ 1e16cm
-2, Implantation Energy 10KeV ~ 200KeV.
Step 7, as shown in Figure 1, form interlayer film 12, described interlayer film 12 covers described P-epitaxial loayer 2 surface outside the described emitter region 22 of Ge-Si heterojunction bipolar transistor, described base 8 and surface, described Chang Yang district 3 and described Ge-Si heterojunction bipolar transistor region.
Step 8, as shown in Figure 1, the Metal Contact 13 through described interlayer film 12 is formed respectively in described outer base area 8 and top, described emitter region 22, the described Metal Contact 13 being positioned at top, described outer base area 8 contacts with described outer base area 8 and for drawing base stage, and the described Metal Contact 13 being positioned at top, described emitter region 22 contacts with described emitter region 22 and for drawing emitter.
Form the first deep hole contact 14 through described interlayer film 12 and described Chang Yang district 3 at the top of described counterfeit buried regions 5, described first deep hole contact 14 contacts with described counterfeit buried regions 5 and for drawing collector electrode.
Outside described Ge-Si heterojunction bipolar transistor region, form the second deep hole contact 15 through described interlayer film 12 and described P-epitaxial loayer 2, described second deep hole contact 15 contacts with described P+ silicon substrate 1.
Be preferably, the step forming described Metal Contact 13 comprises and first forms contact hole in described Metal Contact 13 position, afterwards in described contact hole after deposit titanium and titanium nitride barrier metal layer, insert tungsten again and formed; The step forming described first deep hole contact 14 comprises and first forms the first deep hole in described first deep hole contact 14 position, afterwards in described first deep hole after deposit titanium and titanium nitride barrier metal layer, insert tungsten again and formed; The step forming described second deep hole contact 15 comprises and first forms the second deep hole in described second deep hole contact 15 position, afterwards in described second deep hole after deposit titanium and titanium nitride barrier metal layer, insert tungsten again and formed.
Step 9, as shown in Figure 1, form metal layer at top at described interlayer film 12 top, described metal layer at top is more than one deck.When needs form metal layer at top described in multilayer, then interlayer film also needs multilayer.In the embodiment of the present invention, interlayer film comprises and is two-layerly respectively interlayer film 12 and 12a, and metal layer at top also comprises two-layer, is respectively 16 and 16a, is connected between two metal layer at top 16 and 16a by the Metal Contact 13a through interlayer film 12a.
Described metal layer at top forms described collector electrode, described base stage and described emitter respectively.In the embodiment of the present invention, described emitter to be connected with described second deep hole contact 15 by metal layer at top and to connect described P+ silicon substrate 1 by described second deep hole contact 15, concrete annexation is with reference to shown in figure 1, it is the connection being realized emitter and described second deep hole contact 15 by the metal layer at top 16a of the second layer and corresponding Metal Contact 13a, finally realize the connection of described emitter and described P+ silicon substrate 1, the stray inductance over the ground of described Ge-Si heterojunction bipolar transistor can be reduced like this.
Finally, the back side being also included in described P+ silicon substrate 1 forms the step of metal layer on back 17.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (10)
1. a Ge-Si heterojunction bipolar transistor, is characterized in that, comprising:
P+ silicon substrate, described P+ silicon substrate is formed with P-epitaxial loayer, in described P-epitaxial loayer, isolate active area by Chang Yang district;
One collector region, is made up of the N-type ion implanted region be formed in described active area, and the described collector region degree of depth is greater than the degree of depth bottom described Chang Yang district and the horizontal expansion of described collector region enters bottom the Chang Yang district of both sides, described active area;
One counterfeit buried regions, be made up of the N-type ion implanted region bottom the Chang Yang district being formed at both sides, described active area, the part that the horizontal expansion of described counterfeit buried regions and described collector region enters bottom described Chang Yang district contacts;
One base, is made up of the P type germanium silicon epitaxial layer be formed on described silicon substrate, comprises an intrinsic base region and an outer base area, and described intrinsic base region is formed at top, described active area and is formed with described collector region and contacts, and described outer base area is formed at top, described Chang Yang district;
One emitter region, is made up of the N-type polycrystalline silicon being formed at described intrinsic base region top, is formed contact with described intrinsic base region;
Interlayer film, covers the described P-epi-layer surface outside the described emitter region of Ge-Si heterojunction bipolar transistor, described base and surface, described Chang Yang district and described Ge-Si heterojunction bipolar transistor region;
The Metal Contact of described interlayer film is formed through respectively in described outer base area and top, described emitter region, the described Metal Contact being positioned at top, described outer base area contacts with described outer base area and for drawing base stage, and the described Metal Contact being positioned at top, described emitter region contacts with described emitter region and for drawing emitter;
Be formed through first deep hole contact in described interlayer film and described Chang Yang district at the top of described counterfeit buried regions, described first deep hole contact contacts with described counterfeit buried regions and for drawing collector electrode;
Outside described Ge-Si heterojunction bipolar transistor region, be formed through the second deep hole contact of described interlayer film and described P-epitaxial loayer, described second deep hole contact contacts with described P+ silicon substrate; Described emitter to be connected with described second deep hole contact by metal layer at top and to connect described P+ silicon substrate by described second deep hole contact, can reduce the stray inductance over the ground of described Ge-Si heterojunction bipolar transistor.
2. Ge-Si heterojunction bipolar transistor as claimed in claim 1, is characterized in that: described Metal Contact by after deposit titanium in the contact hole formed in described Metal Contact position and titanium nitride barrier metal layer, insert tungsten again and formed; Described first deep hole contact by after deposit titanium in the first deep hole formed in described first deep hole contact position and titanium nitride barrier metal layer, insert tungsten again and formed; Described second deep hole contact by after deposit titanium in the second deep hole formed in described second deep hole contact position and titanium nitride barrier metal layer, insert tungsten again and formed.
3. Ge-Si heterojunction bipolar transistor as claimed in claim 1, it is characterized in that: described counterfeit buried regions on lateral attitude and described active area to be separated by a lateral separation, by the puncture voltage regulating the lateral separation of described counterfeit buried regions and described active area to regulate described Ge-Si heterojunction bipolar transistor.
4. a manufacture method for Ge-Si heterojunction bipolar transistor, is characterized in that, comprises the steps:
Step one, on P+ silicon substrate, form P-epitaxial loayer, in described P-epitaxial loayer, form Chang Yang district groove, and go out active area by Chang Yang district trench isolations;
Step 2, form counterfeit buried regions in the N-type ion implantation of carrying out of the described Chang Yang district channel bottom of both sides, described active area;
Step 3, insert in described Chang Yang district groove silica formed Chang Yang district;
Step 4, in described active area, carry out N-type ion implantation form collector region, the described collector region degree of depth be greater than the degree of depth bottom described Chang Yang district and the horizontal expansion of described collector region enter both sides, described active area Chang Yang district bottom and formed with described counterfeit buried regions and contact;
Step 5, carry out on described silicon substrate P type germanium and silicon epitaxial layer growth formed base, described base comprises an intrinsic base region and an outer base area, described intrinsic base region is formed at top, described active area and is formed with described collector region and contacts, and described outer base area is formed at top, described Chang Yang district;
Step 6, to carry out N-type polycrystalline silicon growth form emitter region on described intrinsic base region top, described emitter region is formed with described intrinsic base region and contacts;
Step 7, formation interlayer film, described interlayer film covers the described P-epi-layer surface outside the described emitter region of Ge-Si heterojunction bipolar transistor, described base and surface, described Chang Yang district and described Ge-Si heterojunction bipolar transistor region;
Step 8, form the Metal Contact through described interlayer film respectively in described outer base area and top, described emitter region, the described Metal Contact being positioned at top, described outer base area contacts with described outer base area and for drawing base stage, and the described Metal Contact being positioned at top, described emitter region contacts with described emitter region and for drawing emitter;
Form the first deep hole contact through described interlayer film and described Chang Yang district at the top of described counterfeit buried regions, described first deep hole contact contacts with described counterfeit buried regions and for drawing collector electrode;
Outside described Ge-Si heterojunction bipolar transistor region, form the second deep hole contact through described interlayer film and described P-epitaxial loayer, described second deep hole contact contacts with described P+ silicon substrate;
Step 9, form metal layer at top at described interlayer film top, described metal layer at top is more than one deck, described metal layer at top forms described collector electrode, described base stage and described emitter respectively, described emitter to be connected with described second deep hole contact by metal layer at top and to connect described P+ silicon substrate by described second deep hole contact, can reduce the stray inductance over the ground of described Ge-Si heterojunction bipolar transistor.
5. method as claimed in claim 4, is characterized in that: the N-type ion implantation technology condition of counterfeit buried regions described in step 2 is: implantation dosage 1e14cm
-2~ 1e16cm
-2, Implantation Energy 1KeV ~ 100KeV.
6. method as claimed in claim 4, is characterized in that: the N-type ion implantation technology condition of collector region described in step 4 is: implantation dosage 1e12cm
-2~ 5e14cm
-2, Implantation Energy is 50KeV ~ 500KeV.
7. method as claimed in claim 4, is characterized in that: the type of P described in step 5 germanium silicon epitaxial layer adopts boron doping, and wherein the boron of intrinsic base region is doped to the doping in place of outer time delay; And the boron doped technique of outer base area is ion implantation technology, process conditions are: implantation dosage is 1e14cm
-2~ 1e16cm
-2, Implantation Energy is 1KeV ~ 50KeV; Being distributed as of germanium is trapezoidal profile or Triangle-Profile.
8. method as claimed in claim 4, it is characterized in that: the N-type polycrystalline silicon of emitter region described in step 6 is adulterated by N-type ion implantation, the process conditions of described N-type ion implantation are: implantation dosage 1e14cm
-2~ 1e16cm
-2, Implantation Energy 10KeV ~ 200KeV.
9. method as claimed in claim 4, it is characterized in that: the step of the described Metal Contact of the formation in step 8 comprises and first forms contact hole in described Metal Contact position, afterwards in described contact hole after deposit titanium and titanium nitride barrier metal layer, insert tungsten again and formed; The step forming described first deep hole contact comprises and first forms the first deep hole in described first deep hole contact position, afterwards in described first deep hole after deposit titanium and titanium nitride barrier metal layer, insert tungsten again and formed; The step forming described second deep hole contact comprises and first forms the second deep hole in described second deep hole contact position, afterwards in described second deep hole after deposit titanium and titanium nitride barrier metal layer, insert tungsten again and formed.
10. method as claimed in claim 4, it is characterized in that: counterfeit buried regions described in step 2 on lateral attitude and described active area to be separated by a lateral separation, by the puncture voltage regulating the lateral separation of described counterfeit buried regions and described active area to regulate described Ge-Si heterojunction bipolar transistor.
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