CN104576434A - Method for testing through holes in silicon - Google Patents
Method for testing through holes in silicon Download PDFInfo
- Publication number
- CN104576434A CN104576434A CN201510054277.7A CN201510054277A CN104576434A CN 104576434 A CN104576434 A CN 104576434A CN 201510054277 A CN201510054277 A CN 201510054277A CN 104576434 A CN104576434 A CN 104576434A
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- silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Measuring Leads Or Probes (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention discloses a method for testing through holes in silicon. By the aid of the method, problems of complicated technologies and high cost of procedures for testing through holes in silicon due to the fact that the tops and the bottoms of the through holes in the silicon need to be subjected to simultaneous load test connection when directly chemically tested but mainstream test equipment does not support simultaneous load test connection on the front surfaces and the back surfaces of silicon wafers can be solved. A conductive film clings to the back surface of each silicon wafer after the through holes in the silicon are formed in the silicon wafer and miniature bumps are manufactured on the silicon wafer, then bonding pads which are exposed out of the front surfaces of the silicon wafers are tested by the aid of probes, and the method includes modes of on and off tests, resistance tests and the like, and electric parameters of the through holes in the silicon can be tested by the aid of the method. The method has the obvious advantages of simplicity in operation and low cost.
Description
Technical field
The present invention relates to a kind of method manufacturing or process semiconductor or solid state device of microelectronics technology, particularly relate to a kind of method of permanent wafer bonding interconnection.
Background technology
Silicon perforation (Through Silicon Via, being called for short TSV) technique is by forming metal upright post in wafer, and be equipped with metal salient point, can to realize between wafer (chip) or direct three-dimensional interconnection between chip and substrate, the limitation of conventional semiconductor chip two dimension wiring can be made up like this.This interconnection mode and traditional Stack Technology as have compared with bonding techniques the stacking density of three-dimensional large, encapsulate the advantages such as overall dimension is afterwards little, thus greatly improve the speed of chip and reduce power consumption.TSV normally at chip and chip, make vertical conducting hole by modes such as etching, laser drill between wafer and wafer, then realizes the technology of interconnection in via by mode depositing electrically conductive materials such as plating.The technology of preparing of silicon through hole achieves in recent years and develops fast, but the electrical testing of silicon through hole is good solution never, because silicon through hole runs through wafer upper and lower surface, realize the connection with other chip or encapsulation at its top and bottom by pad or micro convex point, need when silicon through hole is directly tested that test is loaded to its top and bottom simultaneously and be connected.Traditional electrical testing method and equipment are all test based on to the single-contact of chip or encapsulation, such as, the electrical testing of wafer is fixed on microscope carrier by wafer, tested by the pad of probes touch crystal column surface, and the back side of wafer need not load test and connect.The testing equipment of present main flow does not support that load test to the surface of wafer with the back side is connected simultaneously yet.Flying probe tester for PCB can load test to PCB surface and the back side simultaneously be connected, but and be not suitable for the test of wafer, the wafer after especially thinning, it holds and supports a difficult problem especially.In order to test silicon through hole, industrial quarters designs a lot of ways, such as, design extra silicon through hole test circuit in the chips, but, which adds chip design cost and chip area; Also the encapsulation flow process had has given up the test link of silicon through hole, silicon through hole and other chip or encapsulation complete weld after carry out integrated testability again, which adds and to cause due to silicon through hole fault and the chip of its welding or the risk of scrapping together with encapsulating.
Summary of the invention
In order to solve the electrical testing problem of silicon through hole, the present invention proposes a kind of silicon through hole method of testing, and technical scheme is as follows:
A kind of silicon through hole method of testing, comprises the following steps:
A, provide a wafer completing silicon through hole preparation technology, in silicon through hole, fill metal;
B, complete thinning back side to above-mentioned wafer, silicon through hole inner wire is appeared;
C, to fit one deck conducting film at above-mentioned wafer rear;
D, the pad exposed by above-mentioned device wafers front are tested silicon through hole.
Further, before wafer rear laminating conducting film, first the front of device wafers is bonded and fixed on a slide glass by ephemeral key rubber alloy.
As preferably, after silicon through hole inner wire is appeared, also carry out the preparation of micro convex point on its end.
If preparation micro convex point, then conducting film thickness is greater than above-mentioned micro convex point, covers above-mentioned micro convex point completely after laminating.
Except micro convex point, interconnection process can also be the steps such as the making of projection or projection and redistributing layer (RDL layer).
After the laminating completing conducting film, just can adopt the mode of probe and contact pads, silicon through hole be tested, comprises on off test, resistance test etc.
Compared with prior art, beneficial effect of the present invention is, the present invention is after, back side bump process thinning at wafer, use the nonconducting blue film in whole conducting film subsides replacement common process or UV film, be fitted in wafer rear, make the mutual conducting of all salient points of wafer rear, only need when like this electrical parameter of silicon through hole being tested that test is carried out to the pad of crystal column surface and connect, just can test the electrical parameter of silicon through hole with the crystal round test approach of routine.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, specific embodiment of the invention is described further.
Fig. 1 has been device wafers schematic diagram prepared by silicon through hole;
Fig. 2 is the schematic diagram of conducting film fit-state;
Fig. 3 is the schematic diagram after removing slide glass and ephemeral key rubber alloy;
Fig. 4 is the schematic diagram tested pad with probe under conducting film fit-state.
Embodiment
Now for the silicon via-hole applications in typical three-dimension packaging, the method for testing of silicon through hole in the present invention is described.Fig. 1 has completed schematic diagram prepared by silicon through hole, and actual conditions are complete wafers, wherein can comprise thousands of silicon through holes, can also comprise the unit such as insulating barrier and other circuit.For simplicity, illustrate only the cross section of the silicon through hole comprising two in schematic diagram, insulating barrier is tested incoherent unit with other and silicon through hole and is not marked.4 is wafers, and its inside has prepared the silicon through hole 5 that two are filled up metal, and the preparation of silicon via top has pad 3, and bottom preparation has micro convex point 6.3,4,5,6 is an inseparable entirety, by pad 3, silicon through hole 5, micro convex point 6, achieves the conducting at wafer frontside and the back side.Wafer 4 being bonded and fixed on slide glass 1 by ephemeral key rubber alloy 2, because usually wafer 4 must be fixed on and slide glass 1 just can carry out thinning and be prepared the technique of micro convex point.
After shown in Fig. 1 prepared by assembly, fit by the micro convex point 6 of conducting film 7 with wafer 4 lower surface, as shown in Figure 2.Adopt nonconducting blue film or UV film laminating wafer in conventional wafer technique.Except using the blue film or UV film that use in conducting film replacement common process, other difference any in this method.
After having pasted conducting film, stripping of being removed photoresist from slide glass by wafer, removes ephemeral key rubber alloy 2, and as shown in Figure 3, this processing step is identical with common process.
As shown in Figure 4, the wafer with conducting film is tested.Because conducting film is by the micro convex point conducting of wafer bottom surface, be equivalent to two silicon through holes and be connected in series, probe 8 need connect the pad of wafer upper surface, just can test the silicon through hole of two series connection, comprise on off test, resistance test etc.
For those of ordinary skills, obviously the invention is not restricted to the details of above-mentioned one exemplary embodiment, when not deviating from spirit of the present invention or essential characteristic, also can realize the present invention in other specific forms.Therefore, all should above-described embodiment be regarded as exemplary, and be nonrestrictive.
Claims (6)
1. a silicon through hole method of testing, is characterized in that comprising the following steps:
A wafer completing silicon through hole preparation technology is provided;
Complete thinning back side to above-mentioned wafer, silicon through hole inner wire is appeared;
To fit one deck conducting film at above-mentioned wafer rear;
The pad exposed by above-mentioned wafer frontside is tested silicon through hole.
2. silicon through hole method of testing according to claim 1, is characterized in that, before wafer rear laminating conducting film, being first bonded and fixed on a slide glass by ephemeral key rubber alloy in device wafers front.
3. silicon through hole method of testing according to claim 1, after it is characterized in that described silicon through hole inner wire is appeared, carries out the preparation of micro convex point on its end.
4. silicon through hole method of testing according to claim 3, is characterized in that conducting film thickness is greater than above-mentioned micro convex point, covers above-mentioned micro convex point completely after laminating.
5. silicon through hole method of testing according to claim 1, is characterized in that described interconnection process also comprises the making step of projection or projection and redistributing layer.
6. any one silicon through hole method of testing according to Claims 1-4, is characterized in that in Step d, adopts the mode of probe and contact pads, tests silicon through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510054277.7A CN104576434A (en) | 2015-02-02 | 2015-02-02 | Method for testing through holes in silicon |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510054277.7A CN104576434A (en) | 2015-02-02 | 2015-02-02 | Method for testing through holes in silicon |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104576434A true CN104576434A (en) | 2015-04-29 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510054277.7A Pending CN104576434A (en) | 2015-02-02 | 2015-02-02 | Method for testing through holes in silicon |
Country Status (1)
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| CN (1) | CN104576434A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109581173A (en) * | 2018-11-30 | 2019-04-05 | 华进半导体封装先导技术研发中心有限公司 | A kind of TSV switching board test device and method based on micro-nano mitron array |
| CN109950341A (en) * | 2019-03-28 | 2019-06-28 | 苏州协鑫纳米科技有限公司 | The method that Thinfilm solar cell assembly and detection Thinfilm solar cell assembly P2 carve disconnected situation |
| CN112509937A (en) * | 2020-11-30 | 2021-03-16 | 西安微电子技术研究所 | Electric on-off test method for double-sided substrate |
| CN116718891A (en) * | 2023-06-06 | 2023-09-08 | 无锡芯光互连技术研究院有限公司 | Test method of adapter plate and structure for testing adapter plate |
| CN117393447A (en) * | 2023-09-12 | 2024-01-12 | 中国科学院上海微***与信息技术研究所 | Vertical interconnection wafer testing method based on temporary short circuit |
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| US20100013512A1 (en) * | 2008-07-15 | 2010-01-21 | Micron Technology, Inc. | Apparatus and methods for through substrate via test |
| US7904273B2 (en) * | 2009-02-16 | 2011-03-08 | International Business Machines Corporation | In-line depth measurement for thru silicon via |
| CN102074544A (en) * | 2009-10-22 | 2011-05-25 | 台湾积体电路制造股份有限公司 | Through-silicon via structure and a process for forming the same |
| CN103165577A (en) * | 2011-12-08 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor detection structure and detection method |
| CN103187399A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Through-silicon via (TSV) testing structure and TSV testing method |
| US20140014959A1 (en) * | 2011-12-07 | 2014-01-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Passivation layer for packaged chip |
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2015
- 2015-02-02 CN CN201510054277.7A patent/CN104576434A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20100013512A1 (en) * | 2008-07-15 | 2010-01-21 | Micron Technology, Inc. | Apparatus and methods for through substrate via test |
| US7904273B2 (en) * | 2009-02-16 | 2011-03-08 | International Business Machines Corporation | In-line depth measurement for thru silicon via |
| CN102074544A (en) * | 2009-10-22 | 2011-05-25 | 台湾积体电路制造股份有限公司 | Through-silicon via structure and a process for forming the same |
| US20140014959A1 (en) * | 2011-12-07 | 2014-01-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Passivation layer for packaged chip |
| CN103165577A (en) * | 2011-12-08 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor detection structure and detection method |
| CN103187399A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Through-silicon via (TSV) testing structure and TSV testing method |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109581173A (en) * | 2018-11-30 | 2019-04-05 | 华进半导体封装先导技术研发中心有限公司 | A kind of TSV switching board test device and method based on micro-nano mitron array |
| CN109950341A (en) * | 2019-03-28 | 2019-06-28 | 苏州协鑫纳米科技有限公司 | The method that Thinfilm solar cell assembly and detection Thinfilm solar cell assembly P2 carve disconnected situation |
| CN112509937A (en) * | 2020-11-30 | 2021-03-16 | 西安微电子技术研究所 | Electric on-off test method for double-sided substrate |
| CN112509937B (en) * | 2020-11-30 | 2023-06-30 | 珠海天成先进半导体科技有限公司 | Electric on-off test method for double-sided substrate |
| CN116718891A (en) * | 2023-06-06 | 2023-09-08 | 无锡芯光互连技术研究院有限公司 | Test method of adapter plate and structure for testing adapter plate |
| CN117393447A (en) * | 2023-09-12 | 2024-01-12 | 中国科学院上海微***与信息技术研究所 | Vertical interconnection wafer testing method based on temporary short circuit |
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Application publication date: 20150429 |
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