CN104576410A - Substrate transferring method for power semiconductor device with perpendicular structure - Google Patents
Substrate transferring method for power semiconductor device with perpendicular structure Download PDFInfo
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- CN104576410A CN104576410A CN201410784887.8A CN201410784887A CN104576410A CN 104576410 A CN104576410 A CN 104576410A CN 201410784887 A CN201410784887 A CN 201410784887A CN 104576410 A CN104576410 A CN 104576410A
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- power semiconductor
- substrate
- solder
- metal electrode
- bonding
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- 239000000758 substrate Substances 0.000 title claims abstract description 79
- 238000000034 method Methods 0.000 title claims abstract description 54
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 229910052594 sapphire Inorganic materials 0.000 claims abstract description 34
- 239000010980 sapphire Substances 0.000 claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 claims abstract description 31
- 239000002184 metal Substances 0.000 claims abstract description 31
- 229910000679 solder Inorganic materials 0.000 claims description 45
- 238000013517 stratification Methods 0.000 claims description 13
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 229910002601 GaN Inorganic materials 0.000 claims description 5
- 229910017083 AlN Inorganic materials 0.000 claims description 3
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical group [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 7
- 230000004907 flux Effects 0.000 abstract 5
- 238000003466 welding Methods 0.000 abstract 5
- 238000010586 diagram Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 229910015365 Au—Si Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Photovoltaic Devices (AREA)
Abstract
The invention discloses a substrate transferring method for a power semiconductor device with perpendicular structure. The power semiconductor device arranged on a sapphire substrate is transferred to a target substrate and comprises extension layers growing on the sapphire substrate and a plurality of metal electrode blocks plated on the upper surfaces of the extension layers. The substrate transferring method mainly comprises the following steps: 1, placing a welding flux, namely, placing the welding flux on the surface of the power semiconductor device; 2, bonding a wafer, namely, bonding the upper surface of the power semiconductor device to the target substrate through the welding flux by a wafer bonding technology; 3, peeling the sapphire substrate, namely, peeling the sapphire substrate from the power semiconductor device by a laser peeling technology to finish the transferring of the power semiconductor device. The method is simple to operate and can effectively prevent device short-circuiting and failure conditions due to the simultaneous contact of the welding flux with the metal electrode blocks and the extension layers of the device which is caused by excessive welding flux placed when the device is bonded with the target substrate.
Description
Technical field
the present invention relates to a kind of substrate transfer method of vertical stratification power semiconductor, belong to semiconductor process techniques field.
Background technology
at present, sapphire, silicon, carborundum is generally adopted to carry out grown epitaxial layer as substrate in semiconductor technology.On a sapphire substrate, Sapphire Substrate has many advantages to the epitaxial loayer primary growth of general GaN base materials and devices: 1, the production technology of Sapphire Substrate is ripe, device quality is better; 2, sapphire good stability, can be used in higher temperature growth processes; 3, sapphire mechanical strength is high, is easy to process and cleaning.Therefore, most of technique is general all using sapphire as substrate, but Sapphire Substrate also has following defect: sapphire is a kind of insulator, resistivity under normal temperature is greater than 1011 Ω cm, the device of vertical stratification cannot be made in this case, usually only make N-shaped and p-type electrode at epitaxial loayer upper surface.Two electrodes are made at upper surface, cause efficient lighting area to reduce, add the photoetching in device manufacture and etching process simultaneously, result makes stock utilization reduction, cost increases, simultaneously, sapphire hardness is very high, and in nature material, its hardness is only second to diamond, but but needs to carry out thinning and cutting (reducing to about 100nm from 400nm) to it in the manufacturing process of LED component.Has added thinning and equipment that is cutting technique and increased a larger investment again, and sapphire heat conductivility is not very well (being about 25W/(mK at 100 DEG C)), when using power semiconductor, can conduct a large amount of heats; Particularly larger to area large power semiconductor device, heat conductivility is a very important Consideration.In order to overcome above difficulty, a lot of people attempts by GaN photoelectric device direct growth on a silicon substrate, thus improves heat conduction and electric conductivity.
and silicon is the good conductor of heat, so the heat conductivility of the device prepared on a silicon substrate can obviously improve, thus extend the life-span of device.And the conduction of the device adopting silicon carbide substrates to make and heat conductivility are all very good, be conducive to making the larger large power semiconductor device of area.But for Sapphire Substrate, the cost that carborundum manufactures is higher.
therefore; in order to guarantee conductivity and the heat conductivility of the device made while reducing cost; at present; people use substrate transfer technology to solve contradiction between cost and quality usually; and in substrate-transfer process, wafer bond techniques usually can be used to have together with the substrate of epitaxial loayer (or completing technique on epitaxial loayer) is bonded to target substrate by solder by long, then remove former substrate by laser lift-off technique.And usually can there is following problem in operation, shown in Figure 1, in bonding process, solder all contacts with metal electrode and epitaxial loayer and causes short circuit, component failure.And at present, researcher not good solution solves this problem.
Summary of the invention
the object of this invention is to provide a kind of substrate transfer method of vertical stratification power semiconductor, can guarantee that device can not lose efficacy in transfer process by the method, its method is simple, be easy to operation, save the energy simultaneously.
for achieving the above object, the technical solution used in the present invention is a kind of substrate transfer method of vertical stratification power semiconductor, the power semiconductor arranged on a sapphire substrate is transferred in target substrate, described power semiconductor comprises the epitaxial loayer grown in described Sapphire Substrate and the multiple metal electrode blocks arranged separately being plated on described epitaxial loayer upper surface, and described substrate transfer method mainly comprises the steps:
1) solder is placed: place solder at the upper surface of the described metal electrode block of described power semiconductor, described solder projected area is in the horizontal plane less than described metal electrode block projected area in the horizontal plane;
2) wafer bonding: target substrate be placed on the upper end of described power semiconductor and contact with described solder, adopt wafer scale bonding techniques, by described solder by the described metal electrode block of described power semiconductor and described target substrate phase bonding;
3) Sapphire Substrate is peeled off: adopt laser lift-off technique to be peeled off from described Sapphire Substrate by described power semiconductor, to complete the transfer of described power semiconductor substrate.
preferably, described solder is tin solder, and described tin solder is spherical in shape or block.
preferably, described target substrate material is silicon, carborundum or polycrystal carborundum.
preferably, described metal electrode block upper surface is also provided with the anti-overflow frame for preventing described solder from overflowing, and described solder is positioned at described anti-overflow frame.
further preferably, the height of the described solder after step (2) is not more than 10um, and area is not more than 40um
2
and be no more than 95% of described metal electrode block area.
further preferably, the method that have employed Jin-Xi bonding in step (2) carries out bonding.
further preferably, the material of described epitaxial loayer is gallium nitride, aluminium nitride, carborundum or GaAs.
due to the utilization of technique scheme, instant invention overcomes in prior art substrate-transfer process, adopt solder solder technology by device epitaxial layers and target substrate bonding, solder is caused solder to contact with metal electrode and epitaxial loayer by compression in bonding process simultaneously, thus be short-circuited, component failure, the present invention compared with prior art has following advantages: the method that the present invention adopts is simple, easy to implement, and the consumption of solder is few, ensure that the validity of the device made on substrate, save the energy simultaneously.
Accompanying drawing explanation
accompanying drawing 1 is the substrate-transfer schematic diagram of power semiconductor in prior art;
accompanying drawing 2 is Sapphire Substrate schematic diagrames;
accompanying drawing 3 is schematic diagrames of Grown on Sapphire Substrates epitaxial loayer;
accompanying drawing 4 is schematic diagrames Sapphire Substrate upper epitaxial layer being carried out to etch processes;
accompanying drawing 5 is schematic diagrames of metal lining electrode block;
accompanying drawing 6 is the schematic diagrames placing solder;
accompanying drawing 7 is the schematic diagrames before power semiconductor and target substrate bonding;
accompanying drawing 8 is the schematic diagrames after power semiconductor and target substrate bonding;
accompanying drawing 9 is the schematic diagrames peeling off Sapphire Substrate;
wherein: 1, Sapphire Substrate; 2, epitaxial loayer; 3, metal electrode block; 4, solder; 5, target substrate; 6, anti-overflow frame.
Embodiment
below in conjunction with accompanying drawing, technical scheme of the present invention is further elaborated.
shown in Fig. 2-9, a kind of substrate transfer method of vertical stratification power semiconductor, the power semiconductor be arranged in Sapphire Substrate 1 to be transferred in target substrate 5, this power semiconductor comprises the epitaxial loayer 2 grown in Sapphire Substrate 1 and several the metal electrode blocks 3 arranged separately being plated on epitaxial loayer 2 upper surface, and this substrate transfer method mainly comprises the steps:
1) solder 4 is placed: on the upper surface of the metal electrode block of power semiconductor, place the solder 4 as bonding material, solder 4 projected area is in the horizontal plane less than metal electrode block 3 projected area in the horizontal plane;
2) wafer bonding: target substrate 5 be placed on the upper end of power semiconductor and contact with solder 4, adopts wafer scale bonding techniques, by solder by the metal electrode block of power semiconductor and target substrate 5 phase bonding;
3) Sapphire Substrate is peeled off: adopt laser lift-off technique the described Sapphire Substrate 1 of described power semiconductor lower surface to be peeled off, to complete the transfer of described power semiconductor substrate.
in the present embodiment, power semiconductor mainly adopts following methods to be made: 1) first in Sapphire Substrate 1, grow one deck epitaxial loayer 2; 2) method of dry etching is adopted to carry out partially-etched process to the surface of epitaxial loayer 2, to form the epitaxial loayer 2 with male and fomale(M&F), on epitaxial loayer 2, then adopt the method plating layer of metal electrode of evaporation or sputtering, and the metal electrode in epitaxial loayer 2 concave surface is removed, make the metal electrode stayed on convex surface form several metal electrode blocks 3, thus complete the making of device.Here, the material of epitaxial loayer can be gallium nitride, aluminium nitride, carborundum or GaAs.
in the present embodiment, described solder 4 is tin solder, described tin solder is spherical in shape or block, in step 2) method of Jin-Xi bonding can be adopted the metal electrode block of device and target substrate 5 phase bonding, certainly silicon can also be adopted as solder, then in step 2) in the method for Au-Si bonding can be adopted the metal electrode block of device and target substrate 5 phase bonding, here, described target substrate 5 material can be silicon, carborundum or polycrystal carborundum.
overflow in bonding process to prevent solder 4, cause solder 4 to contact with metal electrode block 3 and epitaxial loayer 2 simultaneously, cause shorted devices, losing efficacy, in the present embodiment, being also provided with for preventing solder 4 by the anti-overflow frame 6 overflowed during compression at metal electrode block 3 upper surface, this solder 4 is placed in anti-overflow frame 6, meanwhile, after step (2), the height of solder 4 is not more than 10um, and area is not more than 40um
2
and be no more than 95% of metal electrode block 3 area.
above-described embodiment is only for illustrating technical conceive of the present invention and feature; its object is to person skilled in the art can be understood content of the present invention and be implemented; can not limit the scope of the invention with this; all equivalences done according to Spirit Essence of the present invention change or modify, and all should be encompassed in protection scope of the present invention.
Claims (7)
1. the substrate transfer method of a vertical stratification power semiconductor, the power semiconductor arranged on a sapphire substrate is transferred in target substrate, described power semiconductor comprises the epitaxial loayer grown in described Sapphire Substrate and the multiple metal electrode blocks arranged separately being plated on described epitaxial loayer upper surface, it is characterized in that, described substrate transfer method mainly comprises the steps:
1) solder is placed: place solder at the upper surface of the described metal electrode block of described power semiconductor, described solder projected area is in the horizontal plane less than described metal electrode block projected area in the horizontal plane;
2) wafer bonding: target substrate be placed on the upper end of described power semiconductor and contact with described solder, adopt wafer scale bonding techniques, by described solder by the described metal electrode block of described power semiconductor and described target substrate phase bonding;
3) Sapphire Substrate is peeled off: adopt laser lift-off technique to be peeled off from described Sapphire Substrate by described power semiconductor, to complete the transfer of described power semiconductor substrate.
2. the substrate transfer method of vertical stratification power semiconductor according to claim 1, is characterized in that: described solder is tin solder, and described tin solder is spherical in shape or block.
3. the substrate transfer method of vertical stratification power semiconductor according to claim 1, is characterized in that: described target substrate material is silicon, carborundum or polycrystal carborundum.
4. the substrate transfer method of vertical stratification power semiconductor according to claim 1, is characterized in that: described metal electrode block upper surface is also provided with the anti-overflow frame for preventing described solder from overflowing, and described solder is positioned at described anti-overflow frame.
5. the substrate transfer method of vertical stratification power semiconductor according to claim 1, is characterized in that: the height of the described solder after step (2) is not more than 10um, and area is not more than 40um
2and be no more than 95% of described metal electrode block area.
6. the substrate transfer method of vertical stratification power semiconductor according to claim 2, is characterized in that: the method that have employed Jin-Xi bonding in step (2) carries out bonding.
7., according to the substrate transfer method of the arbitrary described vertical stratification power semiconductor of claim 1 to 6, it is characterized in that: the material of described epitaxial loayer is gallium nitride, aluminium nitride, carborundum or GaAs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410784887.8A CN104576410A (en) | 2014-12-17 | 2014-12-17 | Substrate transferring method for power semiconductor device with perpendicular structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410784887.8A CN104576410A (en) | 2014-12-17 | 2014-12-17 | Substrate transferring method for power semiconductor device with perpendicular structure |
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| CN104576410A true CN104576410A (en) | 2015-04-29 |
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| CN201410784887.8A Pending CN104576410A (en) | 2014-12-17 | 2014-12-17 | Substrate transferring method for power semiconductor device with perpendicular structure |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105762088A (en) * | 2016-04-13 | 2016-07-13 | 中国科学院微电子研究所 | Method for preventing metal eutectic bonding alloy from overflowing and device |
| CN106586946A (en) * | 2015-10-15 | 2017-04-26 | 中芯国际集成电路制造(上海)有限公司 | MEMS (microelectromechanical system) device, preparation method thereof and electronic device |
| CN107226453A (en) * | 2016-03-24 | 2017-10-03 | 中芯国际集成电路制造(上海)有限公司 | A kind of MEMS and preparation method thereof, electronic installation |
| CN107416758A (en) * | 2016-05-24 | 2017-12-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of MEMS and preparation method, electronic installation |
| CN107777655A (en) * | 2016-08-25 | 2018-03-09 | 中芯国际集成电路制造(上海)有限公司 | A kind of MEMS and preparation method thereof and electronic installation |
| CN108100986A (en) * | 2016-11-24 | 2018-06-01 | 上海新微技术研发中心有限公司 | Eutectic bonding method and semiconductor device |
| CN109712898A (en) * | 2018-12-10 | 2019-05-03 | 通富微电子股份有限公司 | A kind of packaging method and packaging |
| CN110116984A (en) * | 2018-02-06 | 2019-08-13 | 中芯国际集成电路制造(上海)有限公司 | MEMS device and preparation method thereof |
| CN112872538A (en) * | 2021-01-08 | 2021-06-01 | 晶澳（邢台）太阳能有限公司 | Tin supplementing device and method for junction box |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101479839A (en) * | 2006-04-24 | 2009-07-08 | 株式会社村田制作所 | Electronic element, electronic element device using the same, and manufacturing method thereof |
| CN101771116A (en) * | 2009-12-31 | 2010-07-07 | 杭州士兰明芯科技有限公司 | Manufacturing method of light emitting diode with vertical structure |
| CN102569537A (en) * | 2010-12-10 | 2012-07-11 | 上海蓝光科技有限公司 | Method for manufacturing light emitting diode chip with vertical structure |
| CN202712261U (en) * | 2012-05-31 | 2013-01-30 | 杭州士兰明芯科技有限公司 | White light LED chip |
| CN102931313A (en) * | 2012-08-30 | 2013-02-13 | 厦门市三安光电科技有限公司 | Inverted light emitting diode and manufacture method thereof |
-
2014
- 2014-12-17 CN CN201410784887.8A patent/CN104576410A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101479839A (en) * | 2006-04-24 | 2009-07-08 | 株式会社村田制作所 | Electronic element, electronic element device using the same, and manufacturing method thereof |
| CN101771116A (en) * | 2009-12-31 | 2010-07-07 | 杭州士兰明芯科技有限公司 | Manufacturing method of light emitting diode with vertical structure |
| CN102569537A (en) * | 2010-12-10 | 2012-07-11 | 上海蓝光科技有限公司 | Method for manufacturing light emitting diode chip with vertical structure |
| CN202712261U (en) * | 2012-05-31 | 2013-01-30 | 杭州士兰明芯科技有限公司 | White light LED chip |
| CN102931313A (en) * | 2012-08-30 | 2013-02-13 | 厦门市三安光电科技有限公司 | Inverted light emitting diode and manufacture method thereof |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106586946A (en) * | 2015-10-15 | 2017-04-26 | 中芯国际集成电路制造(上海)有限公司 | MEMS (microelectromechanical system) device, preparation method thereof and electronic device |
| CN107226453A (en) * | 2016-03-24 | 2017-10-03 | 中芯国际集成电路制造(上海)有限公司 | A kind of MEMS and preparation method thereof, electronic installation |
| CN107226453B (en) * | 2016-03-24 | 2021-08-13 | 中芯国际集成电路制造(上海)有限公司 | MEMS device, preparation method thereof and electronic device |
| CN105762088B (en) * | 2016-04-13 | 2018-07-31 | 中国科学院微电子研究所 | Method for preventing metal eutectic bonding alloy from overflowing and device |
| CN105762088A (en) * | 2016-04-13 | 2016-07-13 | 中国科学院微电子研究所 | Method for preventing metal eutectic bonding alloy from overflowing and device |
| CN107416758A (en) * | 2016-05-24 | 2017-12-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of MEMS and preparation method, electronic installation |
| CN107777655A (en) * | 2016-08-25 | 2018-03-09 | 中芯国际集成电路制造(上海)有限公司 | A kind of MEMS and preparation method thereof and electronic installation |
| CN108100986A (en) * | 2016-11-24 | 2018-06-01 | 上海新微技术研发中心有限公司 | Eutectic bonding method and semiconductor device |
| CN108100986B (en) * | 2016-11-24 | 2020-01-31 | 上海新微技术研发中心有限公司 | eutectic bonding method and semiconductor device |
| CN110116984A (en) * | 2018-02-06 | 2019-08-13 | 中芯国际集成电路制造(上海)有限公司 | MEMS device and preparation method thereof |
| CN110116984B (en) * | 2018-02-06 | 2022-01-28 | 中芯国际集成电路制造(上海)有限公司 | MEMS device and preparation method thereof |
| CN109712898A (en) * | 2018-12-10 | 2019-05-03 | 通富微电子股份有限公司 | A kind of packaging method and packaging |
| CN112872538A (en) * | 2021-01-08 | 2021-06-01 | 晶澳（邢台）太阳能有限公司 | Tin supplementing device and method for junction box |
| CN112872538B (en) * | 2021-01-08 | 2023-11-17 | 晶澳（邢台）太阳能有限公司 | Tin supplementing device and tin supplementing method for junction box |
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