CN104574541A

CN104574541A - Method and system for synchronizing time sequence of RSUs and multiple antennae

Info

Publication number: CN104574541A
Application number: CN201410836785.6A
Authority: CN
Inventors: 章佳钦; 黄日文; 周维; 林树亮
Original assignee: Shenzhen Genvict Technology Co Ltd
Current assignee: Shenzhen Genvict Technology Co Ltd
Priority date: 2014-12-26
Filing date: 2014-12-26
Publication date: 2015-04-29
Anticipated expiration: 2034-12-26
Also published as: CN104574541B

Abstract

The invention provides a method and a system for synchronizing time sequences of RSUs and multiple antennae, and aims to trigger all RSUs to generate external interruption through one same pulse signal so as to achieve time sequence synchronization of multiple RSUs. According to the method and the system, respective preset time delay is set for each RSU, after receiving the external interruption, each RSU transmits a signal after the respective preset time delay, the time interval between two RSUs corresponding to two adjacent transmitted signals is at least the preset time interval, and the preset time interval is a shortest time interval in which the two signals are not overlapped. Through the adoption of the method and the system, the problem of synchronizing a plurality of RSUs is solved, the transmitted signals of the RSUs have sufficient time intervals, an OBU can successfully analyze the signals transmitted from the RSUs, and thus the purpose of normal transaction with the RSUs is achieved.

Description

A kind of RSU and multiple antennas sequential synchronous method and system

Technical field

The present invention relates to intelligent transportation field, particularly relate to a kind of RSU and multiple antennas sequential synchronous method and system.

Background technology

At ETC (Electronic Toll Collection, electric non-stop toll) in free streaming system, in order to improve Transaction Success rate and efficiency, not only a RSU (Road-Side Units is often installed, roadside unit) next same OBU (the On board Unit of antenna, board units) complete transaction, generally each road installs even two RSU, all track of more than three on expressway, so the quantity of RSU generally has more than three.

If the sequential that every platform RSU transmits does not carry out synchro control, so just, the situation that synchronization has multiple stage RSU transmits simultaneously or each RSU transmits interval inadequate may be there is, the signal causing RSU to launch collides at space overlapping by this, OBU cannot successfully resolved after receiving this superposed signal, thus cannot complete the arm's length transaction with RSU.

So need now a kind of method can solve the stationary problem of multiple RSU and the problem at the enough time interval that transmits between each RSU, so that OBU successfully can resolve the signal that RSU launches, thus complete the arm's length transaction with RSU.

Summary of the invention

The invention provides a kind of RSU and multiple antennas sequential synchronous method and system, the present invention can solve the stationary problem of multiple RSU, and then ensure to have transmitted between each RSU time enough interval, so that OBU successfully can resolve the signal that RSU launches, thus completes the arm's length transaction with RSU.

A kind of multiple antennas sequential synchronous method, be applied to multiple antennas timing synchronization system, described system comprises the multiple RSU be connected with each other, the controller be connected with described multiple RSU, and described method comprises:

Each RSU receive respectively described controller send with each RSU one_to_one corresponding initialization information, described initialization information comprises respective mode of operation, respective down trigger mode, after receiving described initialization information mode of operation be main frame RSU as main frame RSU, all the other for from machine RSU, at least the initialization information of main frame RSU also comprises the synchronous sequence cycle;

Described main frame RSU sends to all RSU the pulse signal that the cycle is the described synchronous sequence cycle by its PWM interface;

Transmit by respective down trigger mode and respective default delay time after each RSU receives described pulse signal, wherein, the time interval between the default delay time of the RSU of identical triggering mode is not less than prefixed time interval.

Preferably, transmit by respective down trigger mode and respective default delay time after described each RSU receives described pulse signal and comprise:

Have no progeny in the rising edge trigger external of described pulse signal, the RSU that down trigger mode is all rising edge triggering transmits by respective default delay time; And/or

Have no progeny in the negative edge trigger external of described pulse signal, the RSU that down trigger mode is all negative edge triggering transmits by respective default delay time.

Preferably, determine that the concrete grammar of the respective default delay time of described each RSU is:

For rising edge triggering mode and negative edge triggering mode, in identical triggering mode, determine that the default delay time of a RSU is the very first time respectively, the default delay time of all the other RSU at least increases progressively described prefixed time interval successively on the basis of the described very first time; Or

The down trigger mode setting all RSU is identical, determines that the default delay time of a RSU was the second time in all RSU, and the default delay time of all the other RSU at least increases progressively described prefixed time interval successively on described second time basis.

Preferably, each RSU receives after described pulse signal produces external interrupt by respective down trigger mode and also comprises:

Each RSU is according to the design variables value of pulse signal by preset rules change self;

If the design variables value of self does not change in Preset Time, then send alerting signal to described controller.

Preferably, further comprising the steps of:

Described controller receives the alerting signal that warning RSU sends, and whether whether the quantity that judges the RSU of transmission alerting signal comprise main frame RSU in predetermined number;

The quantity of RSU judging to send alerting signal is in predetermined number and do not comprise main frame RSU, then carry out timing synchronization reparation to each warning RSU;

Judge that the RSU quantity sending alerting signal exceedes described predetermined number or comprises main frame RSU, then timing synchronization reparation is carried out to all RSU.

Preferably, describedly timing synchronization reparation carried out to each warning RSU comprise:

Again respective initialization information is sent to each warning RSU, after the first Preset Time, judge that whether the timing synchronization of described each warning RSU is normal, if abnormal, send reset instruction to abnormal RSU, abnormal RSU is resetted, after the second Preset Time, judge that whether the timing synchronization of abnormal RSU is normal, if abnormal, carry out alarm, if timing synchronization normally, terminates to repair;

Describedly timing synchronization reparation carried out to all RSU comprise:

Select next RSU as main frame RSU, described controller resends initialization information to all RSU, after the first Preset Time, judge that whether the timing synchronization of all RSU is normal, if abnormal, whether whether the quantity that then judges the RSU sending alerting signal comprise main frame RSU in predetermined number, if the quantity of RSU sending alerting signal is in predetermined number and do not comprise main frame RSU, then described timing synchronization reparation is carried out to each warning RSU; If the RSU quantity sending alerting signal exceedes described predetermined number or comprises main frame RSU, then send reset instruction to all RSU, all RSU are resetted; After the second Preset Time, judge that whether the sequential of all RSU is normal, if abnormal, reselect a RSU again, as main frame RSU, timing synchronization reparation is carried out to all RSU, until the sequential of all RSU is normal, if the sequential of all RSU normally in repair process, terminate to repair.

A kind of multiple antennas sequential synchronous method, be applied to multiple antennas timing synchronization system, described system comprises multiple RSU, the controller be connected with described multiple RSU, and described method comprises:

Each RSU receive respectively described controller send with each RSU one_to_one corresponding initialization information, described initialization information comprises respective down trigger mode;

It is the pulse signal in synchronous sequence cycle that each RSU receives the cycle that described controller sends respectively;

A kind of RSU, comprising:

Receiver module, for receiving the initialization information that described controller sends, described initialization information comprises mode of operation, down trigger mode;

Principal and subordinate's judge module, for carrying out judgement to mode of operation, when described mode of operation is main frame, described RSU is as main frame RSU, and when described mode of operation is from machine, described RSU is as from machine RSU;

Operational module, for when described RSU is main frame RSU, be then the pulse signal in described synchronous sequence cycle to the cycle that all RSU send by its PWM interface, when described RSU is from machine RSU, then the cycle of Receiving Host RSU transmission is the pulse signal in described synchronous sequence cycle, transmit by respective down trigger mode and respective default delay time after receiving described pulse signal, wherein, the time interval between the default delay time of the RSU of identical triggering mode is not less than prefixed time interval.

A kind of multiple antennas timing synchronization system, comprising:

The RSU multiple as claimed in claim 8 be connected with each other, the controller be connected with described multiple RSU;

Described controller, for generating and each RSU one_to_one corresponding initialization information respectively, described initialization information comprises respective mode of operation, respective down trigger mode and synchronous sequence cycle, sends initialization information one to one to each RSU.

A kind of multiple antennas timing synchronization system, comprising:

Multiple RSU, the controller be connected with described multiple RSU;

Described controller, for generating and each RSU one_to_one corresponding initialization information respectively, described initialization information comprises respective down trigger mode and synchronous sequence cycle; Initialization information is one to one sent to each RSU;

Described RSU comprises the first receiver module and the first operational module; First receiver module is that send with each RSU one_to_one corresponding initialization information for receiving described controller, and described initialization information comprises respective down trigger mode, and receive the cycle that described controller sends is the pulse signal in described synchronous sequence cycle simultaneously; Described first operational module transmits by respective down trigger mode and respective default delay time after receiving described pulse signal, and wherein, the time interval between the default delay time of the RSU of identical triggering mode is not less than prefixed time interval.

The invention provides a kind of multiple antennas sequential synchronous method and system, each RSU of the present invention is connected with each other and each RSU is all connected with controller, same pulse signal is sent to each RSU by controller simultaneously, so each RSU can receive pulse signal simultaneously, or same pulse signal is sent to each from machine RSU by main frame RSU, each RSU is return pulse signal simultaneously, two kinds of modes all can realize each RSU and trigger all RSU generation external interrupt, so can realize the timing synchronization of multiple RSU by same pulse signal.

And, the present invention is that each RSU sets respective default delay time, each RSU is after reception external interrupt, transmit again by after respective default delay time time delay, ensure that the time interval of two RSU corresponding to adjacent transmission signal at least differs prefixed time interval, prefixed time interval is the minimum time interval that two signals do not overlap.So the present invention can solve the stationary problem of multiple RSU, ensure to have transmitted between each RSU enough time interval problem simultaneously, to reach the signal that OBU successfully can resolve RSU transmitting, thus complete the object with the arm's length transaction of RSU.

Accompanying drawing explanation

In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.

The structural representation of Fig. 1 a kind of multiple antennas timing synchronization system disclosed in the embodiment of the present invention;

The process flow diagram of Fig. 2 a kind of multiple antennas sequential synchronous method disclosed in the embodiment of the present invention;

The schematic diagram of delay time is preset in Fig. 3 a-3e a kind of multiple antennas sequential synchronous method disclosed in the embodiment of the present invention;

Fig. 4 is the process flow diagram of the embodiment of the present invention another multiple antennas sequential synchronous method disclosed;

Fig. 5 is the process flow diagram of the embodiment of the present invention another multiple antennas sequential synchronous method disclosed;

Fig. 6 is the process flow diagram of the embodiment of the present invention another multiple antennas sequential synchronous method disclosed;

Fig. 7 is the process flow diagram of the embodiment of the present invention another multiple antennas sequential synchronous method disclosed;

Fig. 8 is the process flow diagram of the embodiment of the present invention another multiple antennas sequential synchronous method disclosed;

The down trigger schematic diagram of Fig. 9 a kind of multiple antennas sequential synchronous method disclosed in the embodiment of the present invention;

Figure 10 is a kind of synchronous sequence cycle of multiple antennas sequential synchronous method and the schematic diagram of default delay time disclosed in the embodiment of the present invention;

Figure 11 is a kind of synchronous sequence cycle of multiple antennas sequential synchronous method and the schematic diagram of default delay time disclosed in the embodiment of the present invention;

The structural representation of Figure 12 a kind of RSU disclosed in the embodiment of the present invention.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.

As shown in Figure 1, the invention provides a kind of multiple antennas timing synchronization system, described system comprises the multiple RSU 100 be connected with each other, the controller 200 be connected with described multiple RSU 100.Multiple RSU adopts RSU 1, RSU 2 ... RSU N represents, N is non-zero natural number.

In native system, each RSU is connected with each other by bus, when data are present on the bus, each RSU all can obtain this data simultaneously, and each RSU is all connected with controller in addition, when controller sends data to all RSU simultaneously, all RSU all can receive same data simultaneously.

As shown in Figure 2, the invention provides a kind of multiple antennas sequential synchronous method, be applied to the RSU of system shown in Figure 1, described method comprises:

Step S101: each RSU receive respectively described controller send with each RSU one_to_one corresponding initialization information, described initialization information comprises respective mode of operation, respective down trigger mode, after receiving described initialization information mode of operation be main frame RSU as main frame RSU, all the other for from machine RSU, at least the initialization information of main frame RSU also comprises the synchronous sequence cycle;

All RSU all can perform and once launch the process with OBU buying signals within a synchronous sequence cycle, each RSU synchronized transmissions signal should be realized within each synchronous sequence cycle, make again to maintain certain time interval between the transmitting of each RSU, to reach multiple RSU synchronized transmissions signal can ensure that again signal is not overlapping, so the mode that the present invention adopts all RSU to adopt same pulse signal trigger external to interrupt is to realize the object of synchronized transmissions signal, be adopted as mode that each RSU sets respective delay time to realize keeping certain time interval between the transmitting of each RSU.

To achieve these goals, before the present invention performs, need controller to set the mode of operation of each RSU, the synchronous sequence cycle that the down trigger mode of each RSU and all RSU use jointly, then the mode of operation of each RSU, down trigger mode and synchronous sequence cycle are sent to each RSU, so that the mode that each RSU sets according to controller performs.Further, if RSU is from machine, then also only can sends mode of operation, the down trigger mode of RSU, and not send the synchronous sequence cycle.

Wherein mode of operation is main frame or from machine, down trigger mode is that rising edge triggers or negative edge triggers, the synchronous sequence cycle is a variable quantity, when default delay time change and/or the change of RSU quantity of RSU, the synchronous sequence cycle all can change, in order to reach the object that all RSU all can transmit within a synchronous sequence cycle, the synchronous sequence cycle is at least default delay time and the value of each RSU.

Step S102: described main frame RSU sends to all RSU the pulse signal that the cycle is the described synchronous sequence cycle by its PWM interface;

Within a synchronous sequence cycle, only having a main frame, all the other are from machine, mode of operation is that main frame then represents that control order receives the RSU of this mode of operation as main frame RSU, mode of operation is then represent that RSU that control order receives this mode of operation is as from machine RSU from machine, main frame RSU has the ability sending pulse signal, when main frame RSU generation pulse signal is supplied to and self sends pulse signal by the PWM interface of self in bus simultaneously, all RSU all from return pulse signal bus, can interrupt to trigger self according to pulse signal.

Step S103: each RSU receive described pulse signal after transmit by respective down trigger mode and respective default delay time, wherein, the time interval between the default delay time of the RSU of identical triggering mode is not less than prefixed time interval.

After each RSU return pulse signal, just the down trigger mode according to self produces external interrupt at the rising edge of pulse signal or negative edge, and according to respective default delay time, transmit after default delay time after down trigger, default delay time can be that controller precalculates out, and be initialized to each RSU inside by initialization information, also can be that RSU is after acquisition initialization information, any mode calculates according to initialization information, no matter all can realize.

The down trigger mode of RSU is relevant to the default delay time of himself, down trigger mode changes, the default delay time of self also can change, no matter but adopt that triggering mode, the prefixed time interval that must reach the RSU corresponding to adjacent transmission signal at least differs prefixed time interval, prefixed time interval be in theory two RSU transmit can not be overlapping the time interval, if the time interval of the default delay time of two of adjacent transmission signal RSU is less than prefixed time interval, then can cause both signal overlap collisions.

The present invention can realize multiple RSU timing synchronization, and adjacent transmission signal can not overlapping collide, so OBU can receive transmitting of RSU preferably, to conclude the business with RSU.

The invention provides a kind of multiple antennas sequential synchronous method, each RSU of the present invention is connected with each other by bus and each RSU is all connected with controller, same pulse signal is sent to each RSU by controller simultaneously, each RSU can receive pulse signal simultaneously, or same pulse signal is sent to bus by main frame RSU, each RSU is simultaneously through bus return pulse signal, two kinds of modes all can realize each RSU and receive same pulse signal simultaneously, trigger all RSU by same pulse signal and produce external interrupt, so the timing synchronization of multiple RSU can be realized.

And, the present invention is that each RSU sets respective default delay time, each RSU is after reception external interrupt, transmit again by after respective default delay time time delay, ensure that the time interval between two RSU corresponding to adjacent transmission signal is at least prefixed time interval, prefixed time interval is the minimum time interval that two signals do not overlap.So the present invention can solve the stationary problem of multiple RSU, ensure to have transmitted between each RSU enough time interval problem simultaneously, to reach the signal that OBU successfully can resolve RSU transmitting, thus complete the object with the arm's length transaction of RSU.

Introduce the process determining each RSU default delay time separately below in detail, the default delay time of each RSU, can by the algorithm realization of therein, after also can being precalculated by controller, be issued to each RSU again, the default delay time of setting RSU is mainly divided into two kinds of modes:

The first: the triggering mode of all RSU is incomplete same;

For rising edge triggering mode and negative edge triggering mode, in identical triggering mode, determine that the default delay time of a RSU is the very first time respectively, the default delay time of all the other RSU at least increases progressively described prefixed time interval successively on the basis of the described very first time; It is easily understood that it is all feasible that the time interval increased progressively only is greater than prefixed time interval ensureing under the prerequisite in the cycle that transmits.

Below by several specific embodiment, first kind of way is described, for four RSU, represents with label 1,2,3 and 4 respectively:

A: setting 1 and 3 is rising edge triggering mode, 2 and 4 is negative edge triggering mode, the default delay time of 1 and 2 is 0, the default delay time of 3 and 4 is t, t is more than or equal to prefixed time interval, then the trigger sequence of four RSU is 1,3,2 and 4 in the manner described above, as shown in Figure 3 a, is the schematic diagram that transmits of above 4 RSU.Under this triggering mode, the synchronous sequence cycle is that high level and low level respectively account for half.

B: setting 1 and 3 is rising edge triggering mode, 2 and 4 is negative edge triggering mode, the default delay time of 1 and 2 is 0, the default delay time of 3 and 4 is 2t, t is more than or equal to prefixed time interval, then the trigger sequence of four RSU is 1,2,3 and 4 in the manner described above, as shown in Figure 3 b, is the schematic diagram that transmits of above 4 RSU.Under this triggering mode, high level accounts for 1/4 the synchronous sequence cycle, and low level accounts for 3/4.

C: setting 1 and 2 is rising edge triggering mode, 3 and 4 is negative edge triggering mode, then the delay time of 1 and 3 is 0, the delay time of 2 and 4 is t, t is more than or equal to prefixed time interval, then the trigger sequence of four RSU is 1,2,3 and 4 in the manner described above, as shown in Figure 3 c, is the schematic diagram that transmits of above 4 RSU.Under this triggering mode, the synchronous sequence cycle is that high level and low level respectively account for half.

Certainly other triggering mode and delay time can also be set, under different triggering mode, the delay time of each RSU is different, thus cause the synchronous sequence cycle inconsistent, no matter as long as at least keep prefixed time interval between two RSU adopting any mode can realize adjacent transmission signal.

The second: the triggering mode of all RSU is identical;

D: all RSU is all rising edge triggers, the delay time selecting label 1 is 0, the delay time t of label 2, the delay time of label 3 is 2t, the delay time of label 4 is 3t, then the trigger sequence of four RSU is 1,2,3 and 4 in the manner described above, as shown in Figure 3 d, is the schematic diagram that transmits of above 4 RSU.

E: all RSU is all lower liter along triggering, the delay time of selection label 1 is delay time is 0, the delay time t of label 2, the delay time of label 3 is 2t, the delay time of label 4 is 3t, then the trigger sequence of four RSU is 1,2,3 and 4 in the manner described above, as shown in Figure 3 e, is the schematic diagram that transmits of above 4 RSU.

In the setting means of the second Preset Time, all RSU are a kind of triggering mode, the triggering mode of negative edge does not use, so under the prerequisite that the time delay interval of each RSU is certain, in the second triggering mode, the synchronous sequence cycle is longer, and the frequency causing each RSU to transmit is lower.

As shown in Figure 4, the invention provides a kind of multiple antennas sequential synchronous method, be applied to the RSU of system shown in Figure 1, described method comprises:

Step S201: each RSU receive respectively described controller send with each RSU one_to_one corresponding initialization information, described initialization information comprises respective down trigger mode and synchronous sequence cycle;

Step S202: each RSU to receive the cycle that described controller sends respectively be the pulse signal in described synchronous sequence cycle;

Step S203: each RSU receive described pulse signal after transmit by respective down trigger mode and respective default delay time, wherein, the time interval between the default delay time of two RSU corresponding to adjacent transmission signal is not less than prefixed time interval.

The general idea of method shown in Fig. 4 is consistent with the method shown in Fig. 2, both differences are only that the mode sending pulse signal is different, Fig. 1 is that main frame RSU sends pulse signal by bus to all RSU, the method of Fig. 4 is that controller sends signal to all RSU, remaining content is consistent, does not repeat them here.

Fig. 4 controller is as the pulse signal sent needed for each RSU, when controller breaks down, all RSU all can not realize timing synchronization, send pulse signal with main frame RSU in Fig. 2, after main frame RSU goes wrong, other RSU can also be adopted as main frame, again timing synchronization is realized, just realize in effect, the mode shown in Fig. 2 is comparatively reliable, and the mode in realization shown in Fig. 4 is comparatively simple.Both respectively have quality.

Because environmental impact or RSU break down, may there is nonsynchronous phenomenon in RSU, in order to solve this phenomenon, the present invention is on the basis of method shown in Fig. 2, receive after described pulse signal produces external interrupt by respective down trigger mode at each RSU, as shown in Figure 5, also comprise:

Step S301: each RSU according to the design variables value of pulse signal by preset rules change self;

When RSU under normal circumstances, external interrupt can be produced according to after pulse signal, when RSU is abnormal, then external interrupt can not be produced, so the present invention is after RSU produces external interrupt, change a design variables value of RSU inside self, as long as RSU can produce external interrupt, then design variables value changes once within a synchronous sequence cycle.

The mode changed can have multiple, such as: setting design variables is a certain value, adopt the mode increased progressively successively, the mode of successively decreasing successively or increase the modes such as fixed value, as long as the mode that can change design variables value all can be used as the preset rules in the present embodiment.

Step S302: judge whether design variables value changes in Preset Time;

RSU is at all after dates of a synchronous sequence, or all after dates of multiple synchronous sequence judge that whether the design variables value of therein is consistent with the variate-value of last registration, if consistent, represent that design variables value does not change, namely this RSU occurs that timing synchronization is abnormal, if inconsistent, then represent that design variables value is more last to change, namely RSU timing synchronization is normal.

Step S303: if the design variables value of self does not change in Preset Time, then send alerting signal to described controller.

Step S304: if the design variables value of self changes in Preset Time, then do not deal with.

If RSU timing synchronization is abnormal, then send alerting signal to controller, to point out controller self timing synchronization abnormal, so that controller carries out subsequent treatment, to occurring that abnormal RSU carries out sequential reparation.

Introduce the processing procedure of controller after receiving alerting signal below, as shown in Figure 6, a kind of multiple antennas sequential synchronous method of the present invention, be applied to system as shown in Figure 1, this method comprises:

Step S401: receive the alerting signal that multiple warning RSU sends;

Step S402: whether whether the quantity that judges the RSU sending alerting signal comprise main frame RSU in predetermined number;

Controller is after reception alerting signal, first the RSU quantity sending alerting signal is checked, and each mode of operation of reporting to the police, then the quantity of warning RSU and the size of predetermined number is judged, and judge whether the mode of operation of warning RSU has main frame RSU, wherein, predetermined number can be the half of RSU total amount.

When the RSU more than RSU total amount half breaks down, then illustrate it is that main frame RSU breaks down, when the RSU being less than RSU total amount half breaks down, then illustrate it is that indivedual RSU breaks down.

Step S403: judging to send the RSU quantity of alerting signal in predetermined number does not comprise main frame RSU, then carry out timing synchronization reparation to each warning RSU;

When the quantity of warning RSU is less than predetermined number and does not comprise main frame RSU, then illustrate that self sequential of other RSU occurs abnormal, then only need to carry out sequential to the RSU reported to the police and repair, the normal RSU of all the other sequential is without the need to carrying out sequential reparation.

Step S404: judge that the RSU quantity sending alerting signal exceedes described predetermined number or comprises main frame RSU, then timing synchronization reparation is carried out to all RSU.

When the quantity of warning RSU exceedes half or comprises main frame RSU, then illustrate that main frame RSU occurs abnormal, when main frame RSU occurs that extremely, all RSU all may occur exception, so need all to carry out timing synchronization reparation to all RSU.

Be described in detail as shown in Figure 7 in step S403 to the process that each warning RSU carries out timing synchronization reparation below, comprise:

Step S501: again send respective initialization information to each warning RSU;

Controller sends initialization information again to each warning RSU, to re-start initialization to warning RSU, then RSU return pulse signal generation external interrupt again, and judge the design variables value of self, if timing synchronization is normal, no longer sends alerting signal to controller, occur synchronous abnormality if continue, continue to send alerting signal to controller.

Step S502: judge that after the first Preset Time whether the timing synchronization of described each warning RSU is normal;

The first Preset Time after carrying out initialization, again judge whether the alerting signal receiving again initialized RSU transmission, if do not receive, illustrate that timing synchronization reparation completes, warning RSU has returned normally, if still receive the alerting signal that RSU sends, then illustrate that this RSU is abnormal RSU.

Step S503: if abnormal, then send reset instruction to abnormal RSU, reset to abnormal RSU; If normal, enter step S506;

There is abnormal RSU if continue, then send reset instruction to abnormal RSU, again RSU is resetted, namely power on and restart.

Step S504: after the second Preset Time, judges that whether the timing synchronization of abnormal RSU is normal;

Judge whether the RSU carrying out resetting sends alerting signal, if still send alerting signal, then illustrates that this RSU breaks down through after a while again, then carry out alarm, need on-call maintenance, if timing synchronization is normal to point out this RSU of staff, then illustrate that RSU has returned normally, still can continue to use.

Step S505: if abnormal, carries out alarm, if normal, enters step S506;

Step S506: if timing synchronization normally, terminates to repair.

The above is to the nonsynchronous repair process of indivedual RSU sequential, introduces below when the nonsynchronous repair process of sequential appears in main frame RSU, as shown in Figure 8, comprising:

Step S601: select next RSU as main frame RSU, described controller resends initialization information to all RSU;

If because main frame RSU occurs that the abnormal timing synchronization that causes is abnormal, then change main frame RSU, reselect next RSU as main frame RSU, controller re-executes timing synchronization process as shown in Figure 2, then determines whether the process occurring timing synchronization exception shown in Fig. 5 performing.If RSU timing synchronization is abnormal, send alerting signal to controller, if RSU timing synchronization is normal, do not deal with.

Step S602: judge that after the first Preset Time whether the timing synchronization of all RSU is normal;

If after the first Preset Time, do not receive the alerting signal that RSU sends, then illustrate that all RSU timing synchronizations are normal, enter step S607, if after the first Preset Time, still receive alerting signal, then enter step S603;

Step S603: whether whether the quantity that judges the RSU sending alerting signal do not comprise main frame RSU in predetermined number; If then enter step S604, then enter step S605 if not;

Step S604: if the quantity of RSU that sends alerting signal does not comprise main frame RSU in predetermined number, then describedly carry out timing synchronization reparation to each warning RSU;

The particular content of this step refers to Fig. 7 and does not repeat them here.

Step S605: if the RSU quantity sending alerting signal exceedes described predetermined number or comprises main frame RSU, then send reset instruction to all RSU, all RSU are resetted;

After changing main frame RSU, still there is the problem of timing synchronization exception, then all RSU are resetted, power on and restart, so that all RSU reply Default Value, then re-execute initialized process, again carry out the judgement of timing synchronization and timing synchronization exception.

Step S606: after the second Preset Time, judges that whether the sequential of all RSU is normal;

If normal, then enter step S607, if abnormal, enter step S601;

If abnormal, then reselect next RSU, as main frame RSU, timing synchronization reparation is carried out to all RSU, until the sequential of all RSU is normal or traveled through all RSU.If the sequential of all RSU normally in repair process, terminate to repair.Still can not be normal by all RSU timing synchronizations when having traveled through all RSU, then illustrate that all RSU all break down, need overall maintenance, and alarm is to remind staff's on-call maintenance.

Step S607: if normal, then terminate to repair.

The present invention provide not only the method for timing synchronization, and provide sequential abnormal time carry out the method for repairing, timing synchronization can not only be carried out and can also carry out sequential reparation, thus ensure RSU timing synchronization, facilitate RSU and OBU to communicate.

Introduce specific embodiments of the invention below, to be described in detail to method of the present invention:

In hardware design, multiple RSU and controller form LAN (Local Area Network), are communicated between RSU, controller by network, connected carry out the synchronous of signal sequence between each RSU by bus.Concrete structure as shown in Figure 1.

485 buses are adopted when concrete use, because 485 interfaces are the combinations adopting balance driver and differential receiver, anti-common mode interference ability is strong, namely noise immunity is good, and transmission range can reach more than 1000 meters, meet in free streaming system, the distance between RSU may reach tens meters, even the requirement of up to a hundred meters.

A MCU and 485 modules are all had in each RSU, MCU is the processor of RSU self, 485 modules are bus module, MCU as the RSU of main frame produces pwm pulse signal, this pulse signal is guided to RSU self MCU by 485 modules again and is produced external interrupt, and by 485 modules of 485 bus transfer to other RSU, make other produce the MCU external interrupt of RSU.As shown in Figure 9, be the diagram of each RSU down trigger.

On Software for Design, first introduce RSU side, distribute a different IP address first to every platform RSU, controller distributes a numbering according to different IP addresses to RSU.Such as, when the 4 single antenna in track, distribution condition can be as shown in table 1 below:

Table 1

Numbering	IP address	Installation site
			0	192.168.5.187	Standby track
1	192.168.5.188	Slow lane
			2	192.168.5.189	Fast traffic lane
3	192.168.5.190	Fast

Controller software realizes the configurable of systematic parameter.Configuration available parameter is as follows: 1. RSU quantity; 2. the signal synchronous sequence cycle of system; 3. interval time between RSU signal; 4. RSU transmits down trigger pattern (rising edge or negative edge trigger); 5. RSU mode of operation (main frame or from machine).

System start time or initialization time, controller by the parameter initialization of system to all RSU.The form of data is defined as follows:

Table 2

RSU quantity	Rsu_num＝N
		RSU numbers	Idx＝0～N-1
The signal synchronous sequence cycle of system	SyncTime
		Interval time between RSU signal	IntervalTime
RSU transmits down trigger pattern	SyncEdge
		RSU mode of operation	Mode＝Master/Slave

1., wherein SyncTime=IntervalTime*N, such as, when the time interval of RSU signal be 7ms, RSU quantity is 4, cycle lock in time of system is exactly 28ms, RSU quantity when being 5, and cycle lock in time of system is exactly 35ms.

2., the RSU down trigger pattern value that transmits is 0 or 1,0 represents rising edge triggers, 1 represents negative edge triggers, and its C language represents that computing formula is as follows: SyncEdge=idx & 0x01, and namely the down trigger situation of every platform antenna is as follows:

Table 3

RSU numbers	Down trigger pattern
		0	0: rising edge triggers
1	1: negative edge triggers
		2	0: rising edge triggers
3	1: negative edge triggers

Such as: when the quantity of RSU be signal sequence between 4, RSU be spaced apart 7ms time, the RSU in standby track is as main frame, and initialized data are as follows:

Table 4

Initialization data implication	Lay aside	Slow lane	Fast traffic lane	Fast
					RSU quantity	4	4	4	4
RSU numbers	0	1	2	3
					The signal synchronous sequence cycle of system	28	28	28	28
Interval time between RSU signal	7	7	7	7
					RSU transmits down trigger pattern	0	1	0	1

RSU mode of operation

0

1

After every platform RSU receives the initialization data that controller sends, as the PWM interface of the RSU of main frame, the cycle of sending is the PWM synchronizing signal of SyncTime, triggers all RSU and produces external interrupt (rising edge or negative edge trigger).The pwm pulse signal that main frame sends, the period proportional that height pulse takies can distribute according to the quantity of antenna, and C language represents that algorithm is as follows: the time shared by high impulse is: IntervalTime* (Rsu_num/2+Rsu_num%2).Such as, when there being 4 RSU, when between RSU signal, interval time is 7ms, cycle lock in time is 4*7=28, and the time that the pulse high impulse sent occupies is 7* (4/2+4%2)=14ms, and namely height pulse respectively accounts for 50%.When there being 5 RSU, cycle lock in time is 5*7=35, and the time that the pulse high impulse sent occupies is 7* (5/2+5%2)=21ms, and namely high impulse respectively accounts for the lock in time of 3/5, and low pulse account for 2/5.

After all RSU receive external interrupt, launch or transmit after time delay a period of time, the C language of time delay represents that algorithm is as follows: time delay is signaled time delay_time=(RSU numbering idx/2) * (between RSU signal interval time IntervalTime), i.e. delay_time=(idx/2) * IntervalTime.Such as, the delay time transmitted according to each RSU of the situation of illustrating above is as follows:

Table 5

Initialization data implication	Lay aside	Slow lane	Fast traffic lane	Fast
					RSU numbers	0	1	2	3
The signal synchronous sequence cycle of system	28	28	28	28
					Interval time between RSU signal	7	7	7	7
RSU transmits down trigger pattern	0	1	0	1
					The time that time delay is signaled	0	0	7	7

According to design above, after each RSU timing synchronization of free streaming system in 4 tracks, skyborne signal as shown in Figure 10.

Wherein, RSU_0 is as main frame, and the cycle of sending is the pwm pulse of 28ms.RSU_0 and RSU_2 is that rising edge triggered interrupts transmits, RSU_1 and RSU_3 is that negative edge triggered interrupts transmits.Transmit after RSU_0 and RSU_1 down trigger at once, transmit again after the time delay of 7ms after RSU_2 and RSU_3 down trigger.Equally, if not the free streaming system in 4 tracks, neat aerial signal timing distribution also can be obtained according to design above.Such as, after each RSU timing synchronization of free streaming system in 5 tracks, skyborne signal as shown in figure 11.

After carrying out timing synchronization, how supervisory system signal sequence synchronous situation and when the timing synchronization failure of system, how again self-healing system, make sequential re-synchronization, and concrete realization is as follows:

Every platform RSU is by interrupting the synchronous of activation schedule, therefore defines a variable sync_irq_time, at every turn when external interrupt produces, by RSU from starting to current elapsed time assignment to this variable.That is, each generation interrupted, variable sync_irq_time can impart new value, and value increases progressively.Such as, if when the system signal timing synchronization cycle is 28ms, when so each interruption produces, the value of sync_irq_time will increase by 28.Therefore the situation of change of the value of Real-Time Monitoring sync_irq_time, if this value certain hour (can value 200ms) does not all change, so just judge that this RSU has not had timing synchronization signal to trigger, think that the synchronous sequence of this RSU is abnormal.

Oneself variable sync_irq_time own is uploaded to controller by every platform RSU in real time, and controller carries out self-healing, the alarm operation of system synchronization signal according to the synchronous situation of whole system, is implemented as follows:

If do not comprise the RSU timing synchronization existing problems of main frame within 1. whole system exists half, be so judged as that the sequential of other RSU own is not synchronous, controller carrys out the concrete RSU of self-healing according to rule below:

1) controller is again sent out initialization directive and is carried out the whole state of initialization this RSU, RSU and re-started initialization, comprises having reconfigured external interrupt interface, reconfiguring the timing synchronization cycle etc.;

2) confirm in 30 seconds whether the timing synchronization of this RSU recovers normal, if normally, repair and terminate, do not produce alarm;

3) if or abnormal, controller sends reset this RSU, RSU of reset instruction to carry out reset and restarts;

4) confirm in 60 seconds whether the timing synchronization of this RSU recovers normal, if normally, repair and terminate, do not produce alarm;

5) if still abnormal, produce this RSU timing synchronization alarm, and every 3 minutes, repeat 1) to 5) step, attempt repairing, if can repair, alarm clearance, this RSU recovers normally monitoring;

If 2. whole system exists RSU timing synchronization existing problems that are more than half or main frame, be so judged as that the RSU as main frame has problems, controller carrys out the sequential of the concrete whole system of self-healing according to rule below:

1) reselect next RSU as main frame, such as, if current main frame is RSU_1, so just selects RSU_2 as main frame, when the main frame selected arrives last, reselect First as main frame;

2) controller is again sent out initialization directive and is carried out initialization whole system, namely reinitializes all RSU;

3) confirm in 30 seconds whether the timing synchronization of system recovers normal, if normally, repair and terminate, do not produce alarm;

4) if or abnormal, controller sends reset whole RSU, RSU of reset instruction to carry out reset and restarts;

5) confirm in 60 seconds whether the timing synchronization of system recovers normal, if normally, repair and terminate, do not produce alarm;

6) if or abnormal, produce corresponding RSU timing synchronization alarm, and every 3 minutes, repeat 1) to 5) step;

7) if system has entered condition 1., reparation alarm logic 1. is so just entered.

As shown in Figure 1, the invention provides a kind of multiple antennas timing synchronization system, comprising:

By multiple RSU 100 that bus is connected with each other, the controller 200 be connected with described multiple RSU;

Described controller 200, for generating and each RSU one_to_one corresponding initialization information respectively, described initialization information comprises respective mode of operation, respective down trigger mode and synchronous sequence cycle, sends initialization information one to one to each RSU;

Described multiple RSU100, for each RSU receive respectively described controller send with each RSU one_to_one corresponding initialization information, described initialization information comprises respective mode of operation, respective down trigger mode and synchronous sequence cycle; After receiving described initialization information mode of operation be the RSU of main frame as main frame RSU, all the other are for from machine RSU, described main frame RSU sends to all RSU the pulse signal that the cycle is the described synchronous sequence cycle by its PWM interface, transmit by respective down trigger mode and respective default delay time after each RSU receives described pulse signal, wherein, the time interval between corresponding two the default delay times of two RSU of adjacent transmission signal is not less than prefixed time interval.

Multiple RSU100, the controller 200 be connected with described multiple RSU;

Described controller 200, for generating and each RSU one_to_one corresponding initialization information respectively, described initialization information comprises respective down trigger mode and synchronous sequence cycle; Initialization information is one to one sent to each RSU;

Described multiple RSU100, for each RSU receive respectively described controller send with each RSU one_to_one corresponding initialization information, described initialization information comprises respective down trigger mode and synchronous sequence cycle; It is the pulse signal in described synchronous sequence cycle that each RSU receives the cycle that described controller sends respectively, transmit by respective down trigger mode and respective default delay time after each RSU receives described pulse signal, wherein, the time interval between corresponding two the default delay times of adjacent transmission signal two RSU is not less than prefixed time interval.

The invention provides a kind of multiple antennas timing synchronization system, each RSU of the present invention is connected with each other by bus and each RSU is all connected with controller, same pulse signal is sent to each RSU by controller simultaneously, so each RSU can receive pulse signal simultaneously, or same pulse signal is sent to bus by main frame RSU, each RSU is simultaneously through bus return pulse signal, two kinds of modes all can realize each RSU and receive same pulse signal simultaneously, trigger all RSU by same pulse signal and produce external interrupt, so the timing synchronization of multiple RSU can be realized.

And, the present invention is that each RSU sets respective default delay time, each RSU is after generation external interrupt, transmit again by after respective default delay time time delay, the time interval between two RSU that ensureing is connected transmits is at least prefixed time interval, prefixed time interval is the minimum time interval that two signals do not overlap, and makes to have time enough interval between two signals adjacent in space, can not produce signal overlap.So the present invention can solve the stationary problem of multiple RSU and the enough time interval problem that transmitted between each RSU, to reach OBU successfully can resolve the signal that RSU launches, thus complete the object with the arm's length transaction of RSU.

Present invention also offers a kind of RSU corresponding with Fig. 1, as shown in figure 12, comprising:

Receiver module 11, for receiving the initialization information that described controller sends, described initialization information comprises mode of operation, down trigger mode;

Principal and subordinate's judge module 12, for carrying out judgement to mode of operation, when described mode of operation is main frame, described RSU is as main frame RSU, and when described mode of operation is from machine, described RSU is as from machine RSU;

Operational module 13, for when described RSU is main frame RSU, be then the pulse signal in described synchronous sequence cycle to the cycle that all RSU send by its PWM interface, when described RSU is from machine RSU, then the cycle of Receiving Host RSU transmission is the pulse signal in described synchronous sequence cycle, transmit by respective down trigger mode and respective default delay time after receiving described pulse signal, wherein, the time interval between the default delay time of the RSU of identical triggering mode is not less than prefixed time interval.

If the function described in the present embodiment method using the form of SFU software functional unit realize and as independently production marketing or use time, can be stored in a computing equipment read/write memory medium.Based on such understanding, the part of the part that the embodiment of the present invention contributes to prior art or this technical scheme can embody with the form of software product, this software product is stored in a storage medium, comprising some instructions in order to make a computing equipment (can be personal computer, server, mobile computing device or the network equipment etc.) perform all or part of step of method described in each embodiment of the present invention.And aforesaid storage medium comprises: USB flash disk, portable hard drive, ROM (read-only memory) (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disc or CD etc. various can be program code stored medium.

In this instructions, each embodiment adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiment, between each embodiment same or similar part mutually see.

To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.

Claims

1. a multiple antennas sequential synchronous method, is characterized in that, is applied to multiple antennas timing synchronization system, and described system comprises the multiple RSU be connected with each other, the controller be connected with described multiple RSU, and described method comprises:

2. the method for claim 1, is characterized in that, transmitting by respective down trigger mode and respective default delay time after described each RSU receives described pulse signal comprises:

3. method as claimed in claim 2, is characterized in that, determine that the concrete grammar of the respective default delay time of described each RSU is:

4. the method according to any one of claim 1-3, is characterized in that, each RSU receives after described pulse signal produces external interrupt by respective down trigger mode and also comprises:

5. method according to claim 4, is characterized in that, further comprising the steps of:

6. method as claimed in claim 5, is characterized in that, describedly carries out timing synchronization reparation to each warning RSU and comprises:

Describedly timing synchronization reparation carried out to all RSU comprise:

7. a multiple antennas sequential synchronous method, is characterized in that, be applied to multiple antennas timing synchronization system, described system comprises multiple RSU, the controller be connected with described multiple RSU, and described method comprises:

8. a RSU, is characterized in that, comprising:

9. a multiple antennas timing synchronization system, is characterized in that, comprising:

10. a multiple antennas timing synchronization system, is characterized in that, comprising:

Multiple RSU, the controller be connected with described multiple RSU;