CN104572518B

CN104572518B - A kind of storage device

Info

Publication number: CN104572518B
Application number: CN201410844479.7A
Authority: CN
Inventors: 蔡远彬; 欧康华; 柳树要
Original assignee: Hangzhou Huawei Digital Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2014-12-30
Filing date: 2014-12-30
Publication date: 2018-06-26
Anticipated expiration: 2034-12-30
Also published as: CN104572518A

Abstract

The embodiment of the invention discloses a kind of storage device, including：An at least bar printing wiring board PCB and a double data rate ddr interface, controller and storage particle are placed on every piece of PCB, the storage particle is connect with the controller, the controller is connect by DDR buses with the ddr interface, the ddr interface is placed on one of PCB, the DDR data lines in the DDR buses by the corresponding DDR data line groups of each controller into；The ddr interface is used to connect with the DDR sockets on mainboard where CPU；Wherein, the corresponding DDR data lines digit of each controller is less than the DDR data line digits that the DDR sockets provide；The controller receives the control signal that the CPU is sent, and stores particle reading and/or write-in target data from described according to the control signal.Using the embodiment of the present invention, system can be reduced from the propagation delay time of storage device read-write data.

Description

Storage device

Technical Field

The invention relates to the technical field of computers, in particular to a storage device.

Background

With the development of terminal technology, the demand of personal consumers, enterprises and the like for information storage is increasing, and the storage pressure on computers and servers is also increasing. As is well known, Hard disks include Hard Disk drives (Hard Disk drives, HDDs) and Solid State disks (Solid State disks, SSDs), in which the Solid State disks have the advantages of fast read/write speed, good shock resistance, low power consumption, and the like by using electronic storage media to store and read data instead of conventional magnetic media, and thus the Solid State disks are widely used in the face of increasing data volume and storage requirements.

The hard disk interface is a connecting part between the hard disk and a host system and is used for transmitting data between the hard disk and the host, and the quality of the hard disk interface directly influences the transmission time delay of the system for reading the data from the hard disk. At present, the common hard disk interfaces include IDE (Integrated Drive Electronics), SATA (Serial advanced technology Attachment, a Serial hardware Drive Interface based on industry standard), SCSI (Small Computer System Interface), and the like, the hard disk is connected to a south bridge through an Interface, and the south bridge is connected to a north bridge (north bridge) (as shown in fig. 1a, fig. 1a is a schematic diagram of a relationship between a solid state disk and a CPU provided in the prior art), so that the hard disk exchanges data through the south bridge and the north bridge followed by the CPU, and transmission delay of data in the read/write process is large.

Disclosure of Invention

The embodiment of the invention provides a storage device, which can reduce the transmission time delay of reading and writing data from the storage device by a system.

In a first aspect, an embodiment of the present invention provides a storage apparatus, including: the DDR interface is arranged on one PCB; DDR data lines in the DDR bus are composed of DDR data lines corresponding to each controller; the DDR interface is used for being connected with a DDR socket on a mainboard where the CPU is located; wherein,

the DDR data line bit number corresponding to each controller is smaller than the DDR data line bit number provided by the DDR socket; and the controller receives a control signal sent by the CPU and reads and/or writes target data from the storage particles according to the control signal.

With reference to the first aspect, in a first possible implementation manner of the first aspect, the number of DDR data lines corresponding to each controller is 8 bits.

With reference to the first aspect or the first possible implementation manner of the first aspect, in a second possible implementation manner of the first aspect, the memory particles include any one of a flash memory chip, a magnetic random access memory MRAM, a phase change random access memory PRAM, and a resistance change memory RRAM.

With reference to the first aspect, in a third possible implementation manner of the first aspect, if the number of the at least one printed circuit board PCB is n, n is greater than or equal to 2, and n is an integer, the storage device further includes n-1 flexible boards, two adjacent PCBs are electrically connected through the flexible boards, and controllers on the two PCBs are connected through the flexible boards.

With reference to the first aspect, in a fourth possible implementation manner of the first aspect, if the number of the at least one printed circuit board PCB is n, n is greater than or equal to 2, and n is an integer, the storage device further includes n-1 connectors through which two adjacent PCBs are electrically connected, where controllers on the two PCBs are connected through the connectors.

With reference to the first aspect, in a fifth possible implementation manner of the first aspect, if the number of the at least one PCB is n, n is greater than or equal to 2, and n is an integer, the storage device further includes n-1 PCB sub-boards, two adjacent PCBs are electrically connected through the PCB sub-boards, and controllers on the two PCBs are connected through the PCB sub-boards.

With reference to any one of the third to fifth possible implementation manners of the first aspect, in a sixth possible implementation manner of the first aspect, the storage device further includes a heat dissipation material, and the heat dissipation material is disposed between two adjacent PCBs.

With reference to the first aspect, the first possible implementation manner of the first aspect, and any one of the third to fifth possible implementation manners of the first aspect, in a seventh possible implementation manner of the first aspect, the DDR interface includes DDR3 and DDR 4.

With reference to the seventh possible implementation manner of the first aspect, in an eighth possible implementation manner of the first aspect, the storage device further includes a housing, the at least one printed circuit board PCB, the controller, and the storage particles are disposed inside the housing, and the DDR interface is disposed in the housing.

With reference to the first aspect, in a ninth possible implementation manner of the first aspect, the memory granule is connected to the controller through an open flash interface ONFI bus.

In the embodiment of the invention, the storage device comprises at least one Printed Circuit Board (PCB) and a Double Data Rate (DDR) interface, wherein a controller and storage particles are arranged on each PCB, the storage particles are connected with the controller, the controller is connected with the DDR interface through a DDR bus, and the DDR interface is arranged on one PCB; DDR data lines in the DDR bus are formed by the DDR data lines corresponding to each controller. By adopting the embodiment of the invention, the DDR interface is connected with the DDR socket on the mainboard where the CPU is located, so that the storage device performs data transmission with the CPU based on the memory channel, and the transmission time delay of reading and writing data from the storage device by the system can be reduced; meanwhile, the DDR data line bit number corresponding to each controller in the storage device is smaller than the DDR data line bit number provided by the DDR socket on the mainboard where the CPU is located, the extensible design of the storage device can be achieved, and the flexibility of designing the storage device is improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1a is a schematic diagram of a relationship between a solid state disk and a CPU provided in the prior art;

fig. 1 is a schematic structural diagram of a memory device according to an embodiment of the present invention;

FIG. 1b is a diagram illustrating a relationship between a storage device and a CPU according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of another structure of a memory device according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of another structure of a memory device according to an embodiment of the present invention;

FIG. 3a is a schematic diagram of another structure of a memory device according to an embodiment of the present invention;

FIG. 3b is a schematic diagram of another embodiment of a memory device;

fig. 3c is a schematic diagram of another structure of a memory device according to an embodiment of the invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a memory device according to an embodiment of the present invention, where in the embodiment of the present invention, the memory device may include: at least one Printed Circuit Board (PCB) 101, a Double Data Rate (DDR) interface 102, a controller 103, and memory particles 104.

The controller is connected with the DDR interface through a DDR bus, and the DDR interface is arranged on one PCB; the DDR data line in the DDR bus consists of DDR data lines corresponding to each controller, and the controllers receive control signals sent by the CPU and read and/or write target data from the memory particles according to the control signals; the DDR interface is used for being connected with a DDR socket on a mainboard where the CPU is located. Therefore, when the storage device provided by the embodiment of the invention is used on equipment such as a computer or a server, a DDR interface in the storage device can be directly connected with a DDR socket on a mainboard where a CPU is located. Because the DDR socket on the mainboard where the CPU is located is used for connecting the memory, the storage device is connected with the CPU through the memory channel, and when the CPU and the storage device carry out data transmission, the transmission time delay of reading and writing data from the storage device by the system can be effectively reduced, so that the DDR socket is suitable for being connected to equipment and used as a hard disk. For convenience of understanding, please refer to fig. 1b, where fig. 1b is a schematic diagram illustrating a relationship between a storage device and a CPU according to an embodiment of the present invention, and it can be seen that, the storage device according to the embodiment of the present invention is directly connected to a north bridge, so that a transmission path is short (only through the north bridge) when the storage device and the CPU perform data transmission, and transmission delay of reading and writing data from the storage device by a system can be effectively reduced.

In the embodiment of the invention, the DDR data line bit number corresponding to each controller is less than the DDR data line bit number provided by the DDR socket. For example, taking DDR4 on an X86 motherboard as an example, a DDR4 socket is usually 288 pins, where 72 pins represent DDR data lines, in the embodiment of the present invention, the DDR data line corresponding to each controller is smaller than the DDR data line provided by the DDR4 socket, for example, the DDR data line corresponding to each controller may be 4 bits, 8 bits, 16 bits, and so on. It should be noted that, in the embodiment of the present invention, the number of DDR data lines corresponding to each controller is only required to be smaller than the number of DDR data lines provided by a DDR socket (for example, the number of data lines of a DDR4 socket in an X86 architecture is 72), and the specific embodiment of the present invention is not limited thereto. For convenience of understanding, still taking the DDR4 socket as an example, assuming that the number of DDR data lines corresponding to each controller is 8 bits, the storage device based on the DDR4 socket may include 9 controllers at most, and assuming that one PCB includes 1 controller, the storage device may be designed as 9 PCBs at most, so that, by adopting the embodiment of the present invention, the storage device may be designed to be expanded, and the storage capacity of the storage device is increased.

It should be noted that in the specific implementation, because the addressing modes of the system when reading data from the hard disk and the memory are different, in the embodiment of the present invention, the DDR address line provided by the memory channel may not be used, that is, the DDR bus may only include the DDR data line and the DDR control line, where the DDR control line connected to the DDR socket is connected to each controller.

It should be noted that, the embodiments of the present invention do not limit the number of the printed circuit board, the controller, and the storage particles, and the specific number thereof can be set according to actual requirements. For example, assuming that it is desired to design a 800G memory device, and a printed circuit board with a suitable size can be made up to 500G at the maximum, two printed circuit boards can be used for design, wherein the two printed circuit boards are electrically connected, and the memory particles on the two printed circuit boards and the controller transmit data with the CPU through the DDR interface 102; if it is desired to design a memory device within 500G, a single printed wiring board may be used. In a specific implementation, the number of the controllers on each printed circuit board may be 1 or multiple, and the embodiment of the present invention is not limited. For convenience of understanding, for example, assuming that the controller has 8 memory channels (such as NAND channels), and each channel can be connected with 8 memory granules at most, the maximum number of memory granules that the controller can support is 64; if a maximum of 128 storage particles can be placed on the printed circuit board, two controllers may be disposed on the printed circuit board, wherein each controller is connected to 64 storage particles, and the two controllers are electrically connected. In a specific implementation, the number and unit capacity of the storage particles need to be selected according to the requirements of the storage device to be designed on the storage capacity, the size and the like, which is not limited in any way by the embodiment of the present invention.

For convenience of illustration, a scenario in which the storage device includes a printed circuit board and a controller is disposed on the printed circuit board (as shown in fig. 1), and referring to the following embodiments, in fig. 1, a controller 103, a storage granule 104 and a DDR interface 102 are disposed on the printed circuit board 101, and the storage granule 104 is connected to the controller 103 respectively, and the connection manner is determined by the nature of the storage granule 104 or a manufacturer. For example, if the memory particles are NAND FLASH FLASH memory chips developed or manufactured by companies such as Intel, Micron, SanDisk, Sony, etc., the memory particles are connected to the controller through an Open Nand FLASH Interface (ONFI) bus. For another example, if the memory particles are NAND FLASH flash memory chips developed or produced by Samsung and Toshiba, the memory particles are connected to the controller based on the Toggle DDR Mode standard, wherein the Toggle DDR Mode standard is derived from a brand new NAND flash memory interface standard established by Samsung and Toshiba in combination. In a specific implementation, a connection manner of the storage particles and the controller needs to be determined according to types of the storage particles, which is not limited in this embodiment of the present invention.

In specific implementation, the storage particles can be FLASH memory chips, such as NOR FLASH or NAND FLASH, wherein NOR and NAND are two main nonvolatile FLASH memories in the market, and NAND FLASH has the characteristics of large storage capacity and low read-write speed; the NOR FLASH has the characteristics of small storage capacity and high read-write speed; typically, NAND FLASH is used as Storage (Storage) and NOR FLASH is used to store codes (codes). Therefore, the flash memory chip can be selected according to actual requirements, and as a preferred embodiment, NAND FLASH flash memory chips are used as the memory particles, so that a memory device with larger memory capacity can be designed on the same-size printed circuit board.

It should be noted that the memory particles may also be any one of a Magnetic Random Access Memory (MRAM), a phase change Random access memory (PRAM), and a Resistive Random Access Memory (RRAM). MRAM is a non-volatile magnetic Random Access Memory that has the high speed read and write capabilities of Static Random Access Memory (SRAM) and the high integration of Dynamic Random Access Memory (DRAM) and can be written to repeatedly, essentially indefinitely. PRAM is a type of memory from Samsung corporation, and compared with common DRAM and flash memory, PRAM has the characteristics of high speed and low power consumption. The RRAM enables the resistance of the material to change between a high resistance state and a low resistance state according to the difference of voltages applied to the metal oxide (MetalOxide), thereby opening or blocking a current flow channel, and using the property to store a memory of various information can significantly improve the durability and the data transmission speed.

The storage device described in the embodiment of the invention comprises at least one Printed Circuit Board (PCB) and a double data rate DDR interface, wherein a controller and storage particles are arranged on each PCB, the storage particles are connected with the controller, and the controller is connected with the DDR interface through a DDR bus; the DDR interface is arranged on one PCB, and DDR data lines in the DDR bus consist of DDR data lines corresponding to each controller. By adopting the embodiment of the invention, the DDR interface is connected with the DDR socket on the mainboard where the CPU is located, so that the storage device performs data transmission with the CPU based on the memory channel, and the transmission time delay of reading and writing data from the storage device by the system can be reduced; meanwhile, the DDR data line bit number corresponding to each controller in the storage device is smaller than the DDR data line bit number provided by the DDR socket on the mainboard where the CPU is located, the extensible design of the storage device can be achieved, and the flexibility of designing the storage device is improved.

Referring to fig. 2, fig. 2 is another schematic structural diagram of a memory device according to an embodiment of the present invention, for convenience of description, the embodiment of the present invention takes two PCBs and one controller is disposed on each PCB as an example, in the embodiment of the present invention, the memory device may include: at least one printed wiring board (101a, 101b), a double data rate interface (102), a controller (103a, 103b) and a memory chip (104a, 104 b).

Wherein, each printed circuit board (101a, 101b) is provided with a controller (103a, 103b) and a storage particle (104a, 104b), the storage particle is connected with the controller (for example, the storage particle 104a is connected with the controller 103a, and the storage particle 104b is connected with the controller 103 b); the DDR interface (102) is arranged on one PCB (101a for example), and the controllers (103a, 103b) are connected with the DDR interface (102) through a DDR bus; a controller (103a) receives a control signal sent by the CPU, and reads and/or writes target data from the storage particles (104a, 104b) according to the control signal; the DDR interface (102) is used for being connected with a DDR socket on a mainboard where the CPU is located. The DDR data lines in the DDR bus are composed of DDR data lines corresponding to each controller, and the number of the DDR data lines corresponding to each controller is smaller than the number of the DDR data lines provided by the DDR socket.

Therefore, when the storage device provided by the embodiment of the invention is used on equipment such as a computer or a server, a DDR interface in the storage device can be directly connected with a DDR socket on a mainboard where a CPU is located. Because the DDR socket on the mainboard where the CPU is located is used for connecting the memory, the storage device is connected with the CPU through the memory channel, when the CPU and the storage device carry out data transmission, the transmission time delay of the system for reading and writing data from the storage device can be effectively reduced, and the real-time performance is high when the system reads the data from the storage device.

In the embodiment of the invention, one storage device corresponds to one DDR interface, each controller is connected with the DDR interface through the DDR bus, and the controllers are arranged on the PCB, so that in the concrete implementation, if the storage device comprises one PCB, the controller on the PCB is directly connected with the DDR interface through the DDR bus; if the storage device comprises two or more than two PCBs, the two adjacent PCBs are electrically connected, the controller on one PCB is directly connected with the DDR interface through the DDR bus, and the controllers on the other PCBs are also connected with the DDR interface through the DDR bus based on the electrical connection characteristics between the PCBs (namely, the DDR control lines in the DDR interface are connected with each controller on the PCB, wherein the DDR data lines in the DDR interface are composed of DDR data lines corresponding to each controller). In the concrete implementation, the storage device comprises n Printed Circuit Boards (PCB), n is an integer, if n is larger than or equal to 2, the two adjacent PCBs are electrically connected, so that each controller on each PCB is connected with a DDR interface through a DDR bus. For convenience of understanding, for example, assuming that the memory device includes 2 PCBs (respectively described as "PCB 1" and "PCB 2"), one controller (respectively described as "controller one" and "controller two") is disposed on each PCB, the DDR data line corresponding to each controller is 8 bits (respectively described as "D1 to D8" and "D9 to D16"), and the DDR control line in the DDR bus of the DDR interface and the DDR socket is 15 bits (described as "C1 to C15"), it can be known that the DDR data line in the DDR bus of the DDR interface and the DDR socket is 16 bits and includes "D1 to D16", wherein the DDR data lines "D1 to D8" in the DDR interface are connected to the DDR data line port corresponding to "controller one", the DDR data lines "D9 to D16" in the DDR interface are connected to the DDR data line port corresponding to "controller two", the DDR data lines "C1 to C1" in the DDR interface are connected to the control line port corresponding to "controller two" control line 15 "respectively, namely, DDR buses corresponding to the controller I are D1-D8 and C1-C15, and DDR buses corresponding to the controller II are D9-D16 and C1-C15; in a specific implementation, the DDR control lines in the DDR interface may also be divided into multiple parts, for example, assuming that each part corresponds to 15 bits, the DDR control lines "C1 to C15" in the DDR interface are connected to the DDR controller ports corresponding to the "controller one", the DDR control lines "C16 to C30" in the DDR interface are connected to the DDR control line ports corresponding to the "controller two", that is, the DDR buses corresponding to the "controller one" are "D1 to D8, C1 to C15", and the DDR buses corresponding to the "controller two" are "D9 to D16, and C16 to C30". It should be noted that the above is only an example, and the specific implementation may perform equivalent or similar conversion according to actual requirements, for example, the DDR data lines corresponding to the controller are 4 bits, 16 bits, and the like, and the DDR control lines corresponding to the controller are 20 bits, 25 bits, and the like, and the embodiment of the present invention is not limited in particular. Generally, because the memory is a direct addressing mode, the system Bus based on the memory channel includes a Data Bus (Data Bus, DB), a Control Bus (CB), and an Address Bus (AB), and the addressing mode when the storage device in the embodiment of the present invention reads Data is similar to a hard disk and a CFC (Compact Flash Card), and belongs to an indirect addressing mode, therefore, the storage capacity can be made very large based on the memory channel. In a specific implementation, DDR address lines in the DDR socket may be omitted, and complexity in designing the memory device is reduced, so that the DDR interface of the memory device may include only DDR data lines and DDR control lines, and of course, may also be a set of DDR data lines, DDR control lines, and DDR address lines, and specifically, the embodiment of the present invention is not limited.

As a feasible implementation manner, if the number of the at least one printed circuit board PCB is n, n is greater than or equal to 2, and n is an integer, the storage device further includes n-1 flexible boards, two adjacent PCBs are electrically connected through the flexible boards, wherein the controllers on the two PCBs are connected through the flexible boards.

For convenience of understanding, please refer to fig. 3, fig. 3 is a schematic structural diagram of a memory device according to an embodiment of the present invention, in fig. 3, taking 2 PCBs (301a, 301b) as an example, the memory device includes a DDR interface (302), a controller (not shown in the figure) and memory particles (simplified as particles in fig. 3, such as 304a, 304b), the two PCBs (301a, 301b) are connected by a flexible board (305), and the DDR interface (302) is used for connecting with a DDR socket on a motherboard where a CPU is located, so that, except the PCB where the DDR interface is located, a DDR bus corresponding to each controller on the other PCBs may be connected to the DDR interface through the flexible board. As a feasible implementation manner, the controllers on two adjacent PCBs are connected through the flexible board, so that when a problem occurs in connection between a DDR bus corresponding to a certain controller and a DDR interface, data, control signals and the like can be transmitted through the interconnection between the controllers, and the fault tolerance of the storage device is improved. In one possible embodiment, the storage device may further include a heat dissipation material disposed between the two adjacent PCBs, considering that the two adjacent PCBs may have heat dissipation problems.

As a feasible implementation manner, if the number of the at least one printed circuit board PCB is n, n is greater than or equal to 2, and n is an integer, the storage device further includes n-1 connectors through which two adjacent PCBs are electrically connected, wherein the controllers on the two PCBs are connected through the connectors.

For convenience of understanding, please refer to fig. 3a, where fig. 3a is a schematic diagram of another structure of a memory device according to an embodiment of the present invention, and fig. 3a takes 2 PCBs (301a, 301b) as an example, the memory device includes a DDR interface (302), a controller (not shown in the figure) and memory particles (simplified as particles in fig. 3a, such as 304a, 304b), the two PCBs (301a, 301b) are connected by a connector (306), and the DDR interface (302) is used for connecting with a DDR socket on a motherboard where a CPU is located, so that, except for the PCB where the DDR interface is located, a DDR bus corresponding to each controller on the other PCBs may be connected to the DDR interface by the connector. As a feasible implementation manner, the controllers on two adjacent PCBs are connected through the connector, so that when a problem occurs in connection between a DDR bus corresponding to a certain controller and a DDR interface, data, control signals and the like can be transmitted through the interconnection between the controllers, and the fault tolerance of the storage device is improved. In one possible embodiment, the storage device may further include a heat dissipation material disposed between the two adjacent PCBs, considering that the two adjacent PCBs may have heat dissipation problems.

As a feasible implementation manner, if the number of the at least one printed circuit board PCB is n, n is greater than or equal to 2, n is an integer, the storage device further comprises n-1 PCB sub-boards, two adjacent PCBs are electrically connected through the PCB sub-boards, and the controllers on the two PCBs are connected through the PCB sub-boards.

For convenience of understanding, please refer to fig. 3b, where fig. 3b is a schematic diagram of another structure of a memory device according to an embodiment of the present invention, and fig. 3b illustrates 2 PCBs (301a, 301b), where the memory device includes a DDR interface (302), a controller (not shown in the figure) and memory particles (simplified as particles in fig. 3a, such as 304a, 304b), the two PCBs (301a, 301b) are connected through a PCB daughter board (307), and the DDR interface (302) is used for connecting with a DDR socket on a motherboard where a CPU is located, so that, except for the PCB where the DDR interface is located, a DDR bus corresponding to each controller on the other PCBs may be connected to the DDR interface through the daughter board PCB. As a feasible implementation manner, the controllers on two adjacent PCBs are connected through the PCB daughter board, so that when a problem occurs in connection between a DDR bus corresponding to a certain controller and a DDR interface, data, control signals and the like can be transmitted through interconnection between the controllers, and the fault tolerance of the storage device is improved. In one possible embodiment, the storage device may further include a heat dissipation material disposed between the two adjacent PCBs, considering that the two adjacent PCBs may have heat dissipation problems.

It should be noted that, in the embodiment of the present invention, the number of the printed circuit board and the controller is not limited, the specific number of the printed circuit board and the controller may be set according to actual requirements, the number and the unit capacity of the storage particles may also be selected according to the requirements of the storage device to be designed on the storage capacity, the size, and the like, and the embodiment of the present invention is not limited to specific details. For example, if it is desired to design a storage device with a storage capacity of 160G, 4 storage particles with a capacity of 40G may be used, 8 storage particles with a capacity of 20G may be used, and the like, however, the storage devices designed with 4 storage particles with a capacity of 40G and 8 storage particles with a capacity of 20G may have differences in size, price and performance, and therefore, the storage particles need to be selected according to actual needs in the actual processing process, which is not limited in this embodiment of the present invention.

For convenience of understanding, assuming that the number of DDR data lines corresponding to each controller is 8, and the DDR socket on the motherboard where the CPU is located is DDR4, it can be known that the DDR4 includes 288 pins, where 72 pins represent a DDR data bus, and therefore, the memory device can be designed to include 9 PCBs at most. In the specific implementation, a PCB with a proper size can be selected according to the size of the storage device to be designed, if the storage capacity of the storage device to be designed cannot be met on one PCB, the PCB is additionally arranged, the two PCBs are electrically connected, and if the storage capacity of the storage device to be designed cannot be met by the two PCBs, the PCBs are continuously additionally arranged until the design is met. Of course, in the specific implementation, factors in various aspects such as size, price, performance and the like need to be comprehensively considered, so that a storage device with large capacity, low cost and small volume is expected to be designed. For convenience of understanding, a structure of a memory device including a plurality of PCBs may be as shown in fig. 3c, and fig. 3c is a schematic view of another structure of a memory device according to an embodiment of the present invention (a controller is not shown in the drawings). Two adjacent PCBs are electrically connected through modes such as a flexible board, a connector and a PCB daughter board, and the controllers on the two adjacent PCBs are connected.

It should be noted that in a specific implementation, the DDR interface may be any memory interface matched with a DDR socket on a motherboard where the CPU is located, and at present, common memory interfaces include DDR3 and DDR 4. In the embodiment of the present invention, the DDR interface includes DDR3 and DDR4, and certainly, the DDR interface may also be DDR2 or DDR1, and the specific embodiment of the present invention is not limited.

In a feasible implementation manner, the storage device according to the embodiment of the invention may further include a housing, wherein at least one printed circuit board PCB, the controller, and the storage particles are all disposed inside the housing, if the PCBs are multiple, the flexible board, the connector, and the PCB daughter board are also disposed inside the housing, and the DDR interface is disposed in the housing, so that the storage device may be designed into a hard disk or a memory card that can be used independently, and may be directly used as a mobile hard disk, which is convenient for a user to carry.

The storage device described in the embodiment of the invention comprises at least one Printed Circuit Board (PCB) and a double data rate DDR interface, wherein a controller and storage particles are arranged on each PCB, and the storage particles are connected with the controller; the DDR interface is arranged on one PCB, the controller on the PCB is connected with the DDR interface through a DDR bus, and DDR data lines in the DDR bus consist of DDR data lines corresponding to each controller. By adopting the embodiment of the invention, the DDR interface is connected with the DDR socket on the mainboard where the CPU is located, so that the storage device performs data transmission with the CPU based on the memory channel, and the transmission time delay of reading and writing data from the storage device by the system can be reduced; meanwhile, the DDR data line bit number corresponding to each controller in the storage device is smaller than the DDR data line bit number provided by the DDR socket on the mainboard where the CPU is located, the extensible design of the storage device can be achieved, and the flexibility of designing the storage device is improved.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily for the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Those skilled in the art will be able to combine and combine features of different embodiments and features of different embodiments described in this specification. The above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions are intended to be included within the scope of the present invention without departing from the spirit and scope of the present invention.

Claims

1. A storage device is characterized by comprising at least two Printed Circuit Boards (PCBs) and a Double Data Rate (DDR) interface, wherein a controller and storage particles are placed on each PCB, the storage particles are connected with the controller, the controller is connected with the DDR interface through a DDR bus, and the DDR interface is placed on one of the PCBs; DDR data lines in the DDR bus are composed of DDR data lines corresponding to each controller; the DDR interface is used for being connected with a DDR socket on a mainboard where the CPU is located; wherein,

the DDR data line bit number corresponding to each controller is any bit number smaller than the DDR data line bit number provided by the DDR socket; and the controller receives a control signal sent by the CPU and reads and/or writes target data from the storage particles according to the control signal.

2. The memory device of claim 1, wherein the number of DDR data line bits per controller is 8 bits.

3. The memory device according to claim 1 or 2, wherein the memory particles include any one of a memory medium of a flash memory chip, a magnetic random access memory MRAM, a phase change random access memory PRAM, and a resistance change memory RRAM.

4. The memory device according to claim 1, wherein if the number of the at least two printed circuit boards is n, n is not less than 2, n is an integer, the memory device further comprises n-1 flexible boards through which two adjacent PCBs are electrically connected, wherein the controllers on the two adjacent PCBs are connected through the flexible boards.

5. The memory device according to claim 1, wherein if the number of the at least two printed circuit boards PCB is n, n is not less than 2, n is an integer, the memory device further comprises n-1 connectors through which two adjacent PCBs are electrically connected, wherein the controllers on the two adjacent PCBs are connected through the connectors.

6. The storage device according to claim 1, wherein if the number of the at least two printed circuit boards is n, n is not less than 2, n is an integer, the storage device further comprises n-1 PCB sub-boards, two adjacent PCBs are electrically connected through the PCB sub-boards, and the controllers on the two adjacent PCBs are connected through the PCB sub-boards.

7. The memory device of any one of claims 4-6, further comprising a heat sink material disposed between two adjacent PCBs.

8. The memory device of any of claims 1-2 or 4-6, wherein the DDR interface comprises DDR3 and DDR 4.

9. The memory device of claim 8, further comprising a housing, the at least two Printed Circuit Boards (PCBs), the controller, and the memory particles being disposed inside the housing, the DDR interface being disposed in the housing.

10. The memory device of claim 1, wherein the memory granule is connected to the controller through an open flash interface (ONFI) bus.